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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ngene.c: nGene PCIe bridge driver
0004  *
0005  * Copyright (C) 2005-2007 Micronas
0006  *
0007  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
0008  *                         Modifications for new nGene firmware,
0009  *                         support for EEPROM-copying,
0010  *                         support for new dual DVB-S2 card prototype
0011  */
0012 
0013 #include <linux/module.h>
0014 #include <linux/init.h>
0015 #include <linux/delay.h>
0016 #include <linux/poll.h>
0017 #include <linux/io.h>
0018 #include <asm/div64.h>
0019 #include <linux/pci.h>
0020 #include <linux/timer.h>
0021 #include <linux/byteorder/generic.h>
0022 #include <linux/firmware.h>
0023 #include <linux/vmalloc.h>
0024 
0025 #include "ngene.h"
0026 
0027 static int one_adapter;
0028 module_param(one_adapter, int, 0444);
0029 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
0030 
0031 static int shutdown_workaround;
0032 module_param(shutdown_workaround, int, 0644);
0033 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
0034 
0035 static int debug;
0036 module_param(debug, int, 0444);
0037 MODULE_PARM_DESC(debug, "Print debugging information.");
0038 
0039 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
0040 
0041 #define ngwriteb(dat, adr)         writeb((dat), dev->iomem + (adr))
0042 #define ngwritel(dat, adr)         writel((dat), dev->iomem + (adr))
0043 #define ngwriteb(dat, adr)         writeb((dat), dev->iomem + (adr))
0044 #define ngreadl(adr)               readl(dev->iomem + (adr))
0045 #define ngreadb(adr)               readb(dev->iomem + (adr))
0046 #define ngcpyto(adr, src, count)   memcpy_toio(dev->iomem + (adr), (src), (count))
0047 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count))
0048 
0049 /****************************************************************************/
0050 /* nGene interrupt handler **************************************************/
0051 /****************************************************************************/
0052 
0053 static void event_tasklet(struct tasklet_struct *t)
0054 {
0055     struct ngene *dev = from_tasklet(dev, t, event_tasklet);
0056 
0057     while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
0058         struct EVENT_BUFFER Event =
0059             dev->EventQueue[dev->EventQueueReadIndex];
0060         dev->EventQueueReadIndex =
0061             (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
0062 
0063         if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
0064             dev->TxEventNotify(dev, Event.TimeStamp);
0065         if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
0066             dev->RxEventNotify(dev, Event.TimeStamp,
0067                        Event.RXCharacter);
0068     }
0069 }
0070 
0071 static void demux_tasklet(struct tasklet_struct *t)
0072 {
0073     struct ngene_channel *chan = from_tasklet(chan, t, demux_tasklet);
0074     struct device *pdev = &chan->dev->pci_dev->dev;
0075     struct SBufferHeader *Cur = chan->nextBuffer;
0076 
0077     spin_lock_irq(&chan->state_lock);
0078 
0079     while (Cur->ngeneBuffer.SR.Flags & 0x80) {
0080         if (chan->mode & NGENE_IO_TSOUT) {
0081             u32 Flags = chan->DataFormatFlags;
0082             if (Cur->ngeneBuffer.SR.Flags & 0x20)
0083                 Flags |= BEF_OVERFLOW;
0084             if (chan->pBufferExchange) {
0085                 if (!chan->pBufferExchange(chan,
0086                                Cur->Buffer1,
0087                                chan->Capture1Length,
0088                                Cur->ngeneBuffer.SR.
0089                                Clock, Flags)) {
0090                     /*
0091                        We didn't get data
0092                        Clear in service flag to make sure we
0093                        get called on next interrupt again.
0094                        leave fill/empty (0x80) flag alone
0095                        to avoid hardware running out of
0096                        buffers during startup, we hold only
0097                        in run state ( the source may be late
0098                        delivering data )
0099                     */
0100 
0101                     if (chan->HWState == HWSTATE_RUN) {
0102                         Cur->ngeneBuffer.SR.Flags &=
0103                             ~0x40;
0104                         break;
0105                         /* Stop processing stream */
0106                     }
0107                 } else {
0108                     /* We got a valid buffer,
0109                        so switch to run state */
0110                     chan->HWState = HWSTATE_RUN;
0111                 }
0112             } else {
0113                 dev_err(pdev, "OOPS\n");
0114                 if (chan->HWState == HWSTATE_RUN) {
0115                     Cur->ngeneBuffer.SR.Flags &= ~0x40;
0116                     break;  /* Stop processing stream */
0117                 }
0118             }
0119             if (chan->AudioDTOUpdated) {
0120                 dev_info(pdev, "Update AudioDTO = %d\n",
0121                      chan->AudioDTOValue);
0122                 Cur->ngeneBuffer.SR.DTOUpdate =
0123                     chan->AudioDTOValue;
0124                 chan->AudioDTOUpdated = 0;
0125             }
0126         } else {
0127             if (chan->HWState == HWSTATE_RUN) {
0128                 u32 Flags = chan->DataFormatFlags;
0129                 IBufferExchange *exch1 = chan->pBufferExchange;
0130                 IBufferExchange *exch2 = chan->pBufferExchange2;
0131                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
0132                     Flags |= BEF_EVEN_FIELD;
0133                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
0134                     Flags |= BEF_OVERFLOW;
0135                 spin_unlock_irq(&chan->state_lock);
0136                 if (exch1)
0137                     exch1(chan, Cur->Buffer1,
0138                         chan->Capture1Length,
0139                         Cur->ngeneBuffer.SR.Clock,
0140                         Flags);
0141                 if (exch2)
0142                     exch2(chan, Cur->Buffer2,
0143                         chan->Capture2Length,
0144                         Cur->ngeneBuffer.SR.Clock,
0145                         Flags);
0146                 spin_lock_irq(&chan->state_lock);
0147             } else if (chan->HWState != HWSTATE_STOP)
0148                 chan->HWState = HWSTATE_RUN;
0149         }
0150         Cur->ngeneBuffer.SR.Flags = 0x00;
0151         Cur = Cur->Next;
0152     }
0153     chan->nextBuffer = Cur;
0154 
0155     spin_unlock_irq(&chan->state_lock);
0156 }
0157 
0158 static irqreturn_t irq_handler(int irq, void *dev_id)
0159 {
0160     struct ngene *dev = (struct ngene *)dev_id;
0161     struct device *pdev = &dev->pci_dev->dev;
0162     u32 icounts = 0;
0163     irqreturn_t rc = IRQ_NONE;
0164     u32 i = MAX_STREAM;
0165     u8 *tmpCmdDoneByte;
0166 
0167     if (dev->BootFirmware) {
0168         icounts = ngreadl(NGENE_INT_COUNTS);
0169         if (icounts != dev->icounts) {
0170             ngwritel(0, FORCE_NMI);
0171             dev->cmd_done = 1;
0172             wake_up(&dev->cmd_wq);
0173             dev->icounts = icounts;
0174             rc = IRQ_HANDLED;
0175         }
0176         return rc;
0177     }
0178 
0179     ngwritel(0, FORCE_NMI);
0180 
0181     spin_lock(&dev->cmd_lock);
0182     tmpCmdDoneByte = dev->CmdDoneByte;
0183     if (tmpCmdDoneByte &&
0184         (*tmpCmdDoneByte ||
0185         (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
0186         dev->CmdDoneByte = NULL;
0187         dev->cmd_done = 1;
0188         wake_up(&dev->cmd_wq);
0189         rc = IRQ_HANDLED;
0190     }
0191     spin_unlock(&dev->cmd_lock);
0192 
0193     if (dev->EventBuffer->EventStatus & 0x80) {
0194         u8 nextWriteIndex =
0195             (dev->EventQueueWriteIndex + 1) &
0196             (EVENT_QUEUE_SIZE - 1);
0197         if (nextWriteIndex != dev->EventQueueReadIndex) {
0198             dev->EventQueue[dev->EventQueueWriteIndex] =
0199                 *(dev->EventBuffer);
0200             dev->EventQueueWriteIndex = nextWriteIndex;
0201         } else {
0202             dev_err(pdev, "event overflow\n");
0203             dev->EventQueueOverflowCount += 1;
0204             dev->EventQueueOverflowFlag = 1;
0205         }
0206         dev->EventBuffer->EventStatus &= ~0x80;
0207         tasklet_schedule(&dev->event_tasklet);
0208         rc = IRQ_HANDLED;
0209     }
0210 
0211     while (i > 0) {
0212         i--;
0213         spin_lock(&dev->channel[i].state_lock);
0214         /* if (dev->channel[i].State>=KSSTATE_RUN) { */
0215         if (dev->channel[i].nextBuffer) {
0216             if ((dev->channel[i].nextBuffer->
0217                  ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
0218                 dev->channel[i].nextBuffer->
0219                     ngeneBuffer.SR.Flags |= 0x40;
0220                 tasklet_schedule(
0221                     &dev->channel[i].demux_tasklet);
0222                 rc = IRQ_HANDLED;
0223             }
0224         }
0225         spin_unlock(&dev->channel[i].state_lock);
0226     }
0227 
0228     /* Request might have been processed by a previous call. */
0229     return IRQ_HANDLED;
0230 }
0231 
0232 /****************************************************************************/
0233 /* nGene command interface **************************************************/
0234 /****************************************************************************/
0235 
0236 static void dump_command_io(struct ngene *dev)
0237 {
0238     struct device *pdev = &dev->pci_dev->dev;
0239     u8 buf[8], *b;
0240 
0241     ngcpyfrom(buf, HOST_TO_NGENE, 8);
0242     dev_err(pdev, "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf);
0243 
0244     ngcpyfrom(buf, NGENE_TO_HOST, 8);
0245     dev_err(pdev, "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf);
0246 
0247     b = dev->hosttongene;
0248     dev_err(pdev, "dev->hosttongene (%p): %*ph\n", b, 8, b);
0249 
0250     b = dev->ngenetohost;
0251     dev_err(pdev, "dev->ngenetohost (%p): %*ph\n", b, 8, b);
0252 }
0253 
0254 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
0255 {
0256     struct device *pdev = &dev->pci_dev->dev;
0257     int ret;
0258     u8 *tmpCmdDoneByte;
0259 
0260     dev->cmd_done = 0;
0261 
0262     if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
0263         dev->BootFirmware = 1;
0264         dev->icounts = ngreadl(NGENE_INT_COUNTS);
0265         ngwritel(0, NGENE_COMMAND);
0266         ngwritel(0, NGENE_COMMAND_HI);
0267         ngwritel(0, NGENE_STATUS);
0268         ngwritel(0, NGENE_STATUS_HI);
0269         ngwritel(0, NGENE_EVENT);
0270         ngwritel(0, NGENE_EVENT_HI);
0271     } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
0272         u64 fwio = dev->PAFWInterfaceBuffer;
0273 
0274         ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
0275         ngwritel(fwio >> 32, NGENE_COMMAND_HI);
0276         ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
0277         ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
0278         ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
0279         ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
0280     }
0281 
0282     memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
0283 
0284     if (dev->BootFirmware)
0285         ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
0286 
0287     spin_lock_irq(&dev->cmd_lock);
0288     tmpCmdDoneByte = dev->ngenetohost + com->out_len;
0289     if (!com->out_len)
0290         tmpCmdDoneByte++;
0291     *tmpCmdDoneByte = 0;
0292     dev->ngenetohost[0] = 0;
0293     dev->ngenetohost[1] = 0;
0294     dev->CmdDoneByte = tmpCmdDoneByte;
0295     spin_unlock_irq(&dev->cmd_lock);
0296 
0297     /* Notify 8051. */
0298     ngwritel(1, FORCE_INT);
0299 
0300     ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
0301     if (!ret) {
0302         /*ngwritel(0, FORCE_NMI);*/
0303 
0304         dev_err(pdev, "Command timeout cmd=%02x prev=%02x\n",
0305             com->cmd.hdr.Opcode, dev->prev_cmd);
0306         dump_command_io(dev);
0307         return -1;
0308     }
0309     if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
0310         dev->BootFirmware = 0;
0311 
0312     dev->prev_cmd = com->cmd.hdr.Opcode;
0313 
0314     if (!com->out_len)
0315         return 0;
0316 
0317     memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
0318 
0319     return 0;
0320 }
0321 
0322 int ngene_command(struct ngene *dev, struct ngene_command *com)
0323 {
0324     int result;
0325 
0326     mutex_lock(&dev->cmd_mutex);
0327     result = ngene_command_mutex(dev, com);
0328     mutex_unlock(&dev->cmd_mutex);
0329     return result;
0330 }
0331 
0332 
0333 static int ngene_command_load_firmware(struct ngene *dev,
0334                        u8 *ngene_fw, u32 size)
0335 {
0336 #define FIRSTCHUNK (1024)
0337     u32 cleft;
0338     struct ngene_command com;
0339 
0340     com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
0341     com.cmd.hdr.Length = 0;
0342     com.in_len = 0;
0343     com.out_len = 0;
0344 
0345     ngene_command(dev, &com);
0346 
0347     cleft = (size + 3) & ~3;
0348     if (cleft > FIRSTCHUNK) {
0349         ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
0350             cleft - FIRSTCHUNK);
0351         cleft = FIRSTCHUNK;
0352     }
0353     ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
0354 
0355     memset(&com, 0, sizeof(struct ngene_command));
0356     com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
0357     com.cmd.hdr.Length = 4;
0358     com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
0359     com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
0360     com.in_len = 4;
0361     com.out_len = 0;
0362 
0363     return ngene_command(dev, &com);
0364 }
0365 
0366 
0367 static int ngene_command_config_buf(struct ngene *dev, u8 config)
0368 {
0369     struct ngene_command com;
0370 
0371     com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
0372     com.cmd.hdr.Length = 1;
0373     com.cmd.ConfigureBuffers.config = config;
0374     com.in_len = 1;
0375     com.out_len = 0;
0376 
0377     if (ngene_command(dev, &com) < 0)
0378         return -EIO;
0379     return 0;
0380 }
0381 
0382 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
0383 {
0384     struct ngene_command com;
0385 
0386     com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
0387     com.cmd.hdr.Length = 6;
0388     memcpy(&com.cmd.ConfigureFreeBuffers.config, config, 6);
0389     com.in_len = 6;
0390     com.out_len = 0;
0391 
0392     if (ngene_command(dev, &com) < 0)
0393         return -EIO;
0394 
0395     return 0;
0396 }
0397 
0398 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
0399 {
0400     struct ngene_command com;
0401 
0402     com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
0403     com.cmd.hdr.Length = 1;
0404     com.cmd.SetGpioPin.select = select | (level << 7);
0405     com.in_len = 1;
0406     com.out_len = 0;
0407 
0408     return ngene_command(dev, &com);
0409 }
0410 
0411 
0412 /*
0413  02000640 is sample on rising edge.
0414  02000740 is sample on falling edge.
0415  02000040 is ignore "valid" signal
0416 
0417  0: FD_CTL1 Bit 7,6 must be 0,1
0418     7   disable(fw controlled)
0419     6   0-AUX,1-TS
0420     5   0-par,1-ser
0421     4   0-lsb/1-msb
0422     3,2 reserved
0423     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
0424  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
0425  2: FD_STA is read-only. 0-sync
0426  3: FD_INSYNC is number of 47s to trigger "in sync".
0427  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
0428  5: FD_MAXBYTE1 is low-order of bytes per packet.
0429  6: FD_MAXBYTE2 is high-order of bytes per packet.
0430  7: Top byte is unused.
0431 */
0432 
0433 /****************************************************************************/
0434 
0435 static u8 TSFeatureDecoderSetup[8 * 5] = {
0436     0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
0437     0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
0438     0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
0439     0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
0440     0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
0441 };
0442 
0443 /* Set NGENE I2S Config to 16 bit packed */
0444 static u8 I2SConfiguration[] = {
0445     0x00, 0x10, 0x00, 0x00,
0446     0x80, 0x10, 0x00, 0x00,
0447 };
0448 
0449 static u8 SPDIFConfiguration[10] = {
0450     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
0451 };
0452 
0453 /* Set NGENE I2S Config to transport stream compatible mode */
0454 
0455 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
0456 
0457 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
0458 
0459 static u8 ITUDecoderSetup[4][16] = {
0460     {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
0461      0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
0462     {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
0463      0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
0464     {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
0465      0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
0466     {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
0467      0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
0468 };
0469 
0470 /*
0471  * 50 48 60 gleich
0472  * 27p50 9f 00 22 80 42 69 18 ...
0473  * 27p60 93 00 22 80 82 69 1c ...
0474  */
0475 
0476 /* Maxbyte to 1144 (for raw data) */
0477 static u8 ITUFeatureDecoderSetup[8] = {
0478     0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
0479 };
0480 
0481 void FillTSBuffer(void *Buffer, int Length, u32 Flags)
0482 {
0483     u32 *ptr = Buffer;
0484 
0485     memset(Buffer, TS_FILLER, Length);
0486     while (Length > 0) {
0487         if (Flags & DF_SWAP32)
0488             *ptr = 0x471FFF10;
0489         else
0490             *ptr = 0x10FF1F47;
0491         ptr += (188 / 4);
0492         Length -= 188;
0493     }
0494 }
0495 
0496 
0497 static void flush_buffers(struct ngene_channel *chan)
0498 {
0499     u8 val;
0500 
0501     do {
0502         msleep(1);
0503         spin_lock_irq(&chan->state_lock);
0504         val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
0505         spin_unlock_irq(&chan->state_lock);
0506     } while (val);
0507 }
0508 
0509 static void clear_buffers(struct ngene_channel *chan)
0510 {
0511     struct SBufferHeader *Cur = chan->nextBuffer;
0512 
0513     do {
0514         memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
0515         if (chan->mode & NGENE_IO_TSOUT)
0516             FillTSBuffer(Cur->Buffer1,
0517                      chan->Capture1Length,
0518                      chan->DataFormatFlags);
0519         Cur = Cur->Next;
0520     } while (Cur != chan->nextBuffer);
0521 
0522     if (chan->mode & NGENE_IO_TSOUT) {
0523         chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
0524             chan->AudioDTOValue;
0525         chan->AudioDTOUpdated = 0;
0526 
0527         Cur = chan->TSIdleBuffer.Head;
0528 
0529         do {
0530             memset(&Cur->ngeneBuffer.SR, 0,
0531                    sizeof(Cur->ngeneBuffer.SR));
0532             FillTSBuffer(Cur->Buffer1,
0533                      chan->Capture1Length,
0534                      chan->DataFormatFlags);
0535             Cur = Cur->Next;
0536         } while (Cur != chan->TSIdleBuffer.Head);
0537     }
0538 }
0539 
0540 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
0541                     u8 control, u8 mode, u8 flags)
0542 {
0543     struct device *pdev = &dev->pci_dev->dev;
0544     struct ngene_channel *chan = &dev->channel[stream];
0545     struct ngene_command com;
0546     u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
0547     u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
0548     u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
0549     u16 BsSDO = 0x9B00;
0550 
0551     memset(&com, 0, sizeof(com));
0552     com.cmd.hdr.Opcode = CMD_CONTROL;
0553     com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
0554     com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
0555     if (chan->mode & NGENE_IO_TSOUT)
0556         com.cmd.StreamControl.Stream |= 0x07;
0557     com.cmd.StreamControl.Control = control |
0558         (flags & SFLAG_ORDER_LUMA_CHROMA);
0559     com.cmd.StreamControl.Mode = mode;
0560     com.in_len = sizeof(struct FW_STREAM_CONTROL);
0561     com.out_len = 0;
0562 
0563     dev_dbg(pdev, "Stream=%02x, Control=%02x, Mode=%02x\n",
0564         com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
0565         com.cmd.StreamControl.Mode);
0566 
0567     chan->Mode = mode;
0568 
0569     if (!(control & 0x80)) {
0570         spin_lock_irq(&chan->state_lock);
0571         if (chan->State == KSSTATE_RUN) {
0572             chan->State = KSSTATE_ACQUIRE;
0573             chan->HWState = HWSTATE_STOP;
0574             spin_unlock_irq(&chan->state_lock);
0575             if (ngene_command(dev, &com) < 0)
0576                 return -1;
0577             /* clear_buffers(chan); */
0578             flush_buffers(chan);
0579             return 0;
0580         }
0581         spin_unlock_irq(&chan->state_lock);
0582         return 0;
0583     }
0584 
0585     if (mode & SMODE_AUDIO_CAPTURE) {
0586         com.cmd.StreamControl.CaptureBlockCount =
0587             chan->Capture1Length / AUDIO_BLOCK_SIZE;
0588         com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
0589     } else if (mode & SMODE_TRANSPORT_STREAM) {
0590         com.cmd.StreamControl.CaptureBlockCount =
0591             chan->Capture1Length / TS_BLOCK_SIZE;
0592         com.cmd.StreamControl.MaxLinesPerField =
0593             chan->Capture1Length / TS_BLOCK_SIZE;
0594         com.cmd.StreamControl.Buffer_Address =
0595             chan->TSRingBuffer.PAHead;
0596         if (chan->mode & NGENE_IO_TSOUT) {
0597             com.cmd.StreamControl.BytesPerVBILine =
0598                 chan->Capture1Length / TS_BLOCK_SIZE;
0599             com.cmd.StreamControl.Stream |= 0x07;
0600         }
0601     } else {
0602         com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
0603         com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
0604         com.cmd.StreamControl.MinLinesPerField = 100;
0605         com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
0606 
0607         if (mode & SMODE_VBI_CAPTURE) {
0608             com.cmd.StreamControl.MaxVBILinesPerField =
0609                 chan->nVBILines;
0610             com.cmd.StreamControl.MinVBILinesPerField = 0;
0611             com.cmd.StreamControl.BytesPerVBILine =
0612                 chan->nBytesPerVBILine;
0613         }
0614         if (flags & SFLAG_COLORBAR)
0615             com.cmd.StreamControl.Stream |= 0x04;
0616     }
0617 
0618     spin_lock_irq(&chan->state_lock);
0619     if (mode & SMODE_AUDIO_CAPTURE) {
0620         chan->nextBuffer = chan->RingBuffer.Head;
0621         if (mode & SMODE_AUDIO_SPDIF) {
0622             com.cmd.StreamControl.SetupDataLen =
0623                 sizeof(SPDIFConfiguration);
0624             com.cmd.StreamControl.SetupDataAddr = BsSPI;
0625             memcpy(com.cmd.StreamControl.SetupData,
0626                    SPDIFConfiguration, sizeof(SPDIFConfiguration));
0627         } else {
0628             com.cmd.StreamControl.SetupDataLen = 4;
0629             com.cmd.StreamControl.SetupDataAddr = BsSDI;
0630             memcpy(com.cmd.StreamControl.SetupData,
0631                    I2SConfiguration +
0632                    4 * dev->card_info->i2s[stream], 4);
0633         }
0634     } else if (mode & SMODE_TRANSPORT_STREAM) {
0635         chan->nextBuffer = chan->TSRingBuffer.Head;
0636         if (stream >= STREAM_AUDIOIN1) {
0637             if (chan->mode & NGENE_IO_TSOUT) {
0638                 com.cmd.StreamControl.SetupDataLen =
0639                     sizeof(TS_I2SOutConfiguration);
0640                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
0641                 memcpy(com.cmd.StreamControl.SetupData,
0642                        TS_I2SOutConfiguration,
0643                        sizeof(TS_I2SOutConfiguration));
0644             } else {
0645                 com.cmd.StreamControl.SetupDataLen =
0646                     sizeof(TS_I2SConfiguration);
0647                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
0648                 memcpy(com.cmd.StreamControl.SetupData,
0649                        TS_I2SConfiguration,
0650                        sizeof(TS_I2SConfiguration));
0651             }
0652         } else {
0653             com.cmd.StreamControl.SetupDataLen = 8;
0654             com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
0655             memcpy(com.cmd.StreamControl.SetupData,
0656                    TSFeatureDecoderSetup +
0657                    8 * dev->card_info->tsf[stream], 8);
0658         }
0659     } else {
0660         chan->nextBuffer = chan->RingBuffer.Head;
0661         com.cmd.StreamControl.SetupDataLen =
0662             16 + sizeof(ITUFeatureDecoderSetup);
0663         com.cmd.StreamControl.SetupDataAddr = BsUVI;
0664         memcpy(com.cmd.StreamControl.SetupData,
0665                ITUDecoderSetup[chan->itumode], 16);
0666         memcpy(com.cmd.StreamControl.SetupData + 16,
0667                ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
0668     }
0669     clear_buffers(chan);
0670     chan->State = KSSTATE_RUN;
0671     if (mode & SMODE_TRANSPORT_STREAM)
0672         chan->HWState = HWSTATE_RUN;
0673     else
0674         chan->HWState = HWSTATE_STARTUP;
0675     spin_unlock_irq(&chan->state_lock);
0676 
0677     if (ngene_command(dev, &com) < 0)
0678         return -1;
0679 
0680     return 0;
0681 }
0682 
0683 void set_transfer(struct ngene_channel *chan, int state)
0684 {
0685     struct device *pdev = &chan->dev->pci_dev->dev;
0686     u8 control = 0, mode = 0, flags = 0;
0687     struct ngene *dev = chan->dev;
0688     int ret;
0689 
0690     /*
0691     dev_info(pdev, "st %d\n", state);
0692     msleep(100);
0693     */
0694 
0695     if (state) {
0696         if (chan->running) {
0697             dev_info(pdev, "already running\n");
0698             return;
0699         }
0700     } else {
0701         if (!chan->running) {
0702             dev_info(pdev, "already stopped\n");
0703             return;
0704         }
0705     }
0706 
0707     if (dev->card_info->switch_ctrl)
0708         dev->card_info->switch_ctrl(chan, 1, state ^ 1);
0709 
0710     if (state) {
0711         spin_lock_irq(&chan->state_lock);
0712 
0713         /* dev_info(pdev, "lock=%08x\n",
0714               ngreadl(0x9310)); */
0715         dvb_ringbuffer_flush(&dev->tsout_rbuf);
0716         control = 0x80;
0717         if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
0718             chan->Capture1Length = 512 * 188;
0719             mode = SMODE_TRANSPORT_STREAM;
0720         }
0721         if (chan->mode & NGENE_IO_TSOUT) {
0722             chan->pBufferExchange = tsout_exchange;
0723             /* 0x66666666 = 50MHz *2^33 /250MHz */
0724             chan->AudioDTOValue = 0x80000000;
0725             chan->AudioDTOUpdated = 1;
0726         }
0727         if (chan->mode & NGENE_IO_TSIN)
0728             chan->pBufferExchange = tsin_exchange;
0729         spin_unlock_irq(&chan->state_lock);
0730     }
0731         /* else dev_info(pdev, "lock=%08x\n",
0732                ngreadl(0x9310)); */
0733 
0734     mutex_lock(&dev->stream_mutex);
0735     ret = ngene_command_stream_control(dev, chan->number,
0736                        control, mode, flags);
0737     mutex_unlock(&dev->stream_mutex);
0738 
0739     if (!ret)
0740         chan->running = state;
0741     else
0742         dev_err(pdev, "%s %d failed\n", __func__, state);
0743     if (!state) {
0744         spin_lock_irq(&chan->state_lock);
0745         chan->pBufferExchange = NULL;
0746         dvb_ringbuffer_flush(&dev->tsout_rbuf);
0747         spin_unlock_irq(&chan->state_lock);
0748     }
0749 }
0750 
0751 
0752 /****************************************************************************/
0753 /* nGene hardware init and release functions ********************************/
0754 /****************************************************************************/
0755 
0756 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
0757 {
0758     struct SBufferHeader *Cur = rb->Head;
0759     u32 j;
0760 
0761     if (!Cur)
0762         return;
0763 
0764     for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
0765         if (Cur->Buffer1)
0766             dma_free_coherent(&dev->pci_dev->dev,
0767                       rb->Buffer1Length, Cur->Buffer1,
0768                       Cur->scList1->Address);
0769 
0770         if (Cur->Buffer2)
0771             dma_free_coherent(&dev->pci_dev->dev,
0772                       rb->Buffer2Length, Cur->Buffer2,
0773                       Cur->scList2->Address);
0774     }
0775 
0776     if (rb->SCListMem)
0777         dma_free_coherent(&dev->pci_dev->dev, rb->SCListMemSize,
0778                   rb->SCListMem, rb->PASCListMem);
0779 
0780     dma_free_coherent(&dev->pci_dev->dev, rb->MemSize, rb->Head,
0781               rb->PAHead);
0782 }
0783 
0784 static void free_idlebuffer(struct ngene *dev,
0785              struct SRingBufferDescriptor *rb,
0786              struct SRingBufferDescriptor *tb)
0787 {
0788     int j;
0789     struct SBufferHeader *Cur = tb->Head;
0790 
0791     if (!rb->Head)
0792         return;
0793     free_ringbuffer(dev, rb);
0794     for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
0795         Cur->Buffer2 = NULL;
0796         Cur->scList2 = NULL;
0797         Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
0798         Cur->ngeneBuffer.Number_of_entries_2 = 0;
0799     }
0800 }
0801 
0802 static void free_common_buffers(struct ngene *dev)
0803 {
0804     u32 i;
0805     struct ngene_channel *chan;
0806 
0807     for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
0808         chan = &dev->channel[i];
0809         free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
0810         free_ringbuffer(dev, &chan->RingBuffer);
0811         free_ringbuffer(dev, &chan->TSRingBuffer);
0812     }
0813 
0814     if (dev->OverflowBuffer)
0815         dma_free_coherent(&dev->pci_dev->dev, OVERFLOW_BUFFER_SIZE,
0816                   dev->OverflowBuffer, dev->PAOverflowBuffer);
0817 
0818     if (dev->FWInterfaceBuffer)
0819         dma_free_coherent(&dev->pci_dev->dev, 4096,
0820                   dev->FWInterfaceBuffer,
0821                   dev->PAFWInterfaceBuffer);
0822 }
0823 
0824 /****************************************************************************/
0825 /* Ring buffer handling *****************************************************/
0826 /****************************************************************************/
0827 
0828 static int create_ring_buffer(struct pci_dev *pci_dev,
0829                struct SRingBufferDescriptor *descr, u32 NumBuffers)
0830 {
0831     dma_addr_t tmp;
0832     struct SBufferHeader *Head;
0833     u32 i;
0834     u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
0835     u64 PARingBufferHead;
0836     u64 PARingBufferCur;
0837     u64 PARingBufferNext;
0838     struct SBufferHeader *Cur, *Next;
0839 
0840     descr->Head = NULL;
0841     descr->MemSize = 0;
0842     descr->PAHead = 0;
0843     descr->NumBuffers = 0;
0844 
0845     if (MemSize < 4096)
0846         MemSize = 4096;
0847 
0848     Head = dma_alloc_coherent(&pci_dev->dev, MemSize, &tmp, GFP_KERNEL);
0849     PARingBufferHead = tmp;
0850 
0851     if (!Head)
0852         return -ENOMEM;
0853 
0854     PARingBufferCur = PARingBufferHead;
0855     Cur = Head;
0856 
0857     for (i = 0; i < NumBuffers - 1; i++) {
0858         Next = (struct SBufferHeader *)
0859             (((u8 *) Cur) + SIZEOF_SBufferHeader);
0860         PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
0861         Cur->Next = Next;
0862         Cur->ngeneBuffer.Next = PARingBufferNext;
0863         Cur = Next;
0864         PARingBufferCur = PARingBufferNext;
0865     }
0866     /* Last Buffer points back to first one */
0867     Cur->Next = Head;
0868     Cur->ngeneBuffer.Next = PARingBufferHead;
0869 
0870     descr->Head       = Head;
0871     descr->MemSize    = MemSize;
0872     descr->PAHead     = PARingBufferHead;
0873     descr->NumBuffers = NumBuffers;
0874 
0875     return 0;
0876 }
0877 
0878 static int AllocateRingBuffers(struct pci_dev *pci_dev,
0879                    dma_addr_t of,
0880                    struct SRingBufferDescriptor *pRingBuffer,
0881                    u32 Buffer1Length, u32 Buffer2Length)
0882 {
0883     dma_addr_t tmp;
0884     u32 i, j;
0885     u32 SCListMemSize = pRingBuffer->NumBuffers
0886         * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
0887             NUM_SCATTER_GATHER_ENTRIES)
0888         * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
0889 
0890     u64 PASCListMem;
0891     struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
0892     u64 PASCListEntry;
0893     struct SBufferHeader *Cur;
0894     void *SCListMem;
0895 
0896     if (SCListMemSize < 4096)
0897         SCListMemSize = 4096;
0898 
0899     SCListMem = dma_alloc_coherent(&pci_dev->dev, SCListMemSize, &tmp,
0900                        GFP_KERNEL);
0901 
0902     PASCListMem = tmp;
0903     if (SCListMem == NULL)
0904         return -ENOMEM;
0905 
0906     pRingBuffer->SCListMem = SCListMem;
0907     pRingBuffer->PASCListMem = PASCListMem;
0908     pRingBuffer->SCListMemSize = SCListMemSize;
0909     pRingBuffer->Buffer1Length = Buffer1Length;
0910     pRingBuffer->Buffer2Length = Buffer2Length;
0911 
0912     SCListEntry = SCListMem;
0913     PASCListEntry = PASCListMem;
0914     Cur = pRingBuffer->Head;
0915 
0916     for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
0917         u64 PABuffer;
0918 
0919         void *Buffer = dma_alloc_coherent(&pci_dev->dev,
0920                           Buffer1Length, &tmp, GFP_KERNEL);
0921         PABuffer = tmp;
0922 
0923         if (Buffer == NULL)
0924             return -ENOMEM;
0925 
0926         Cur->Buffer1 = Buffer;
0927 
0928         SCListEntry->Address = PABuffer;
0929         SCListEntry->Length  = Buffer1Length;
0930 
0931         Cur->scList1 = SCListEntry;
0932         Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
0933         Cur->ngeneBuffer.Number_of_entries_1 =
0934             NUM_SCATTER_GATHER_ENTRIES;
0935 
0936         SCListEntry += 1;
0937         PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
0938 
0939 #if NUM_SCATTER_GATHER_ENTRIES > 1
0940         for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
0941             SCListEntry->Address = of;
0942             SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
0943             SCListEntry += 1;
0944             PASCListEntry +=
0945                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
0946         }
0947 #endif
0948 
0949         if (!Buffer2Length)
0950             continue;
0951 
0952         Buffer = dma_alloc_coherent(&pci_dev->dev, Buffer2Length,
0953                         &tmp, GFP_KERNEL);
0954         PABuffer = tmp;
0955 
0956         if (Buffer == NULL)
0957             return -ENOMEM;
0958 
0959         Cur->Buffer2 = Buffer;
0960 
0961         SCListEntry->Address = PABuffer;
0962         SCListEntry->Length  = Buffer2Length;
0963 
0964         Cur->scList2 = SCListEntry;
0965         Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
0966         Cur->ngeneBuffer.Number_of_entries_2 =
0967             NUM_SCATTER_GATHER_ENTRIES;
0968 
0969         SCListEntry   += 1;
0970         PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
0971 
0972 #if NUM_SCATTER_GATHER_ENTRIES > 1
0973         for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
0974             SCListEntry->Address = of;
0975             SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
0976             SCListEntry += 1;
0977             PASCListEntry +=
0978                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
0979         }
0980 #endif
0981 
0982     }
0983 
0984     return 0;
0985 }
0986 
0987 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
0988                 struct SRingBufferDescriptor *pRingBuffer)
0989 {
0990     /* Copy pointer to scatter gather list in TSRingbuffer
0991        structure for buffer 2
0992        Load number of buffer
0993     */
0994     u32 n = pRingBuffer->NumBuffers;
0995 
0996     /* Point to first buffer entry */
0997     struct SBufferHeader *Cur = pRingBuffer->Head;
0998     int i;
0999     /* Loop through all buffer and set Buffer 2 pointers to TSIdlebuffer */
1000     for (i = 0; i < n; i++) {
1001         Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1002         Cur->scList2 = pIdleBuffer->Head->scList1;
1003         Cur->ngeneBuffer.Address_of_first_entry_2 =
1004             pIdleBuffer->Head->ngeneBuffer.
1005             Address_of_first_entry_1;
1006         Cur->ngeneBuffer.Number_of_entries_2 =
1007             pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1008         Cur = Cur->Next;
1009     }
1010     return 0;
1011 }
1012 
1013 static u32 RingBufferSizes[MAX_STREAM] = {
1014     RING_SIZE_VIDEO,
1015     RING_SIZE_VIDEO,
1016     RING_SIZE_AUDIO,
1017     RING_SIZE_AUDIO,
1018     RING_SIZE_AUDIO,
1019 };
1020 
1021 static u32 Buffer1Sizes[MAX_STREAM] = {
1022     MAX_VIDEO_BUFFER_SIZE,
1023     MAX_VIDEO_BUFFER_SIZE,
1024     MAX_AUDIO_BUFFER_SIZE,
1025     MAX_AUDIO_BUFFER_SIZE,
1026     MAX_AUDIO_BUFFER_SIZE
1027 };
1028 
1029 static u32 Buffer2Sizes[MAX_STREAM] = {
1030     MAX_VBI_BUFFER_SIZE,
1031     MAX_VBI_BUFFER_SIZE,
1032     0,
1033     0,
1034     0
1035 };
1036 
1037 
1038 static int AllocCommonBuffers(struct ngene *dev)
1039 {
1040     int status = 0, i;
1041 
1042     dev->FWInterfaceBuffer = dma_alloc_coherent(&dev->pci_dev->dev, 4096,
1043                             &dev->PAFWInterfaceBuffer,
1044                             GFP_KERNEL);
1045     if (!dev->FWInterfaceBuffer)
1046         return -ENOMEM;
1047     dev->hosttongene = dev->FWInterfaceBuffer;
1048     dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1049     dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1050 
1051     dev->OverflowBuffer = dma_alloc_coherent(&dev->pci_dev->dev,
1052                          OVERFLOW_BUFFER_SIZE,
1053                          &dev->PAOverflowBuffer, GFP_KERNEL);
1054     if (!dev->OverflowBuffer)
1055         return -ENOMEM;
1056 
1057     for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1058         int type = dev->card_info->io_type[i];
1059 
1060         dev->channel[i].State = KSSTATE_STOP;
1061 
1062         if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1063             status = create_ring_buffer(dev->pci_dev,
1064                             &dev->channel[i].RingBuffer,
1065                             RingBufferSizes[i]);
1066             if (status < 0)
1067                 break;
1068 
1069             if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1070                 status = AllocateRingBuffers(dev->pci_dev,
1071                                  dev->
1072                                  PAOverflowBuffer,
1073                                  &dev->channel[i].
1074                                  RingBuffer,
1075                                  Buffer1Sizes[i],
1076                                  Buffer2Sizes[i]);
1077                 if (status < 0)
1078                     break;
1079             } else if (type & NGENE_IO_HDTV) {
1080                 status = AllocateRingBuffers(dev->pci_dev,
1081                                  dev->
1082                                  PAOverflowBuffer,
1083                                  &dev->channel[i].
1084                                  RingBuffer,
1085                                MAX_HDTV_BUFFER_SIZE,
1086                                  0);
1087                 if (status < 0)
1088                     break;
1089             }
1090         }
1091 
1092         if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1093 
1094             status = create_ring_buffer(dev->pci_dev,
1095                             &dev->channel[i].
1096                             TSRingBuffer, RING_SIZE_TS);
1097             if (status < 0)
1098                 break;
1099 
1100             status = AllocateRingBuffers(dev->pci_dev,
1101                              dev->PAOverflowBuffer,
1102                              &dev->channel[i].
1103                              TSRingBuffer,
1104                              MAX_TS_BUFFER_SIZE, 0);
1105             if (status)
1106                 break;
1107         }
1108 
1109         if (type & NGENE_IO_TSOUT) {
1110             status = create_ring_buffer(dev->pci_dev,
1111                             &dev->channel[i].
1112                             TSIdleBuffer, 1);
1113             if (status < 0)
1114                 break;
1115             status = AllocateRingBuffers(dev->pci_dev,
1116                              dev->PAOverflowBuffer,
1117                              &dev->channel[i].
1118                              TSIdleBuffer,
1119                              MAX_TS_BUFFER_SIZE, 0);
1120             if (status)
1121                 break;
1122             FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1123                      &dev->channel[i].TSRingBuffer);
1124         }
1125     }
1126     return status;
1127 }
1128 
1129 static void ngene_release_buffers(struct ngene *dev)
1130 {
1131     if (dev->iomem)
1132         iounmap(dev->iomem);
1133     free_common_buffers(dev);
1134     vfree(dev->tsout_buf);
1135     vfree(dev->tsin_buf);
1136     vfree(dev->ain_buf);
1137     vfree(dev->vin_buf);
1138     vfree(dev);
1139 }
1140 
1141 static int ngene_get_buffers(struct ngene *dev)
1142 {
1143     if (AllocCommonBuffers(dev))
1144         return -ENOMEM;
1145     if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1146         dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1147         if (!dev->tsout_buf)
1148             return -ENOMEM;
1149         dvb_ringbuffer_init(&dev->tsout_rbuf,
1150                     dev->tsout_buf, TSOUT_BUF_SIZE);
1151     }
1152     if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1153         dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1154         if (!dev->tsin_buf)
1155             return -ENOMEM;
1156         dvb_ringbuffer_init(&dev->tsin_rbuf,
1157                     dev->tsin_buf, TSIN_BUF_SIZE);
1158     }
1159     if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1160         dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1161         if (!dev->ain_buf)
1162             return -ENOMEM;
1163         dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1164     }
1165     if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1166         dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1167         if (!dev->vin_buf)
1168             return -ENOMEM;
1169         dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1170     }
1171     dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1172                  pci_resource_len(dev->pci_dev, 0));
1173     if (!dev->iomem)
1174         return -ENOMEM;
1175 
1176     return 0;
1177 }
1178 
1179 static void ngene_init(struct ngene *dev)
1180 {
1181     struct device *pdev = &dev->pci_dev->dev;
1182     int i;
1183 
1184     tasklet_setup(&dev->event_tasklet, event_tasklet);
1185 
1186     memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1187     memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1188 
1189     for (i = 0; i < MAX_STREAM; i++) {
1190         dev->channel[i].dev = dev;
1191         dev->channel[i].number = i;
1192     }
1193 
1194     dev->fw_interface_version = 0;
1195 
1196     ngwritel(0, NGENE_INT_ENABLE);
1197 
1198     dev->icounts = ngreadl(NGENE_INT_COUNTS);
1199 
1200     dev->device_version = ngreadl(DEV_VER) & 0x0f;
1201     dev_info(pdev, "Device version %d\n", dev->device_version);
1202 }
1203 
1204 static int ngene_load_firm(struct ngene *dev)
1205 {
1206     struct device *pdev = &dev->pci_dev->dev;
1207     u32 size;
1208     const struct firmware *fw = NULL;
1209     u8 *ngene_fw;
1210     char *fw_name;
1211     int err, version;
1212 
1213     version = dev->card_info->fw_version;
1214 
1215     switch (version) {
1216     default:
1217     case 15:
1218         version = 15;
1219         size = 23466;
1220         fw_name = "ngene_15.fw";
1221         dev->cmd_timeout_workaround = true;
1222         break;
1223     case 16:
1224         size = 23498;
1225         fw_name = "ngene_16.fw";
1226         dev->cmd_timeout_workaround = true;
1227         break;
1228     case 17:
1229         size = 24446;
1230         fw_name = "ngene_17.fw";
1231         dev->cmd_timeout_workaround = true;
1232         break;
1233     case 18:
1234         size = 0;
1235         fw_name = "ngene_18.fw";
1236         break;
1237     }
1238 
1239     if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1240         dev_err(pdev, "Could not load firmware file %s.\n", fw_name);
1241         dev_info(pdev, "Copy %s to your hotplug directory!\n",
1242              fw_name);
1243         return -1;
1244     }
1245     if (size == 0)
1246         size = fw->size;
1247     if (size != fw->size) {
1248         dev_err(pdev, "Firmware %s has invalid size!", fw_name);
1249         err = -1;
1250     } else {
1251         dev_info(pdev, "Loading firmware file %s.\n", fw_name);
1252         ngene_fw = (u8 *) fw->data;
1253         err = ngene_command_load_firmware(dev, ngene_fw, size);
1254     }
1255 
1256     release_firmware(fw);
1257 
1258     return err;
1259 }
1260 
1261 static void ngene_stop(struct ngene *dev)
1262 {
1263     mutex_destroy(&dev->cmd_mutex);
1264     i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1265     i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1266     ngwritel(0, NGENE_INT_ENABLE);
1267     ngwritel(0, NGENE_COMMAND);
1268     ngwritel(0, NGENE_COMMAND_HI);
1269     ngwritel(0, NGENE_STATUS);
1270     ngwritel(0, NGENE_STATUS_HI);
1271     ngwritel(0, NGENE_EVENT);
1272     ngwritel(0, NGENE_EVENT_HI);
1273     free_irq(dev->pci_dev->irq, dev);
1274 #ifdef CONFIG_PCI_MSI
1275     if (dev->msi_enabled)
1276         pci_disable_msi(dev->pci_dev);
1277 #endif
1278 }
1279 
1280 static int ngene_buffer_config(struct ngene *dev)
1281 {
1282     int stat;
1283 
1284     if (dev->card_info->fw_version >= 17) {
1285         u8 tsin12_config[6]   = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1286         u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1287         u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1288         u8 *bconf = tsin12_config;
1289 
1290         if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1291             dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1292             bconf = tsin1234_config;
1293             if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1294                 dev->ci.en)
1295                 bconf = tsio1235_config;
1296         }
1297         stat = ngene_command_config_free_buf(dev, bconf);
1298     } else {
1299         int bconf = BUFFER_CONFIG_4422;
1300 
1301         if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1302             bconf = BUFFER_CONFIG_3333;
1303         stat = ngene_command_config_buf(dev, bconf);
1304     }
1305     return stat;
1306 }
1307 
1308 
1309 static int ngene_start(struct ngene *dev)
1310 {
1311     int stat;
1312     int i;
1313 
1314     pci_set_master(dev->pci_dev);
1315     ngene_init(dev);
1316 
1317     stat = request_irq(dev->pci_dev->irq, irq_handler,
1318                IRQF_SHARED, "nGene",
1319                (void *)dev);
1320     if (stat < 0)
1321         return stat;
1322 
1323     init_waitqueue_head(&dev->cmd_wq);
1324     init_waitqueue_head(&dev->tx_wq);
1325     init_waitqueue_head(&dev->rx_wq);
1326     mutex_init(&dev->cmd_mutex);
1327     mutex_init(&dev->stream_mutex);
1328     sema_init(&dev->pll_mutex, 1);
1329     mutex_init(&dev->i2c_switch_mutex);
1330     spin_lock_init(&dev->cmd_lock);
1331     for (i = 0; i < MAX_STREAM; i++)
1332         spin_lock_init(&dev->channel[i].state_lock);
1333     ngwritel(1, TIMESTAMPS);
1334 
1335     ngwritel(1, NGENE_INT_ENABLE);
1336 
1337     stat = ngene_load_firm(dev);
1338     if (stat < 0)
1339         goto fail;
1340 
1341 #ifdef CONFIG_PCI_MSI
1342     /* enable MSI if kernel and card support it */
1343     if (pci_msi_enabled() && dev->card_info->msi_supported) {
1344         struct device *pdev = &dev->pci_dev->dev;
1345         unsigned long flags;
1346 
1347         ngwritel(0, NGENE_INT_ENABLE);
1348         free_irq(dev->pci_dev->irq, dev);
1349         stat = pci_enable_msi(dev->pci_dev);
1350         if (stat) {
1351             dev_info(pdev, "MSI not available\n");
1352             flags = IRQF_SHARED;
1353         } else {
1354             flags = 0;
1355             dev->msi_enabled = true;
1356         }
1357         stat = request_irq(dev->pci_dev->irq, irq_handler,
1358                     flags, "nGene", dev);
1359         if (stat < 0)
1360             goto fail2;
1361         ngwritel(1, NGENE_INT_ENABLE);
1362     }
1363 #endif
1364 
1365     stat = ngene_i2c_init(dev, 0);
1366     if (stat < 0)
1367         goto fail;
1368 
1369     stat = ngene_i2c_init(dev, 1);
1370     if (stat < 0)
1371         goto fail;
1372 
1373     return 0;
1374 
1375 fail:
1376     ngwritel(0, NGENE_INT_ENABLE);
1377     free_irq(dev->pci_dev->irq, dev);
1378 #ifdef CONFIG_PCI_MSI
1379 fail2:
1380     if (dev->msi_enabled)
1381         pci_disable_msi(dev->pci_dev);
1382 #endif
1383     return stat;
1384 }
1385 
1386 /****************************************************************************/
1387 /****************************************************************************/
1388 /****************************************************************************/
1389 
1390 static void release_channel(struct ngene_channel *chan)
1391 {
1392     struct dvb_demux *dvbdemux = &chan->demux;
1393     struct ngene *dev = chan->dev;
1394 
1395     if (chan->running)
1396         set_transfer(chan, 0);
1397 
1398     tasklet_kill(&chan->demux_tasklet);
1399 
1400     if (chan->ci_dev) {
1401         dvb_unregister_device(chan->ci_dev);
1402         chan->ci_dev = NULL;
1403     }
1404 
1405     if (chan->fe2)
1406         dvb_unregister_frontend(chan->fe2);
1407 
1408     if (chan->fe) {
1409         dvb_unregister_frontend(chan->fe);
1410 
1411         /* release I2C client (tuner) if needed */
1412         if (chan->i2c_client_fe) {
1413             dvb_module_release(chan->i2c_client[0]);
1414             chan->i2c_client[0] = NULL;
1415         }
1416 
1417         dvb_frontend_detach(chan->fe);
1418         chan->fe = NULL;
1419     }
1420 
1421     if (chan->has_demux) {
1422         dvb_net_release(&chan->dvbnet);
1423         dvbdemux->dmx.close(&dvbdemux->dmx);
1424         dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1425                           &chan->hw_frontend);
1426         dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1427                           &chan->mem_frontend);
1428         dvb_dmxdev_release(&chan->dmxdev);
1429         dvb_dmx_release(&chan->demux);
1430         chan->has_demux = false;
1431     }
1432 
1433     if (chan->has_adapter) {
1434         dvb_unregister_adapter(&dev->adapter[chan->number]);
1435         chan->has_adapter = false;
1436     }
1437 }
1438 
1439 static int init_channel(struct ngene_channel *chan)
1440 {
1441     int ret = 0, nr = chan->number;
1442     struct dvb_adapter *adapter = NULL;
1443     struct dvb_demux *dvbdemux = &chan->demux;
1444     struct ngene *dev = chan->dev;
1445     struct ngene_info *ni = dev->card_info;
1446     int io = ni->io_type[nr];
1447 
1448     tasklet_setup(&chan->demux_tasklet, demux_tasklet);
1449     chan->users = 0;
1450     chan->type = io;
1451     chan->mode = chan->type;    /* for now only one mode */
1452     chan->i2c_client_fe = 0;    /* be sure this is set to zero */
1453 
1454     if (io & NGENE_IO_TSIN) {
1455         chan->fe = NULL;
1456         if (ni->demod_attach[nr]) {
1457             ret = ni->demod_attach[nr](chan);
1458             if (ret < 0)
1459                 goto err;
1460         }
1461         if (chan->fe && ni->tuner_attach[nr]) {
1462             ret = ni->tuner_attach[nr](chan);
1463             if (ret < 0)
1464                 goto err;
1465         }
1466     }
1467 
1468     if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1469         return 0;
1470 
1471     if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1472         if (nr >= STREAM_AUDIOIN1)
1473             chan->DataFormatFlags = DF_SWAP32;
1474 
1475         if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1476             adapter = &dev->adapter[nr];
1477             ret = dvb_register_adapter(adapter, "nGene",
1478                            THIS_MODULE,
1479                            &chan->dev->pci_dev->dev,
1480                            adapter_nr);
1481             if (ret < 0)
1482                 goto err;
1483             if (dev->first_adapter == NULL)
1484                 dev->first_adapter = adapter;
1485             chan->has_adapter = true;
1486         } else
1487             adapter = dev->first_adapter;
1488     }
1489 
1490     if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1491         dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1492         set_transfer(chan, 1);
1493         chan->dev->channel[2].DataFormatFlags = DF_SWAP32;
1494         set_transfer(&chan->dev->channel[2], 1);
1495         dvb_register_device(adapter, &chan->ci_dev,
1496                     &ngene_dvbdev_ci, (void *) chan,
1497                     DVB_DEVICE_SEC, 0);
1498         if (!chan->ci_dev)
1499             goto err;
1500     }
1501 
1502     if (chan->fe) {
1503         if (dvb_register_frontend(adapter, chan->fe) < 0)
1504             goto err;
1505         chan->has_demux = true;
1506     }
1507     if (chan->fe2) {
1508         if (dvb_register_frontend(adapter, chan->fe2) < 0)
1509             goto err;
1510         if (chan->fe) {
1511             chan->fe2->tuner_priv = chan->fe->tuner_priv;
1512             memcpy(&chan->fe2->ops.tuner_ops,
1513                    &chan->fe->ops.tuner_ops,
1514                    sizeof(struct dvb_tuner_ops));
1515         }
1516     }
1517 
1518     if (chan->has_demux) {
1519         ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1520                           ngene_start_feed,
1521                           ngene_stop_feed, chan);
1522         ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1523                          &chan->hw_frontend,
1524                          &chan->mem_frontend, adapter);
1525         ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
1526     }
1527 
1528     return ret;
1529 
1530 err:
1531     if (chan->fe) {
1532         dvb_frontend_detach(chan->fe);
1533         chan->fe = NULL;
1534     }
1535     release_channel(chan);
1536     return 0;
1537 }
1538 
1539 static int init_channels(struct ngene *dev)
1540 {
1541     int i, j;
1542 
1543     for (i = 0; i < MAX_STREAM; i++) {
1544         dev->channel[i].number = i;
1545         if (init_channel(&dev->channel[i]) < 0) {
1546             for (j = i - 1; j >= 0; j--)
1547                 release_channel(&dev->channel[j]);
1548             return -1;
1549         }
1550     }
1551     return 0;
1552 }
1553 
1554 static const struct cxd2099_cfg cxd_cfgtmpl = {
1555     .bitrate = 62000,
1556     .polarity = 0,
1557     .clock_mode = 0,
1558 };
1559 
1560 static void cxd_attach(struct ngene *dev)
1561 {
1562     struct device *pdev = &dev->pci_dev->dev;
1563     struct ngene_ci *ci = &dev->ci;
1564     struct cxd2099_cfg cxd_cfg = cxd_cfgtmpl;
1565     struct i2c_client *client;
1566     int ret;
1567     u8 type;
1568 
1569     /* check for CXD2099AR presence before attaching */
1570     ret = ngene_port_has_cxd2099(&dev->channel[0].i2c_adapter, &type);
1571     if (!ret) {
1572         dev_dbg(pdev, "No CXD2099AR found\n");
1573         return;
1574     }
1575 
1576     if (type != 1) {
1577         dev_warn(pdev, "CXD2099AR is uninitialized!\n");
1578         return;
1579     }
1580 
1581     cxd_cfg.en = &ci->en;
1582     client = dvb_module_probe("cxd2099", NULL,
1583                   &dev->channel[0].i2c_adapter,
1584                   0x40, &cxd_cfg);
1585     if (!client)
1586         goto err;
1587 
1588     ci->dev = dev;
1589     dev->channel[0].i2c_client[0] = client;
1590     return;
1591 
1592 err:
1593     dev_err(pdev, "CXD2099AR attach failed\n");
1594     return;
1595 }
1596 
1597 static void cxd_detach(struct ngene *dev)
1598 {
1599     struct ngene_ci *ci = &dev->ci;
1600 
1601     dvb_ca_en50221_release(ci->en);
1602 
1603     dvb_module_release(dev->channel[0].i2c_client[0]);
1604     dev->channel[0].i2c_client[0] = NULL;
1605     ci->en = NULL;
1606 }
1607 
1608 /***********************************/
1609 /* workaround for shutdown failure */
1610 /***********************************/
1611 
1612 static void ngene_unlink(struct ngene *dev)
1613 {
1614     struct ngene_command com;
1615 
1616     com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1617     com.cmd.hdr.Length = 3;
1618     com.cmd.MemoryWrite.address = 0x910c;
1619     com.cmd.MemoryWrite.data = 0xff;
1620     com.in_len = 3;
1621     com.out_len = 1;
1622 
1623     mutex_lock(&dev->cmd_mutex);
1624     ngwritel(0, NGENE_INT_ENABLE);
1625     ngene_command_mutex(dev, &com);
1626     mutex_unlock(&dev->cmd_mutex);
1627 }
1628 
1629 void ngene_shutdown(struct pci_dev *pdev)
1630 {
1631     struct ngene *dev = pci_get_drvdata(pdev);
1632 
1633     if (!dev || !shutdown_workaround)
1634         return;
1635 
1636     dev_info(&pdev->dev, "shutdown workaround...\n");
1637     ngene_unlink(dev);
1638     pci_disable_device(pdev);
1639 }
1640 
1641 /****************************************************************************/
1642 /* device probe/remove calls ************************************************/
1643 /****************************************************************************/
1644 
1645 void ngene_remove(struct pci_dev *pdev)
1646 {
1647     struct ngene *dev = pci_get_drvdata(pdev);
1648     int i;
1649 
1650     tasklet_kill(&dev->event_tasklet);
1651     for (i = MAX_STREAM - 1; i >= 0; i--)
1652         release_channel(&dev->channel[i]);
1653     if (dev->ci.en)
1654         cxd_detach(dev);
1655     ngene_stop(dev);
1656     ngene_release_buffers(dev);
1657     pci_disable_device(pdev);
1658 }
1659 
1660 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1661 {
1662     struct ngene *dev;
1663     int stat = 0;
1664 
1665     if (pci_enable_device(pci_dev) < 0)
1666         return -ENODEV;
1667 
1668     dev = vzalloc(sizeof(struct ngene));
1669     if (dev == NULL) {
1670         stat = -ENOMEM;
1671         goto fail0;
1672     }
1673 
1674     dev->pci_dev = pci_dev;
1675     dev->card_info = (struct ngene_info *)id->driver_data;
1676     dev_info(&pci_dev->dev, "Found %s\n", dev->card_info->name);
1677 
1678     pci_set_drvdata(pci_dev, dev);
1679 
1680     /* Alloc buffers and start nGene */
1681     stat = ngene_get_buffers(dev);
1682     if (stat < 0)
1683         goto fail1;
1684     stat = ngene_start(dev);
1685     if (stat < 0)
1686         goto fail1;
1687 
1688     cxd_attach(dev);
1689 
1690     stat = ngene_buffer_config(dev);
1691     if (stat < 0)
1692         goto fail1;
1693 
1694 
1695     dev->i2c_current_bus = -1;
1696 
1697     /* Register DVB adapters and devices for both channels */
1698     stat = init_channels(dev);
1699     if (stat < 0)
1700         goto fail2;
1701 
1702     return 0;
1703 
1704 fail2:
1705     ngene_stop(dev);
1706 fail1:
1707     ngene_release_buffers(dev);
1708 fail0:
1709     pci_disable_device(pci_dev);
1710     return stat;
1711 }
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