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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * netup_unidvb_i2c.c
0004  *
0005  * Internal I2C bus driver for NetUP Universal Dual DVB-CI
0006  *
0007  * Copyright (C) 2014 NetUP Inc.
0008  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
0009  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/moduleparam.h>
0014 #include <linux/init.h>
0015 #include <linux/delay.h>
0016 #include "netup_unidvb.h"
0017 
0018 #define NETUP_I2C_BUS0_ADDR     0x4800
0019 #define NETUP_I2C_BUS1_ADDR     0x4840
0020 #define NETUP_I2C_TIMEOUT       1000
0021 
0022 /* twi_ctrl0_stat reg bits */
0023 #define TWI_IRQEN_COMPL 0x1
0024 #define TWI_IRQEN_ANACK 0x2
0025 #define TWI_IRQEN_DNACK 0x4
0026 #define TWI_IRQ_COMPL   (TWI_IRQEN_COMPL << 8)
0027 #define TWI_IRQ_ANACK   (TWI_IRQEN_ANACK << 8)
0028 #define TWI_IRQ_DNACK   (TWI_IRQEN_DNACK << 8)
0029 #define TWI_IRQ_TX  0x800
0030 #define TWI_IRQ_RX  0x1000
0031 #define TWI_IRQEN   (TWI_IRQEN_COMPL | TWI_IRQEN_ANACK | TWI_IRQEN_DNACK)
0032 /* twi_addr_ctrl1 reg bits*/
0033 #define TWI_TRANSFER    0x100
0034 #define TWI_NOSTOP  0x200
0035 #define TWI_SOFT_RESET  0x2000
0036 /* twi_clkdiv reg value */
0037 #define TWI_CLKDIV  156
0038 /* fifo_stat_ctrl reg bits */
0039 #define FIFO_IRQEN  0x8000
0040 #define FIFO_RESET  0x4000
0041 /* FIFO size */
0042 #define FIFO_SIZE   16
0043 
0044 struct netup_i2c_fifo_regs {
0045     union {
0046         __u8    data8;
0047         __le16  data16;
0048         __le32  data32;
0049     };
0050     __u8        padding[4];
0051     __le16      stat_ctrl;
0052 } __packed __aligned(1);
0053 
0054 struct netup_i2c_regs {
0055     __le16              clkdiv;
0056     __le16              twi_ctrl0_stat;
0057     __le16              twi_addr_ctrl1;
0058     __le16              length;
0059     __u8                padding1[8];
0060     struct netup_i2c_fifo_regs  tx_fifo;
0061     __u8                padding2[6];
0062     struct netup_i2c_fifo_regs  rx_fifo;
0063 } __packed __aligned(1);
0064 
0065 irqreturn_t netup_i2c_interrupt(struct netup_i2c *i2c)
0066 {
0067     u16 reg, tmp;
0068     unsigned long flags;
0069     irqreturn_t iret = IRQ_HANDLED;
0070 
0071     spin_lock_irqsave(&i2c->lock, flags);
0072     reg = readw(&i2c->regs->twi_ctrl0_stat);
0073     writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat);
0074     dev_dbg(i2c->adap.dev.parent,
0075         "%s(): twi_ctrl0_state 0x%x\n", __func__, reg);
0076     if ((reg & TWI_IRQEN_COMPL) != 0 && (reg & TWI_IRQ_COMPL)) {
0077         dev_dbg(i2c->adap.dev.parent,
0078             "%s(): TWI_IRQEN_COMPL\n", __func__);
0079         i2c->state = STATE_DONE;
0080         goto irq_ok;
0081     }
0082     if ((reg & TWI_IRQEN_ANACK) != 0 && (reg & TWI_IRQ_ANACK)) {
0083         dev_dbg(i2c->adap.dev.parent,
0084             "%s(): TWI_IRQEN_ANACK\n", __func__);
0085         i2c->state = STATE_ERROR;
0086         goto irq_ok;
0087     }
0088     if ((reg & TWI_IRQEN_DNACK) != 0 && (reg & TWI_IRQ_DNACK)) {
0089         dev_dbg(i2c->adap.dev.parent,
0090             "%s(): TWI_IRQEN_DNACK\n", __func__);
0091         i2c->state = STATE_ERROR;
0092         goto irq_ok;
0093     }
0094     if ((reg & TWI_IRQ_RX) != 0) {
0095         tmp = readw(&i2c->regs->rx_fifo.stat_ctrl);
0096         writew(tmp & ~FIFO_IRQEN, &i2c->regs->rx_fifo.stat_ctrl);
0097         i2c->state = STATE_WANT_READ;
0098         dev_dbg(i2c->adap.dev.parent,
0099             "%s(): want read\n", __func__);
0100         goto irq_ok;
0101     }
0102     if ((reg & TWI_IRQ_TX) != 0) {
0103         tmp = readw(&i2c->regs->tx_fifo.stat_ctrl);
0104         writew(tmp & ~FIFO_IRQEN, &i2c->regs->tx_fifo.stat_ctrl);
0105         i2c->state = STATE_WANT_WRITE;
0106         dev_dbg(i2c->adap.dev.parent,
0107             "%s(): want write\n", __func__);
0108         goto irq_ok;
0109     }
0110     dev_warn(&i2c->adap.dev, "%s(): not mine interrupt\n", __func__);
0111     iret = IRQ_NONE;
0112 irq_ok:
0113     spin_unlock_irqrestore(&i2c->lock, flags);
0114     if (iret == IRQ_HANDLED)
0115         wake_up(&i2c->wq);
0116     return iret;
0117 }
0118 
0119 static void netup_i2c_reset(struct netup_i2c *i2c)
0120 {
0121     dev_dbg(i2c->adap.dev.parent, "%s()\n", __func__);
0122     i2c->state = STATE_DONE;
0123     writew(TWI_SOFT_RESET, &i2c->regs->twi_addr_ctrl1);
0124     writew(TWI_CLKDIV, &i2c->regs->clkdiv);
0125     writew(FIFO_RESET, &i2c->regs->tx_fifo.stat_ctrl);
0126     writew(FIFO_RESET, &i2c->regs->rx_fifo.stat_ctrl);
0127     writew(0x800, &i2c->regs->tx_fifo.stat_ctrl);
0128     writew(0x800, &i2c->regs->rx_fifo.stat_ctrl);
0129 }
0130 
0131 static void netup_i2c_fifo_tx(struct netup_i2c *i2c)
0132 {
0133     u8 data;
0134     u32 fifo_space = FIFO_SIZE -
0135         (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f);
0136     u32 msg_length = i2c->msg->len - i2c->xmit_size;
0137 
0138     msg_length = (msg_length < fifo_space ? msg_length : fifo_space);
0139     while (msg_length--) {
0140         data = i2c->msg->buf[i2c->xmit_size++];
0141         writeb(data, &i2c->regs->tx_fifo.data8);
0142         dev_dbg(i2c->adap.dev.parent,
0143             "%s(): write 0x%02x\n", __func__, data);
0144     }
0145     if (i2c->xmit_size < i2c->msg->len) {
0146         dev_dbg(i2c->adap.dev.parent,
0147             "%s(): TX IRQ enabled\n", __func__);
0148         writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN,
0149             &i2c->regs->tx_fifo.stat_ctrl);
0150     }
0151 }
0152 
0153 static void netup_i2c_fifo_rx(struct netup_i2c *i2c)
0154 {
0155     u8 data;
0156     u32 fifo_size = readw(&i2c->regs->rx_fifo.stat_ctrl) & 0x3f;
0157 
0158     dev_dbg(i2c->adap.dev.parent,
0159         "%s(): RX fifo size %d\n", __func__, fifo_size);
0160     while (fifo_size--) {
0161         data = readb(&i2c->regs->rx_fifo.data8);
0162         if ((i2c->msg->flags & I2C_M_RD) != 0 &&
0163                     i2c->xmit_size < i2c->msg->len) {
0164             i2c->msg->buf[i2c->xmit_size++] = data;
0165             dev_dbg(i2c->adap.dev.parent,
0166                 "%s(): read 0x%02x\n", __func__, data);
0167         }
0168     }
0169     if (i2c->xmit_size < i2c->msg->len) {
0170         dev_dbg(i2c->adap.dev.parent,
0171             "%s(): RX IRQ enabled\n", __func__);
0172         writew(readw(&i2c->regs->rx_fifo.stat_ctrl) | FIFO_IRQEN,
0173             &i2c->regs->rx_fifo.stat_ctrl);
0174     }
0175 }
0176 
0177 static void netup_i2c_start_xfer(struct netup_i2c *i2c)
0178 {
0179     u16 rdflag = ((i2c->msg->flags & I2C_M_RD) ? 1 : 0);
0180     u16 reg = readw(&i2c->regs->twi_ctrl0_stat);
0181 
0182     writew(TWI_IRQEN | reg, &i2c->regs->twi_ctrl0_stat);
0183     writew(i2c->msg->len, &i2c->regs->length);
0184     writew(TWI_TRANSFER | (i2c->msg->addr << 1) | rdflag,
0185         &i2c->regs->twi_addr_ctrl1);
0186     dev_dbg(i2c->adap.dev.parent,
0187         "%s(): length %d twi_addr_ctrl1 0x%x twi_ctrl0_stat 0x%x\n",
0188         __func__, readw(&i2c->regs->length),
0189         readw(&i2c->regs->twi_addr_ctrl1),
0190         readw(&i2c->regs->twi_ctrl0_stat));
0191     i2c->state = STATE_WAIT;
0192     i2c->xmit_size = 0;
0193     if (!rdflag)
0194         netup_i2c_fifo_tx(i2c);
0195     else
0196         writew(FIFO_IRQEN | readw(&i2c->regs->rx_fifo.stat_ctrl),
0197             &i2c->regs->rx_fifo.stat_ctrl);
0198 }
0199 
0200 static int netup_i2c_xfer(struct i2c_adapter *adap,
0201               struct i2c_msg *msgs, int num)
0202 {
0203     unsigned long flags;
0204     int i, trans_done, res = num;
0205     struct netup_i2c *i2c = i2c_get_adapdata(adap);
0206     u16 reg;
0207 
0208     spin_lock_irqsave(&i2c->lock, flags);
0209     if (i2c->state != STATE_DONE) {
0210         dev_dbg(i2c->adap.dev.parent,
0211             "%s(): i2c->state == %d, resetting I2C\n",
0212             __func__, i2c->state);
0213         netup_i2c_reset(i2c);
0214     }
0215     dev_dbg(i2c->adap.dev.parent, "%s() num %d\n", __func__, num);
0216     for (i = 0; i < num; i++) {
0217         i2c->msg = &msgs[i];
0218         netup_i2c_start_xfer(i2c);
0219         trans_done = 0;
0220         while (!trans_done) {
0221             spin_unlock_irqrestore(&i2c->lock, flags);
0222             if (wait_event_timeout(i2c->wq,
0223                     i2c->state != STATE_WAIT,
0224                     msecs_to_jiffies(NETUP_I2C_TIMEOUT))) {
0225                 spin_lock_irqsave(&i2c->lock, flags);
0226                 switch (i2c->state) {
0227                 case STATE_WANT_READ:
0228                     netup_i2c_fifo_rx(i2c);
0229                     break;
0230                 case STATE_WANT_WRITE:
0231                     netup_i2c_fifo_tx(i2c);
0232                     break;
0233                 case STATE_DONE:
0234                     if ((i2c->msg->flags & I2C_M_RD) != 0 &&
0235                         i2c->xmit_size != i2c->msg->len)
0236                         netup_i2c_fifo_rx(i2c);
0237                     dev_dbg(i2c->adap.dev.parent,
0238                         "%s(): msg %d OK\n",
0239                         __func__, i);
0240                     trans_done = 1;
0241                     break;
0242                 case STATE_ERROR:
0243                     res = -EIO;
0244                     dev_dbg(i2c->adap.dev.parent,
0245                         "%s(): error state\n",
0246                         __func__);
0247                     goto done;
0248                 default:
0249                     dev_dbg(i2c->adap.dev.parent,
0250                         "%s(): invalid state %d\n",
0251                         __func__, i2c->state);
0252                     res = -EINVAL;
0253                     goto done;
0254                 }
0255                 if (!trans_done) {
0256                     i2c->state = STATE_WAIT;
0257                     reg = readw(
0258                         &i2c->regs->twi_ctrl0_stat);
0259                     writew(TWI_IRQEN | reg,
0260                         &i2c->regs->twi_ctrl0_stat);
0261                 }
0262                 spin_unlock_irqrestore(&i2c->lock, flags);
0263             } else {
0264                 spin_lock_irqsave(&i2c->lock, flags);
0265                 dev_dbg(i2c->adap.dev.parent,
0266                     "%s(): wait timeout\n", __func__);
0267                 res = -ETIMEDOUT;
0268                 goto done;
0269             }
0270             spin_lock_irqsave(&i2c->lock, flags);
0271         }
0272     }
0273 done:
0274     spin_unlock_irqrestore(&i2c->lock, flags);
0275     dev_dbg(i2c->adap.dev.parent, "%s(): result %d\n", __func__, res);
0276     return res;
0277 }
0278 
0279 static u32 netup_i2c_func(struct i2c_adapter *adap)
0280 {
0281     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0282 }
0283 
0284 static const struct i2c_algorithm netup_i2c_algorithm = {
0285     .master_xfer    = netup_i2c_xfer,
0286     .functionality  = netup_i2c_func,
0287 };
0288 
0289 static const struct i2c_adapter netup_i2c_adapter = {
0290     .owner      = THIS_MODULE,
0291     .name       = NETUP_UNIDVB_NAME,
0292     .class      = I2C_CLASS_HWMON | I2C_CLASS_SPD,
0293     .algo       = &netup_i2c_algorithm,
0294 };
0295 
0296 static int netup_i2c_init(struct netup_unidvb_dev *ndev, int bus_num)
0297 {
0298     int ret;
0299     struct netup_i2c *i2c;
0300 
0301     if (bus_num < 0 || bus_num > 1) {
0302         dev_err(&ndev->pci_dev->dev,
0303             "%s(): invalid bus_num %d\n", __func__, bus_num);
0304         return -EINVAL;
0305     }
0306     i2c = &ndev->i2c[bus_num];
0307     spin_lock_init(&i2c->lock);
0308     init_waitqueue_head(&i2c->wq);
0309     i2c->regs = (struct netup_i2c_regs __iomem *)(ndev->bmmio0 +
0310         (bus_num == 0 ? NETUP_I2C_BUS0_ADDR : NETUP_I2C_BUS1_ADDR));
0311     netup_i2c_reset(i2c);
0312     i2c->adap = netup_i2c_adapter;
0313     i2c->adap.dev.parent = &ndev->pci_dev->dev;
0314     i2c_set_adapdata(&i2c->adap, i2c);
0315     ret = i2c_add_adapter(&i2c->adap);
0316     if (ret)
0317         return ret;
0318     dev_info(&ndev->pci_dev->dev,
0319         "%s(): registered I2C bus %d at 0x%x\n",
0320         __func__,
0321         bus_num, (bus_num == 0 ?
0322             NETUP_I2C_BUS0_ADDR :
0323             NETUP_I2C_BUS1_ADDR));
0324     return 0;
0325 }
0326 
0327 static void netup_i2c_remove(struct netup_unidvb_dev *ndev, int bus_num)
0328 {
0329     struct netup_i2c *i2c;
0330 
0331     if (bus_num < 0 || bus_num > 1) {
0332         dev_err(&ndev->pci_dev->dev,
0333             "%s(): invalid bus number %d\n", __func__, bus_num);
0334         return;
0335     }
0336     i2c = &ndev->i2c[bus_num];
0337     netup_i2c_reset(i2c);
0338     /* remove adapter */
0339     i2c_del_adapter(&i2c->adap);
0340     dev_info(&ndev->pci_dev->dev,
0341         "netup_i2c_remove: unregistered I2C bus %d\n", bus_num);
0342 }
0343 
0344 int netup_i2c_register(struct netup_unidvb_dev *ndev)
0345 {
0346     int ret;
0347 
0348     ret = netup_i2c_init(ndev, 0);
0349     if (ret)
0350         return ret;
0351     ret = netup_i2c_init(ndev, 1);
0352     if (ret) {
0353         netup_i2c_remove(ndev, 0);
0354         return ret;
0355     }
0356     return 0;
0357 }
0358 
0359 void netup_i2c_unregister(struct netup_unidvb_dev *ndev)
0360 {
0361     netup_i2c_remove(ndev, 0);
0362     netup_i2c_remove(ndev, 1);
0363 }
0364
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