pci/dt3155/dt3155.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /***************************************************************************
0003  *   Copyright (C) 2006-2010 by Marin Mitov                                *
0004  *   mitov@issp.bas.bg                                                     *
0005  *                                                                         *
0006  *                                                                         *
0007  ***************************************************************************/
0008
0009 /*    DT3155 header file    */
0010 #ifndef _DT3155_H_
0011 #define _DT3155_H_
0012
0013 #include <linux/pci.h>
0014 #include <linux/interrupt.h>
0015 #include <media/v4l2-device.h>
0016 #include <media/v4l2-dev.h>
0017 #include <media/videobuf2-v4l2.h>
0018
0019 #define DT3155_NAME "dt3155"
0020 #define DT3155_VER_MAJ 2
0021 #define DT3155_VER_MIN 0
0022 #define DT3155_VER_EXT 0
0023 #define DT3155_VERSION  __stringify(DT3155_VER_MAJ) "."     \
0024             __stringify(DT3155_VER_MIN) "."     \
0025             __stringify(DT3155_VER_EXT)
0026
0027 /* DT3155 Base Register offsets (memory mapped) */
0028 #define EVEN_DMA_START   0x00
0029 #define ODD_DMA_START    0x0C
0030 #define EVEN_DMA_STRIDE  0x18
0031 #define ODD_DMA_STRIDE   0x24
0032 #define EVEN_PIXEL_FMT   0x30
0033 #define ODD_PIXEL_FMT    0x34
0034 #define FIFO_TRIGGER     0x38
0035 #define XFER_MODE    0x3C
0036 #define CSR1         0x40
0037 #define RETRY_WAIT_CNT   0x44
0038 #define INT_CSR      0x48
0039 #define EVEN_FLD_MASK    0x4C
0040 #define ODD_FLD_MASK     0x50
0041 #define MASK_LENGTH  0x54
0042 #define FIFO_FLAG_CNT    0x58
0043 #define IIC_CLK_DUR  0x5C
0044 #define IIC_CSR1     0x60
0045 #define IIC_CSR2     0x64
0046
0047 /*  DT3155 Internal Registers indexes (i2c/IIC mapped) */
0048 #define CSR2         0x10
0049 #define EVEN_CSR     0x11
0050 #define ODD_CSR      0x12
0051 #define CONFIG       0x13
0052 #define DT_ID        0x1F
0053 #define X_CLIP_START 0x20
0054 #define Y_CLIP_START 0x22
0055 #define X_CLIP_END   0x24
0056 #define Y_CLIP_END   0x26
0057 #define AD_ADDR      0x30
0058 #define AD_LUT       0x31
0059 #define AD_CMD       0x32
0060 #define DIG_OUT      0x40
0061 #define PM_LUT_ADDR  0x50
0062 #define PM_LUT_DATA  0x51
0063
0064 /* AD command register values  */
0065 #define AD_CMD_REG   0x00
0066 #define AD_POS_REF   0x01
0067 #define AD_NEG_REF   0x02
0068
0069 /* CSR1 bit masks */
0070 #define RANGE_EN       0x00008000
0071 #define CRPT_DIS       0x00004000
0072 #define ADDR_ERR_ODD   0x00000800
0073 #define ADDR_ERR_EVEN  0x00000400
0074 #define FLD_CRPT_ODD   0x00000200
0075 #define FLD_CRPT_EVEN  0x00000100
0076 #define FIFO_EN        0x00000080
0077 #define SRST           0x00000040
0078 #define FLD_DN_ODD     0x00000020
0079 #define FLD_DN_EVEN    0x00000010
0080 /*   These should not be used.
0081  *   Use CAP_CONT_ODD/EVEN instead
0082 #define CAP_SNGL_ODD   0x00000008
0083 #define CAP_SNGL_EVEN  0x00000004
0084 */
0085 #define CAP_CONT_ODD   0x00000002
0086 #define CAP_CONT_EVEN  0x00000001
0087
0088 /*  INT_CSR bit masks */
0089 #define FLD_START_EN     0x00000400
0090 #define FLD_END_ODD_EN   0x00000200
0091 #define FLD_END_EVEN_EN  0x00000100
0092 #define FLD_START    0x00000004
0093 #define FLD_END_ODD  0x00000002
0094 #define FLD_END_EVEN     0x00000001
0095
0096 /* IIC_CSR1 bit masks */
0097 #define DIRECT_ABORT     0x00000200
0098
0099 /* IIC_CSR2 bit masks */
0100 #define NEW_CYCLE   0x01000000
0101 #define DIR_RD      0x00010000
0102 #define IIC_READ    0x01010000
0103 #define IIC_WRITE   0x01000000
0104
0105 /* CSR2 bit masks */
0106 #define DISP_PASS     0x40
0107 #define BUSY_ODD      0x20
0108 #define BUSY_EVEN     0x10
0109 #define SYNC_PRESENT  0x08
0110 #define VT_50HZ       0x04
0111 #define SYNC_SNTL     0x02
0112 #define CHROM_FILT    0x01
0113 #define VT_60HZ       0x00
0114
0115 /* CSR_EVEN/ODD bit masks */
0116 #define CSR_ERROR   0x04
0117 #define CSR_SNGL    0x02
0118 #define CSR_DONE    0x01
0119
0120 /* CONFIG bit masks */
0121 #define PM_LUT_PGM     0x80
0122 #define PM_LUT_SEL     0x40
0123 #define CLIP_EN        0x20
0124 #define HSCALE_EN      0x10
0125 #define EXT_TRIG_UP    0x0C
0126 #define EXT_TRIG_DOWN  0x04
0127 #define ACQ_MODE_NEXT  0x02
0128 #define ACQ_MODE_ODD   0x01
0129 #define ACQ_MODE_EVEN  0x00
0130
0131 /* AD_CMD bit masks */
0132 #define VIDEO_CNL_1  0x00
0133 #define VIDEO_CNL_2  0x40
0134 #define VIDEO_CNL_3  0x80
0135 #define VIDEO_CNL_4  0xC0
0136 #define SYNC_CNL_1   0x00
0137 #define SYNC_CNL_2   0x10
0138 #define SYNC_CNL_3   0x20
0139 #define SYNC_CNL_4   0x30
0140 #define SYNC_LVL_1   0x00
0141 #define SYNC_LVL_2   0x04
0142 #define SYNC_LVL_3   0x08
0143 #define SYNC_LVL_4   0x0C
0144
0145 /* DT3155 identificator */
0146 #define DT3155_ID   0x20
0147
0148 /*    per board private data structure   */
0149 /**
0150  * struct dt3155_priv - private data structure
0151  *
0152  * @v4l2_dev:       v4l2_device structure
0153  * @vdev:       video_device structure
0154  * @pdev:       pointer to pci_dev structure
0155  * @vidq:       vb2_queue structure
0156  * @curr_buf:       pointer to curren buffer
0157  * @mux:        mutex to protect the instance
0158  * @dmaq:       queue for dma buffers
0159  * @lock:       spinlock for dma queue
0160  * @std:        input standard
0161  * @width:      frame width
0162  * @height:     frame height
0163  * @input:      current input
0164  * @sequence:       frame counter
0165  * @stats:      statistics structure
0166  * @regs:       local copy of mmio base register
0167  * @csr2:       local copy of csr2 register
0168  * @config:     local copy of config register
0169  */
0170 struct dt3155_priv {
0171     struct v4l2_device v4l2_dev;
0172     struct video_device vdev;
0173     struct pci_dev *pdev;
0174     struct vb2_queue vidq;
0175     struct vb2_v4l2_buffer *curr_buf;
0176     struct mutex mux;
0177     struct list_head dmaq;
0178     spinlock_t lock;
0179     v4l2_std_id std;
0180     unsigned width, height;
0181     unsigned input;
0182     unsigned int sequence;
0183     void __iomem *regs;
0184     u8 csr2, config;
0185 };
0186
0187 #endif /*  _DT3155_H_  */