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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Driver for the Conexant CX25821 PCIe bridge
0004  *
0005  *  Copyright (C) 2009 Conexant Systems Inc.
0006  *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
0007  *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
0008  */
0009 
0010 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0011 
0012 #include <linux/i2c.h>
0013 #include <linux/slab.h>
0014 #include "cx25821.h"
0015 #include "cx25821-sram.h"
0016 #include "cx25821-video.h"
0017 
0018 MODULE_DESCRIPTION("Driver for Athena cards");
0019 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
0020 MODULE_LICENSE("GPL");
0021 
0022 static unsigned int debug;
0023 module_param(debug, int, 0644);
0024 MODULE_PARM_DESC(debug, "enable debug messages");
0025 
0026 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
0027 module_param_array(card, int, NULL, 0444);
0028 MODULE_PARM_DESC(card, "card type");
0029 
0030 const struct sram_channel cx25821_sram_channels[] = {
0031     [SRAM_CH00] = {
0032         .i = SRAM_CH00,
0033         .name = "VID A",
0034         .cmds_start = VID_A_DOWN_CMDS,
0035         .ctrl_start = VID_A_IQ,
0036         .cdt = VID_A_CDT,
0037         .fifo_start = VID_A_DOWN_CLUSTER_1,
0038         .fifo_size = (VID_CLUSTER_SIZE << 2),
0039         .ptr1_reg = DMA1_PTR1,
0040         .ptr2_reg = DMA1_PTR2,
0041         .cnt1_reg = DMA1_CNT1,
0042         .cnt2_reg = DMA1_CNT2,
0043         .int_msk = VID_A_INT_MSK,
0044         .int_stat = VID_A_INT_STAT,
0045         .int_mstat = VID_A_INT_MSTAT,
0046         .dma_ctl = VID_DST_A_DMA_CTL,
0047         .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
0048         .gpcnt = VID_DST_A_GPCNT,
0049         .vip_ctl = VID_DST_A_VIP_CTL,
0050         .pix_frmt = VID_DST_A_PIX_FRMT,
0051     },
0052 
0053     [SRAM_CH01] = {
0054         .i = SRAM_CH01,
0055         .name = "VID B",
0056         .cmds_start = VID_B_DOWN_CMDS,
0057         .ctrl_start = VID_B_IQ,
0058         .cdt = VID_B_CDT,
0059         .fifo_start = VID_B_DOWN_CLUSTER_1,
0060         .fifo_size = (VID_CLUSTER_SIZE << 2),
0061         .ptr1_reg = DMA2_PTR1,
0062         .ptr2_reg = DMA2_PTR2,
0063         .cnt1_reg = DMA2_CNT1,
0064         .cnt2_reg = DMA2_CNT2,
0065         .int_msk = VID_B_INT_MSK,
0066         .int_stat = VID_B_INT_STAT,
0067         .int_mstat = VID_B_INT_MSTAT,
0068         .dma_ctl = VID_DST_B_DMA_CTL,
0069         .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
0070         .gpcnt = VID_DST_B_GPCNT,
0071         .vip_ctl = VID_DST_B_VIP_CTL,
0072         .pix_frmt = VID_DST_B_PIX_FRMT,
0073     },
0074 
0075     [SRAM_CH02] = {
0076         .i = SRAM_CH02,
0077         .name = "VID C",
0078         .cmds_start = VID_C_DOWN_CMDS,
0079         .ctrl_start = VID_C_IQ,
0080         .cdt = VID_C_CDT,
0081         .fifo_start = VID_C_DOWN_CLUSTER_1,
0082         .fifo_size = (VID_CLUSTER_SIZE << 2),
0083         .ptr1_reg = DMA3_PTR1,
0084         .ptr2_reg = DMA3_PTR2,
0085         .cnt1_reg = DMA3_CNT1,
0086         .cnt2_reg = DMA3_CNT2,
0087         .int_msk = VID_C_INT_MSK,
0088         .int_stat = VID_C_INT_STAT,
0089         .int_mstat = VID_C_INT_MSTAT,
0090         .dma_ctl = VID_DST_C_DMA_CTL,
0091         .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
0092         .gpcnt = VID_DST_C_GPCNT,
0093         .vip_ctl = VID_DST_C_VIP_CTL,
0094         .pix_frmt = VID_DST_C_PIX_FRMT,
0095     },
0096 
0097     [SRAM_CH03] = {
0098         .i = SRAM_CH03,
0099         .name = "VID D",
0100         .cmds_start = VID_D_DOWN_CMDS,
0101         .ctrl_start = VID_D_IQ,
0102         .cdt = VID_D_CDT,
0103         .fifo_start = VID_D_DOWN_CLUSTER_1,
0104         .fifo_size = (VID_CLUSTER_SIZE << 2),
0105         .ptr1_reg = DMA4_PTR1,
0106         .ptr2_reg = DMA4_PTR2,
0107         .cnt1_reg = DMA4_CNT1,
0108         .cnt2_reg = DMA4_CNT2,
0109         .int_msk = VID_D_INT_MSK,
0110         .int_stat = VID_D_INT_STAT,
0111         .int_mstat = VID_D_INT_MSTAT,
0112         .dma_ctl = VID_DST_D_DMA_CTL,
0113         .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
0114         .gpcnt = VID_DST_D_GPCNT,
0115         .vip_ctl = VID_DST_D_VIP_CTL,
0116         .pix_frmt = VID_DST_D_PIX_FRMT,
0117     },
0118 
0119     [SRAM_CH04] = {
0120         .i = SRAM_CH04,
0121         .name = "VID E",
0122         .cmds_start = VID_E_DOWN_CMDS,
0123         .ctrl_start = VID_E_IQ,
0124         .cdt = VID_E_CDT,
0125         .fifo_start = VID_E_DOWN_CLUSTER_1,
0126         .fifo_size = (VID_CLUSTER_SIZE << 2),
0127         .ptr1_reg = DMA5_PTR1,
0128         .ptr2_reg = DMA5_PTR2,
0129         .cnt1_reg = DMA5_CNT1,
0130         .cnt2_reg = DMA5_CNT2,
0131         .int_msk = VID_E_INT_MSK,
0132         .int_stat = VID_E_INT_STAT,
0133         .int_mstat = VID_E_INT_MSTAT,
0134         .dma_ctl = VID_DST_E_DMA_CTL,
0135         .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
0136         .gpcnt = VID_DST_E_GPCNT,
0137         .vip_ctl = VID_DST_E_VIP_CTL,
0138         .pix_frmt = VID_DST_E_PIX_FRMT,
0139     },
0140 
0141     [SRAM_CH05] = {
0142         .i = SRAM_CH05,
0143         .name = "VID F",
0144         .cmds_start = VID_F_DOWN_CMDS,
0145         .ctrl_start = VID_F_IQ,
0146         .cdt = VID_F_CDT,
0147         .fifo_start = VID_F_DOWN_CLUSTER_1,
0148         .fifo_size = (VID_CLUSTER_SIZE << 2),
0149         .ptr1_reg = DMA6_PTR1,
0150         .ptr2_reg = DMA6_PTR2,
0151         .cnt1_reg = DMA6_CNT1,
0152         .cnt2_reg = DMA6_CNT2,
0153         .int_msk = VID_F_INT_MSK,
0154         .int_stat = VID_F_INT_STAT,
0155         .int_mstat = VID_F_INT_MSTAT,
0156         .dma_ctl = VID_DST_F_DMA_CTL,
0157         .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
0158         .gpcnt = VID_DST_F_GPCNT,
0159         .vip_ctl = VID_DST_F_VIP_CTL,
0160         .pix_frmt = VID_DST_F_PIX_FRMT,
0161     },
0162 
0163     [SRAM_CH06] = {
0164         .i = SRAM_CH06,
0165         .name = "VID G",
0166         .cmds_start = VID_G_DOWN_CMDS,
0167         .ctrl_start = VID_G_IQ,
0168         .cdt = VID_G_CDT,
0169         .fifo_start = VID_G_DOWN_CLUSTER_1,
0170         .fifo_size = (VID_CLUSTER_SIZE << 2),
0171         .ptr1_reg = DMA7_PTR1,
0172         .ptr2_reg = DMA7_PTR2,
0173         .cnt1_reg = DMA7_CNT1,
0174         .cnt2_reg = DMA7_CNT2,
0175         .int_msk = VID_G_INT_MSK,
0176         .int_stat = VID_G_INT_STAT,
0177         .int_mstat = VID_G_INT_MSTAT,
0178         .dma_ctl = VID_DST_G_DMA_CTL,
0179         .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
0180         .gpcnt = VID_DST_G_GPCNT,
0181         .vip_ctl = VID_DST_G_VIP_CTL,
0182         .pix_frmt = VID_DST_G_PIX_FRMT,
0183     },
0184 
0185     [SRAM_CH07] = {
0186         .i = SRAM_CH07,
0187         .name = "VID H",
0188         .cmds_start = VID_H_DOWN_CMDS,
0189         .ctrl_start = VID_H_IQ,
0190         .cdt = VID_H_CDT,
0191         .fifo_start = VID_H_DOWN_CLUSTER_1,
0192         .fifo_size = (VID_CLUSTER_SIZE << 2),
0193         .ptr1_reg = DMA8_PTR1,
0194         .ptr2_reg = DMA8_PTR2,
0195         .cnt1_reg = DMA8_CNT1,
0196         .cnt2_reg = DMA8_CNT2,
0197         .int_msk = VID_H_INT_MSK,
0198         .int_stat = VID_H_INT_STAT,
0199         .int_mstat = VID_H_INT_MSTAT,
0200         .dma_ctl = VID_DST_H_DMA_CTL,
0201         .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
0202         .gpcnt = VID_DST_H_GPCNT,
0203         .vip_ctl = VID_DST_H_VIP_CTL,
0204         .pix_frmt = VID_DST_H_PIX_FRMT,
0205     },
0206 
0207     [SRAM_CH08] = {
0208         .name = "audio from",
0209         .cmds_start = AUD_A_DOWN_CMDS,
0210         .ctrl_start = AUD_A_IQ,
0211         .cdt = AUD_A_CDT,
0212         .fifo_start = AUD_A_DOWN_CLUSTER_1,
0213         .fifo_size = AUDIO_CLUSTER_SIZE * 3,
0214         .ptr1_reg = DMA17_PTR1,
0215         .ptr2_reg = DMA17_PTR2,
0216         .cnt1_reg = DMA17_CNT1,
0217         .cnt2_reg = DMA17_CNT2,
0218     },
0219 
0220     [SRAM_CH09] = {
0221         .i = SRAM_CH09,
0222         .name = "VID Upstream I",
0223         .cmds_start = VID_I_UP_CMDS,
0224         .ctrl_start = VID_I_IQ,
0225         .cdt = VID_I_CDT,
0226         .fifo_start = VID_I_UP_CLUSTER_1,
0227         .fifo_size = (VID_CLUSTER_SIZE << 2),
0228         .ptr1_reg = DMA15_PTR1,
0229         .ptr2_reg = DMA15_PTR2,
0230         .cnt1_reg = DMA15_CNT1,
0231         .cnt2_reg = DMA15_CNT2,
0232         .int_msk = VID_I_INT_MSK,
0233         .int_stat = VID_I_INT_STAT,
0234         .int_mstat = VID_I_INT_MSTAT,
0235         .dma_ctl = VID_SRC_I_DMA_CTL,
0236         .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
0237         .gpcnt = VID_SRC_I_GPCNT,
0238 
0239         .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
0240         .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
0241         .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
0242         .vid_cdt_size = VID_SRC_I_CDT_SZ,
0243         .irq_bit = 8,
0244     },
0245 
0246     [SRAM_CH10] = {
0247         .i = SRAM_CH10,
0248         .name = "VID Upstream J",
0249         .cmds_start = VID_J_UP_CMDS,
0250         .ctrl_start = VID_J_IQ,
0251         .cdt = VID_J_CDT,
0252         .fifo_start = VID_J_UP_CLUSTER_1,
0253         .fifo_size = (VID_CLUSTER_SIZE << 2),
0254         .ptr1_reg = DMA16_PTR1,
0255         .ptr2_reg = DMA16_PTR2,
0256         .cnt1_reg = DMA16_CNT1,
0257         .cnt2_reg = DMA16_CNT2,
0258         .int_msk = VID_J_INT_MSK,
0259         .int_stat = VID_J_INT_STAT,
0260         .int_mstat = VID_J_INT_MSTAT,
0261         .dma_ctl = VID_SRC_J_DMA_CTL,
0262         .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
0263         .gpcnt = VID_SRC_J_GPCNT,
0264 
0265         .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
0266         .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
0267         .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
0268         .vid_cdt_size = VID_SRC_J_CDT_SZ,
0269         .irq_bit = 9,
0270     },
0271 
0272     [SRAM_CH11] = {
0273         .i = SRAM_CH11,
0274         .name = "Audio Upstream Channel B",
0275         .cmds_start = AUD_B_UP_CMDS,
0276         .ctrl_start = AUD_B_IQ,
0277         .cdt = AUD_B_CDT,
0278         .fifo_start = AUD_B_UP_CLUSTER_1,
0279         .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
0280         .ptr1_reg = DMA22_PTR1,
0281         .ptr2_reg = DMA22_PTR2,
0282         .cnt1_reg = DMA22_CNT1,
0283         .cnt2_reg = DMA22_CNT2,
0284         .int_msk = AUD_B_INT_MSK,
0285         .int_stat = AUD_B_INT_STAT,
0286         .int_mstat = AUD_B_INT_MSTAT,
0287         .dma_ctl = AUD_INT_DMA_CTL,
0288         .gpcnt_ctl = AUD_B_GPCNT_CTL,
0289         .gpcnt = AUD_B_GPCNT,
0290         .aud_length = AUD_B_LNGTH,
0291         .aud_cfg = AUD_B_CFG,
0292         .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
0293         .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
0294         .irq_bit = 11,
0295     },
0296 };
0297 EXPORT_SYMBOL(cx25821_sram_channels);
0298 
0299 static int cx25821_risc_decode(u32 risc)
0300 {
0301     static const char * const instr[16] = {
0302         [RISC_SYNC >> 28] = "sync",
0303         [RISC_WRITE >> 28] = "write",
0304         [RISC_WRITEC >> 28] = "writec",
0305         [RISC_READ >> 28] = "read",
0306         [RISC_READC >> 28] = "readc",
0307         [RISC_JUMP >> 28] = "jump",
0308         [RISC_SKIP >> 28] = "skip",
0309         [RISC_WRITERM >> 28] = "writerm",
0310         [RISC_WRITECM >> 28] = "writecm",
0311         [RISC_WRITECR >> 28] = "writecr",
0312     };
0313     static const int incr[16] = {
0314         [RISC_WRITE >> 28] = 3,
0315         [RISC_JUMP >> 28] = 3,
0316         [RISC_SKIP >> 28] = 1,
0317         [RISC_SYNC >> 28] = 1,
0318         [RISC_WRITERM >> 28] = 3,
0319         [RISC_WRITECM >> 28] = 3,
0320         [RISC_WRITECR >> 28] = 4,
0321     };
0322     static const char * const bits[] = {
0323         "12", "13", "14", "resync",
0324         "cnt0", "cnt1", "18", "19",
0325         "20", "21", "22", "23",
0326         "irq1", "irq2", "eol", "sol",
0327     };
0328     int i;
0329 
0330     pr_cont("0x%08x [ %s",
0331         risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
0332     for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
0333         if (risc & (1 << (i + 12)))
0334             pr_cont(" %s", bits[i]);
0335     }
0336     pr_cont(" count=%d ]\n", risc & 0xfff);
0337     return incr[risc >> 28] ? incr[risc >> 28] : 1;
0338 }
0339 
0340 static void cx25821_registers_init(struct cx25821_dev *dev)
0341 {
0342     u32 tmp;
0343 
0344     /* enable RUN_RISC in Pecos */
0345     cx_write(DEV_CNTRL2, 0x20);
0346 
0347     /* Set the master PCI interrupt masks to enable video, audio, MBIF,
0348      * and GPIO interrupts
0349      * I2C interrupt masking is handled by the I2C objects themselves. */
0350     cx_write(PCI_INT_MSK, 0x2001FFFF);
0351 
0352     tmp = cx_read(RDR_TLCTL0);
0353     tmp &= ~FLD_CFG_RCB_CK_EN;  /* Clear the RCB_CK_EN bit */
0354     cx_write(RDR_TLCTL0, tmp);
0355 
0356     /* PLL-A setting for the Audio Master Clock */
0357     cx_write(PLL_A_INT_FRAC, 0x9807A58B);
0358 
0359     /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
0360     cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
0361 
0362     /* clear reset bit [31] */
0363     tmp = cx_read(PLL_A_INT_FRAC);
0364     cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
0365 
0366     /* PLL-B setting for Mobilygen Host Bus Interface */
0367     cx_write(PLL_B_INT_FRAC, 0x9883A86F);
0368 
0369     /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
0370     cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
0371 
0372     /* clear reset bit [31] */
0373     tmp = cx_read(PLL_B_INT_FRAC);
0374     cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
0375 
0376     /* PLL-C setting for video upstream channel */
0377     cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
0378 
0379     /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
0380     cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
0381 
0382     /* clear reset bit [31] */
0383     tmp = cx_read(PLL_C_INT_FRAC);
0384     cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
0385 
0386     /* PLL-D setting for audio upstream channel */
0387     cx_write(PLL_D_INT_FRAC, 0x98757F5B);
0388 
0389     /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
0390     cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
0391 
0392     /* clear reset bit [31] */
0393     tmp = cx_read(PLL_D_INT_FRAC);
0394     cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
0395 
0396     /* This selects the PLL C clock source for the video upstream channel
0397      * I and J */
0398     tmp = cx_read(VID_CH_CLK_SEL);
0399     cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
0400 
0401     /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
0402      * channel A-C
0403      * select 656/VIP DST for downstream Channel A - C */
0404     tmp = cx_read(VID_CH_MODE_SEL);
0405     /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
0406     cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
0407 
0408     /* enables 656 port I and J as output */
0409     tmp = cx_read(CLK_RST);
0410     /* use external ALT_PLL_REF pin as its reference clock instead */
0411     tmp |= FLD_USE_ALT_PLL_REF;
0412     cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
0413 
0414     msleep(100);
0415 }
0416 
0417 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
0418                    const struct sram_channel *ch,
0419                    unsigned int bpl, u32 risc)
0420 {
0421     unsigned int i, lines;
0422     u32 cdt;
0423 
0424     if (ch->cmds_start == 0) {
0425         cx_write(ch->ptr1_reg, 0);
0426         cx_write(ch->ptr2_reg, 0);
0427         cx_write(ch->cnt2_reg, 0);
0428         cx_write(ch->cnt1_reg, 0);
0429         return 0;
0430     }
0431 
0432     bpl = (bpl + 7) & ~7;   /* alignment */
0433     cdt = ch->cdt;
0434     lines = ch->fifo_size / bpl;
0435 
0436     if (lines > 4)
0437         lines = 4;
0438 
0439     BUG_ON(lines < 2);
0440 
0441     cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
0442     cx_write(8 + 4, 8);
0443     cx_write(8 + 8, 0);
0444 
0445     /* write CDT */
0446     for (i = 0; i < lines; i++) {
0447         cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
0448         cx_write(cdt + 16 * i + 4, 0);
0449         cx_write(cdt + 16 * i + 8, 0);
0450         cx_write(cdt + 16 * i + 12, 0);
0451     }
0452 
0453     /* init the first cdt buffer */
0454     for (i = 0; i < 128; i++)
0455         cx_write(ch->fifo_start + 4 * i, i);
0456 
0457     /* write CMDS */
0458     if (ch->jumponly)
0459         cx_write(ch->cmds_start + 0, 8);
0460     else
0461         cx_write(ch->cmds_start + 0, risc);
0462 
0463     cx_write(ch->cmds_start + 4, 0);    /* 64 bits 63-32 */
0464     cx_write(ch->cmds_start + 8, cdt);
0465     cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
0466     cx_write(ch->cmds_start + 16, ch->ctrl_start);
0467 
0468     if (ch->jumponly)
0469         cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
0470     else
0471         cx_write(ch->cmds_start + 20, 64 >> 2);
0472 
0473     for (i = 24; i < 80; i += 4)
0474         cx_write(ch->cmds_start + i, 0);
0475 
0476     /* fill registers */
0477     cx_write(ch->ptr1_reg, ch->fifo_start);
0478     cx_write(ch->ptr2_reg, cdt);
0479     cx_write(ch->cnt2_reg, (lines * 16) >> 3);
0480     cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
0481 
0482     return 0;
0483 }
0484 
0485 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
0486                      const struct sram_channel *ch,
0487                      unsigned int bpl, u32 risc)
0488 {
0489     unsigned int i, lines;
0490     u32 cdt;
0491 
0492     if (ch->cmds_start == 0) {
0493         cx_write(ch->ptr1_reg, 0);
0494         cx_write(ch->ptr2_reg, 0);
0495         cx_write(ch->cnt2_reg, 0);
0496         cx_write(ch->cnt1_reg, 0);
0497         return 0;
0498     }
0499 
0500     bpl = (bpl + 7) & ~7;   /* alignment */
0501     cdt = ch->cdt;
0502     lines = ch->fifo_size / bpl;
0503 
0504     if (lines > 3)
0505         lines = 3;  /* for AUDIO */
0506 
0507     BUG_ON(lines < 2);
0508 
0509     cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
0510     cx_write(8 + 4, 8);
0511     cx_write(8 + 8, 0);
0512 
0513     /* write CDT */
0514     for (i = 0; i < lines; i++) {
0515         cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
0516         cx_write(cdt + 16 * i + 4, 0);
0517         cx_write(cdt + 16 * i + 8, 0);
0518         cx_write(cdt + 16 * i + 12, 0);
0519     }
0520 
0521     /* write CMDS */
0522     if (ch->jumponly)
0523         cx_write(ch->cmds_start + 0, 8);
0524     else
0525         cx_write(ch->cmds_start + 0, risc);
0526 
0527     cx_write(ch->cmds_start + 4, 0);    /* 64 bits 63-32 */
0528     cx_write(ch->cmds_start + 8, cdt);
0529     cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
0530     cx_write(ch->cmds_start + 16, ch->ctrl_start);
0531 
0532     /* IQ size */
0533     if (ch->jumponly)
0534         cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
0535     else
0536         cx_write(ch->cmds_start + 20, 64 >> 2);
0537 
0538     /* zero out */
0539     for (i = 24; i < 80; i += 4)
0540         cx_write(ch->cmds_start + i, 0);
0541 
0542     /* fill registers */
0543     cx_write(ch->ptr1_reg, ch->fifo_start);
0544     cx_write(ch->ptr2_reg, cdt);
0545     cx_write(ch->cnt2_reg, (lines * 16) >> 3);
0546     cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
0547 
0548     return 0;
0549 }
0550 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
0551 
0552 void cx25821_sram_channel_dump(struct cx25821_dev *dev, const struct sram_channel *ch)
0553 {
0554     static char *name[] = {
0555         "init risc lo",
0556         "init risc hi",
0557         "cdt base",
0558         "cdt size",
0559         "iq base",
0560         "iq size",
0561         "risc pc lo",
0562         "risc pc hi",
0563         "iq wr ptr",
0564         "iq rd ptr",
0565         "cdt current",
0566         "pci target lo",
0567         "pci target hi",
0568         "line / byte",
0569     };
0570     u32 risc;
0571     unsigned int i, j, n;
0572 
0573     pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
0574     for (i = 0; i < ARRAY_SIZE(name); i++)
0575         pr_warn("cmds + 0x%2x:   %-15s: 0x%08x\n",
0576             i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
0577 
0578     j = i * 4;
0579     for (i = 0; i < 4;) {
0580         risc = cx_read(ch->cmds_start + 4 * (i + 14));
0581         pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
0582         i += cx25821_risc_decode(risc);
0583     }
0584 
0585     for (i = 0; i < (64 >> 2); i += n) {
0586         risc = cx_read(ch->ctrl_start + 4 * i);
0587         /* No consideration for bits 63-32 */
0588 
0589         pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
0590             i * 4, ch->ctrl_start + 4 * i, i);
0591         n = cx25821_risc_decode(risc);
0592         for (j = 1; j < n; j++) {
0593             risc = cx_read(ch->ctrl_start + 4 * (i + j));
0594             pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
0595                 4 * (i + j), i + j, risc, j);
0596         }
0597     }
0598 
0599     pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
0600         ch->fifo_start, ch->fifo_start + ch->fifo_size);
0601     pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
0602         ch->ctrl_start, ch->ctrl_start + 6 * 16);
0603     pr_warn("        :   ptr1_reg: 0x%08x\n",
0604         cx_read(ch->ptr1_reg));
0605     pr_warn("        :   ptr2_reg: 0x%08x\n",
0606         cx_read(ch->ptr2_reg));
0607     pr_warn("        :   cnt1_reg: 0x%08x\n",
0608         cx_read(ch->cnt1_reg));
0609     pr_warn("        :   cnt2_reg: 0x%08x\n",
0610         cx_read(ch->cnt2_reg));
0611 }
0612 
0613 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
0614                      const struct sram_channel *ch)
0615 {
0616     static const char * const name[] = {
0617         "init risc lo",
0618         "init risc hi",
0619         "cdt base",
0620         "cdt size",
0621         "iq base",
0622         "iq size",
0623         "risc pc lo",
0624         "risc pc hi",
0625         "iq wr ptr",
0626         "iq rd ptr",
0627         "cdt current",
0628         "pci target lo",
0629         "pci target hi",
0630         "line / byte",
0631     };
0632 
0633     u32 risc, value, tmp;
0634     unsigned int i, j, n;
0635 
0636     pr_info("\n%s: %s - dma Audio channel status dump\n",
0637         dev->name, ch->name);
0638 
0639     for (i = 0; i < ARRAY_SIZE(name); i++)
0640         pr_info("%s: cmds + 0x%2x:   %-15s: 0x%08x\n",
0641             dev->name, i * 4, name[i],
0642             cx_read(ch->cmds_start + 4 * i));
0643 
0644     j = i * 4;
0645     for (i = 0; i < 4;) {
0646         risc = cx_read(ch->cmds_start + 4 * (i + 14));
0647         pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
0648         i += cx25821_risc_decode(risc);
0649     }
0650 
0651     for (i = 0; i < (64 >> 2); i += n) {
0652         risc = cx_read(ch->ctrl_start + 4 * i);
0653         /* No consideration for bits 63-32 */
0654 
0655         pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
0656             i * 4, ch->ctrl_start + 4 * i, i);
0657         n = cx25821_risc_decode(risc);
0658 
0659         for (j = 1; j < n; j++) {
0660             risc = cx_read(ch->ctrl_start + 4 * (i + j));
0661             pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
0662                 4 * (i + j), i + j, risc, j);
0663         }
0664     }
0665 
0666     pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
0667         ch->fifo_start, ch->fifo_start + ch->fifo_size);
0668     pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
0669         ch->ctrl_start, ch->ctrl_start + 6 * 16);
0670     pr_warn("        :   ptr1_reg: 0x%08x\n",
0671         cx_read(ch->ptr1_reg));
0672     pr_warn("        :   ptr2_reg: 0x%08x\n",
0673         cx_read(ch->ptr2_reg));
0674     pr_warn("        :   cnt1_reg: 0x%08x\n",
0675         cx_read(ch->cnt1_reg));
0676     pr_warn("        :   cnt2_reg: 0x%08x\n",
0677         cx_read(ch->cnt2_reg));
0678 
0679     for (i = 0; i < 4; i++) {
0680         risc = cx_read(ch->cmds_start + 56 + (i * 4));
0681         pr_warn("instruction %d = 0x%x\n", i, risc);
0682     }
0683 
0684     /* read data from the first cdt buffer */
0685     risc = cx_read(AUD_A_CDT);
0686     pr_warn("\nread cdt loc=0x%x\n", risc);
0687     for (i = 0; i < 8; i++) {
0688         n = cx_read(risc + i * 4);
0689         pr_cont("0x%x ", n);
0690     }
0691     pr_cont("\n\n");
0692 
0693     value = cx_read(CLK_RST);
0694     CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
0695 
0696     value = cx_read(PLL_A_POST_STAT_BIST);
0697     CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
0698     value = cx_read(PLL_A_INT_FRAC);
0699     CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
0700 
0701     value = cx_read(PLL_B_POST_STAT_BIST);
0702     CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
0703     value = cx_read(PLL_B_INT_FRAC);
0704     CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
0705 
0706     value = cx_read(PLL_C_POST_STAT_BIST);
0707     CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
0708     value = cx_read(PLL_C_INT_FRAC);
0709     CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
0710 
0711     value = cx_read(PLL_D_POST_STAT_BIST);
0712     CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
0713     value = cx_read(PLL_D_INT_FRAC);
0714     CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
0715 
0716     value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
0717     CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
0718 }
0719 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
0720 
0721 static void cx25821_shutdown(struct cx25821_dev *dev)
0722 {
0723     int i;
0724 
0725     /* disable RISC controller */
0726     cx_write(DEV_CNTRL2, 0);
0727 
0728     /* Disable Video A/B activity */
0729     for (i = 0; i < VID_CHANNEL_NUM; i++) {
0730         cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
0731         cx_write(dev->channels[i].sram_channels->int_msk, 0);
0732     }
0733 
0734     for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
0735         i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
0736         cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
0737         cx_write(dev->channels[i].sram_channels->int_msk, 0);
0738     }
0739 
0740     /* Disable Audio activity */
0741     cx_write(AUD_INT_DMA_CTL, 0);
0742 
0743     /* Disable Serial port */
0744     cx_write(UART_CTL, 0);
0745 
0746     /* Disable Interrupts */
0747     cx_write(PCI_INT_MSK, 0);
0748     cx_write(AUD_A_INT_MSK, 0);
0749 }
0750 
0751 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
0752                   u32 format)
0753 {
0754     if (channel_select <= 7 && channel_select >= 0) {
0755         cx_write(dev->channels[channel_select].sram_channels->pix_frmt,
0756                 format);
0757     }
0758     dev->channels[channel_select].pixel_formats = format;
0759 }
0760 
0761 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
0762                  const struct sram_channel *ch)
0763 {
0764     cx_write(ch->pix_frmt, PIXEL_FRMT_422);
0765     cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
0766 }
0767 
0768 static void cx25821_initialize(struct cx25821_dev *dev)
0769 {
0770     int i;
0771 
0772     dprintk(1, "%s()\n", __func__);
0773 
0774     cx25821_shutdown(dev);
0775     cx_write(PCI_INT_STAT, 0xffffffff);
0776 
0777     for (i = 0; i < VID_CHANNEL_NUM; i++)
0778         cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
0779 
0780     cx_write(AUD_A_INT_STAT, 0xffffffff);
0781     cx_write(AUD_B_INT_STAT, 0xffffffff);
0782     cx_write(AUD_C_INT_STAT, 0xffffffff);
0783     cx_write(AUD_D_INT_STAT, 0xffffffff);
0784     cx_write(AUD_E_INT_STAT, 0xffffffff);
0785 
0786     cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
0787     cx_write(PAD_CTRL, 0x12);   /* for I2C */
0788     cx25821_registers_init(dev);    /* init Pecos registers */
0789     msleep(100);
0790 
0791     for (i = 0; i < VID_CHANNEL_NUM; i++) {
0792         cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
0793         cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
0794                         1440, 0);
0795         dev->channels[i].pixel_formats = PIXEL_FRMT_422;
0796         dev->channels[i].use_cif_resolution = 0;
0797     }
0798 
0799     /* Probably only affect Downstream */
0800     for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
0801         i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
0802         dev->channels[i].pixel_formats = PIXEL_FRMT_422;
0803         cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
0804     }
0805 
0806     cx25821_sram_channel_setup_audio(dev,
0807             dev->channels[SRAM_CH08].sram_channels, 128, 0);
0808 
0809     cx25821_gpio_init(dev);
0810 }
0811 
0812 static int cx25821_get_resources(struct cx25821_dev *dev)
0813 {
0814     if (request_mem_region(pci_resource_start(dev->pci, 0),
0815                 pci_resource_len(dev->pci, 0), dev->name))
0816         return 0;
0817 
0818     pr_err("%s: can't get MMIO memory @ 0x%llx\n",
0819         dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
0820 
0821     return -EBUSY;
0822 }
0823 
0824 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
0825 {
0826     dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
0827 
0828     pr_info("Hardware revision = 0x%02x\n", dev->hwrevision);
0829 }
0830 
0831 static void cx25821_iounmap(struct cx25821_dev *dev)
0832 {
0833     if (dev == NULL)
0834         return;
0835 
0836     /* Releasing IO memory */
0837     if (dev->lmmio != NULL) {
0838         iounmap(dev->lmmio);
0839         dev->lmmio = NULL;
0840     }
0841 }
0842 
0843 static int cx25821_dev_setup(struct cx25821_dev *dev)
0844 {
0845     static unsigned int cx25821_devcount;
0846     int i;
0847 
0848     mutex_init(&dev->lock);
0849 
0850     dev->nr = ++cx25821_devcount;
0851     sprintf(dev->name, "cx25821[%d]", dev->nr);
0852 
0853     if (dev->nr >= ARRAY_SIZE(card)) {
0854         CX25821_INFO("dev->nr >= %zd", ARRAY_SIZE(card));
0855         return -ENODEV;
0856     }
0857     if (dev->pci->device != 0x8210) {
0858         pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
0859             __func__, dev->pci->device);
0860         return -ENODEV;
0861     }
0862     pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
0863 
0864     /* Apply a sensible clock frequency for the PCIe bridge */
0865     dev->clk_freq = 28000000;
0866     for (i = 0; i < MAX_VID_CHANNEL_NUM; i++) {
0867         dev->channels[i].dev = dev;
0868         dev->channels[i].id = i;
0869         dev->channels[i].sram_channels = &cx25821_sram_channels[i];
0870     }
0871 
0872     /* board config */
0873     dev->board = 1;     /* card[dev->nr]; */
0874     dev->_max_num_decoders = MAX_DECODERS;
0875 
0876     dev->pci_bus = dev->pci->bus->number;
0877     dev->pci_slot = PCI_SLOT(dev->pci->devfn);
0878     dev->pci_irqmask = 0x001f00;
0879 
0880     /* External Master 1 Bus */
0881     dev->i2c_bus[0].nr = 0;
0882     dev->i2c_bus[0].dev = dev;
0883     dev->i2c_bus[0].reg_stat = I2C1_STAT;
0884     dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
0885     dev->i2c_bus[0].reg_addr = I2C1_ADDR;
0886     dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
0887     dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
0888     dev->i2c_bus[0].i2c_period = (0x07 << 24);  /* 1.95MHz */
0889 
0890     if (cx25821_get_resources(dev) < 0) {
0891         pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
0892                dev->name, dev->pci->subsystem_vendor,
0893                dev->pci->subsystem_device);
0894 
0895         cx25821_devcount--;
0896         return -EBUSY;
0897     }
0898 
0899     /* PCIe stuff */
0900     dev->base_io_addr = pci_resource_start(dev->pci, 0);
0901 
0902     if (!dev->base_io_addr) {
0903         CX25821_ERR("No PCI Memory resources, exiting!\n");
0904         return -ENODEV;
0905     }
0906 
0907     dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
0908 
0909     if (!dev->lmmio) {
0910         CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
0911         cx25821_iounmap(dev);
0912         return -ENOMEM;
0913     }
0914 
0915     dev->bmmio = (u8 __iomem *) dev->lmmio;
0916 
0917     pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
0918         dev->name, dev->pci->subsystem_vendor,
0919         dev->pci->subsystem_device, cx25821_boards[dev->board].name,
0920         dev->board, card[dev->nr] == dev->board ?
0921         "insmod option" : "autodetected");
0922 
0923     /* init hardware */
0924     cx25821_initialize(dev);
0925 
0926     cx25821_i2c_register(&dev->i2c_bus[0]);
0927 /*  cx25821_i2c_register(&dev->i2c_bus[1]);
0928  *  cx25821_i2c_register(&dev->i2c_bus[2]); */
0929 
0930     if (medusa_video_init(dev) < 0)
0931         CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
0932 
0933     cx25821_video_register(dev);
0934 
0935     cx25821_dev_checkrevision(dev);
0936     return 0;
0937 }
0938 
0939 void cx25821_dev_unregister(struct cx25821_dev *dev)
0940 {
0941     int i;
0942 
0943     if (!dev->base_io_addr)
0944         return;
0945 
0946     release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
0947 
0948     for (i = 0; i < MAX_VID_CAP_CHANNEL_NUM - 1; i++) {
0949         if (i == SRAM_CH08) /* audio channel */
0950             continue;
0951         /*
0952          * TODO: enable when video output is properly
0953          * supported.
0954         if (i == SRAM_CH09 || i == SRAM_CH10)
0955             cx25821_free_mem_upstream(&dev->channels[i]);
0956          */
0957         cx25821_video_unregister(dev, i);
0958     }
0959 
0960     cx25821_i2c_unregister(&dev->i2c_bus[0]);
0961     cx25821_iounmap(dev);
0962 }
0963 EXPORT_SYMBOL(cx25821_dev_unregister);
0964 
0965 int cx25821_riscmem_alloc(struct pci_dev *pci,
0966                struct cx25821_riscmem *risc,
0967                unsigned int size)
0968 {
0969     __le32 *cpu;
0970     dma_addr_t dma = 0;
0971 
0972     if (risc->cpu && risc->size < size) {
0973         dma_free_coherent(&pci->dev, risc->size, risc->cpu, risc->dma);
0974         risc->cpu = NULL;
0975     }
0976     if (NULL == risc->cpu) {
0977         cpu = dma_alloc_coherent(&pci->dev, size, &dma, GFP_KERNEL);
0978         if (NULL == cpu)
0979             return -ENOMEM;
0980         risc->cpu  = cpu;
0981         risc->dma  = dma;
0982         risc->size = size;
0983     }
0984     return 0;
0985 }
0986 EXPORT_SYMBOL(cx25821_riscmem_alloc);
0987 
0988 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
0989                   unsigned int offset, u32 sync_line,
0990                   unsigned int bpl, unsigned int padding,
0991                   unsigned int lines, bool jump)
0992 {
0993     struct scatterlist *sg;
0994     unsigned int line, todo;
0995 
0996     if (jump) {
0997         *(rp++) = cpu_to_le32(RISC_JUMP);
0998         *(rp++) = cpu_to_le32(0);
0999         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1000     }
1001 
1002     /* sync instruction */
1003     if (sync_line != NO_SYNC_LINE)
1004         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1005 
1006     /* scan lines */
1007     sg = sglist;
1008     for (line = 0; line < lines; line++) {
1009         while (offset && offset >= sg_dma_len(sg)) {
1010             offset -= sg_dma_len(sg);
1011             sg = sg_next(sg);
1012         }
1013         if (bpl <= sg_dma_len(sg) - offset) {
1014             /* fits into current chunk */
1015             *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL |
1016                     bpl);
1017             *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1018             *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1019             offset += bpl;
1020         } else {
1021             /* scanline needs to be split */
1022             todo = bpl;
1023             *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL |
1024                     (sg_dma_len(sg) - offset));
1025             *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1026             *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1027             todo -= (sg_dma_len(sg) - offset);
1028             offset = 0;
1029             sg = sg_next(sg);
1030             while (todo > sg_dma_len(sg)) {
1031                 *(rp++) = cpu_to_le32(RISC_WRITE |
1032                         sg_dma_len(sg));
1033                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1034                 *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1035                 todo -= sg_dma_len(sg);
1036                 sg = sg_next(sg);
1037             }
1038             *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1039             *(rp++) = cpu_to_le32(sg_dma_address(sg));
1040             *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1041             offset += todo;
1042         }
1043 
1044         offset += padding;
1045     }
1046 
1047     return rp;
1048 }
1049 
1050 int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
1051             struct scatterlist *sglist, unsigned int top_offset,
1052             unsigned int bottom_offset, unsigned int bpl,
1053             unsigned int padding, unsigned int lines)
1054 {
1055     u32 instructions;
1056     u32 fields;
1057     __le32 *rp;
1058     int rc;
1059 
1060     fields = 0;
1061     if (UNSET != top_offset)
1062         fields++;
1063     if (UNSET != bottom_offset)
1064         fields++;
1065 
1066     /* estimate risc mem: worst case is one write per page border +
1067        one write per scan line + syncs + jump (all 3 dwords).  Padding
1068        can cause next bpl to start close to a page border.  First DMA
1069        region may be smaller than PAGE_SIZE */
1070     /* write and jump need and extra dword */
1071     instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE +
1072             lines);
1073     instructions += 5;
1074     rc = cx25821_riscmem_alloc(pci, risc, instructions * 12);
1075 
1076     if (rc < 0)
1077         return rc;
1078 
1079     /* write risc instructions */
1080     rp = risc->cpu;
1081 
1082     if (UNSET != top_offset) {
1083         rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1084                     lines, true);
1085     }
1086 
1087     if (UNSET != bottom_offset) {
1088         rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1089                     padding, lines, UNSET == top_offset);
1090     }
1091 
1092     /* save pointer to jmp instruction address */
1093     risc->jmp = rp;
1094     BUG_ON((risc->jmp - risc->cpu + 3) * sizeof(*risc->cpu) > risc->size);
1095 
1096     return 0;
1097 }
1098 
1099 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1100                     unsigned int offset, u32 sync_line,
1101                     unsigned int bpl, unsigned int padding,
1102                     unsigned int lines, unsigned int lpi)
1103 {
1104     struct scatterlist *sg;
1105     unsigned int line, todo, sol;
1106 
1107     /* sync instruction */
1108     if (sync_line != NO_SYNC_LINE)
1109         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1110 
1111     /* scan lines */
1112     sg = sglist;
1113     for (line = 0; line < lines; line++) {
1114         while (offset && offset >= sg_dma_len(sg)) {
1115             offset -= sg_dma_len(sg);
1116             sg = sg_next(sg);
1117         }
1118 
1119         if (lpi && line > 0 && !(line % lpi))
1120             sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1121         else
1122             sol = RISC_SOL;
1123 
1124         if (bpl <= sg_dma_len(sg) - offset) {
1125             /* fits into current chunk */
1126             *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL |
1127                     bpl);
1128             *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1129             *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1130             offset += bpl;
1131         } else {
1132             /* scanline needs to be split */
1133             todo = bpl;
1134             *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1135                     (sg_dma_len(sg) - offset));
1136             *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1137             *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1138             todo -= (sg_dma_len(sg) - offset);
1139             offset = 0;
1140             sg = sg_next(sg);
1141             while (todo > sg_dma_len(sg)) {
1142                 *(rp++) = cpu_to_le32(RISC_WRITE |
1143                         sg_dma_len(sg));
1144                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1145                 *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1146                 todo -= sg_dma_len(sg);
1147                 sg = sg_next(sg);
1148             }
1149             *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1150             *(rp++) = cpu_to_le32(sg_dma_address(sg));
1151             *(rp++) = cpu_to_le32(0);   /* bits 63-32 */
1152             offset += todo;
1153         }
1154         offset += padding;
1155     }
1156 
1157     return rp;
1158 }
1159 
1160 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1161                   struct cx25821_riscmem *risc,
1162                   struct scatterlist *sglist,
1163                   unsigned int bpl,
1164                   unsigned int lines, unsigned int lpi)
1165 {
1166     u32 instructions;
1167     __le32 *rp;
1168     int rc;
1169 
1170     /* estimate risc mem: worst case is one write per page border +
1171        one write per scan line + syncs + jump (all 2 dwords).  Here
1172        there is no padding and no sync.  First DMA region may be smaller
1173        than PAGE_SIZE */
1174     /* Jump and write need an extra dword */
1175     instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1176     instructions += 1;
1177 
1178     rc = cx25821_riscmem_alloc(pci, risc, instructions * 12);
1179     if (rc < 0)
1180         return rc;
1181 
1182     /* write risc instructions */
1183     rp = risc->cpu;
1184     rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1185                       lines, lpi);
1186 
1187     /* save pointer to jmp instruction address */
1188     risc->jmp = rp;
1189     BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1190     return 0;
1191 }
1192 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1193 
1194 void cx25821_free_buffer(struct cx25821_dev *dev, struct cx25821_buffer *buf)
1195 {
1196     if (WARN_ON(buf->risc.size == 0))
1197         return;
1198     dma_free_coherent(&dev->pci->dev, buf->risc.size, buf->risc.cpu,
1199               buf->risc.dma);
1200     memset(&buf->risc, 0, sizeof(buf->risc));
1201 }
1202 
1203 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1204 {
1205     struct cx25821_dev *dev = dev_id;
1206     u32 pci_status;
1207     u32 vid_status;
1208     int i, handled = 0;
1209     u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1210 
1211     pci_status = cx_read(PCI_INT_STAT);
1212 
1213     if (pci_status == 0)
1214         goto out;
1215 
1216     for (i = 0; i < VID_CHANNEL_NUM; i++) {
1217         if (pci_status & mask[i]) {
1218             vid_status = cx_read(dev->channels[i].
1219                 sram_channels->int_stat);
1220 
1221             if (vid_status)
1222                 handled += cx25821_video_irq(dev, i,
1223                         vid_status);
1224 
1225             cx_write(PCI_INT_STAT, mask[i]);
1226         }
1227     }
1228 
1229 out:
1230     return IRQ_RETVAL(handled);
1231 }
1232 
1233 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1234                int len, u32 bits, u32 mask)
1235 {
1236     unsigned int i;
1237 
1238     printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1239 
1240     for (i = 0; i < len; i++) {
1241         if (!(bits & (1 << i)))
1242             continue;
1243         if (strings[i])
1244             pr_cont(" %s", strings[i]);
1245         else
1246             pr_cont(" %d", i);
1247         if (!(mask & (1 << i)))
1248             continue;
1249         pr_cont("*");
1250     }
1251     pr_cont("\n");
1252 }
1253 EXPORT_SYMBOL(cx25821_print_irqbits);
1254 
1255 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1256 {
1257     struct cx25821_dev *dev = pci_get_drvdata(pci);
1258     return dev;
1259 }
1260 EXPORT_SYMBOL(cx25821_dev_get);
1261 
1262 static int cx25821_initdev(struct pci_dev *pci_dev,
1263                const struct pci_device_id *pci_id)
1264 {
1265     struct cx25821_dev *dev;
1266     int err = 0;
1267 
1268     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1269     if (NULL == dev)
1270         return -ENOMEM;
1271 
1272     err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1273     if (err < 0)
1274         goto fail_free;
1275 
1276     /* pci init */
1277     dev->pci = pci_dev;
1278     if (pci_enable_device(pci_dev)) {
1279         err = -EIO;
1280 
1281         pr_info("pci enable failed!\n");
1282 
1283         goto fail_unregister_device;
1284     }
1285 
1286     err = cx25821_dev_setup(dev);
1287     if (err)
1288         goto fail_unregister_pci;
1289 
1290     /* print pci info */
1291     pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1292     pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1293     pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1294         dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1295         dev->pci_lat, (unsigned long long)dev->base_io_addr);
1296 
1297     pci_set_master(pci_dev);
1298     err = dma_set_mask(&pci_dev->dev, 0xffffffff);
1299     if (err) {
1300         pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1301         err = -EIO;
1302         goto fail_irq;
1303     }
1304 
1305     err = request_irq(pci_dev->irq, cx25821_irq,
1306             IRQF_SHARED, dev->name, dev);
1307 
1308     if (err < 0) {
1309         pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1310         goto fail_irq;
1311     }
1312 
1313     return 0;
1314 
1315 fail_irq:
1316     pr_info("cx25821_initdev() can't get IRQ !\n");
1317     cx25821_dev_unregister(dev);
1318 
1319 fail_unregister_pci:
1320     pci_disable_device(pci_dev);
1321 fail_unregister_device:
1322     v4l2_device_unregister(&dev->v4l2_dev);
1323 
1324 fail_free:
1325     kfree(dev);
1326     return err;
1327 }
1328 
1329 static void cx25821_finidev(struct pci_dev *pci_dev)
1330 {
1331     struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1332     struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1333 
1334     cx25821_shutdown(dev);
1335 
1336     /* unregister stuff */
1337     if (pci_dev->irq)
1338         free_irq(pci_dev->irq, dev);
1339     pci_disable_device(pci_dev);
1340 
1341     cx25821_dev_unregister(dev);
1342     v4l2_device_unregister(v4l2_dev);
1343     kfree(dev);
1344 }
1345 
1346 static const struct pci_device_id cx25821_pci_tbl[] = {
1347     {
1348         /* CX25821 Athena */
1349         .vendor = 0x14f1,
1350         .device = 0x8210,
1351         .subvendor = 0x14f1,
1352         .subdevice = 0x0920,
1353     }, {
1354         /* CX25821 No Brand */
1355         .vendor = 0x14f1,
1356         .device = 0x8210,
1357         .subvendor = 0x0000,
1358         .subdevice = 0x0000,
1359     }, {
1360         /* --- end of list --- */
1361     }
1362 };
1363 
1364 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1365 
1366 static struct pci_driver cx25821_pci_driver = {
1367     .name = "cx25821",
1368     .id_table = cx25821_pci_tbl,
1369     .probe = cx25821_initdev,
1370     .remove = cx25821_finidev,
1371 };
1372 
1373 static int __init cx25821_init(void)
1374 {
1375     pr_info("driver loaded\n");
1376     return pci_register_driver(&cx25821_pci_driver);
1377 }
1378 
1379 static void __exit cx25821_fini(void)
1380 {
1381     pci_unregister_driver(&cx25821_pci_driver);
1382 }
1383 
1384 module_init(cx25821_init);
1385 module_exit(cx25821_fini);
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