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0001 /* SPDX-License-Identifier: GPL-2.0-only */ 0002 /* 0003 * Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates. 0004 * All rights reserved. 0005 */ 0006 0007 #ifndef M00235_FDMA_PACKER_MEMMAP_PACKAGE_H 0008 #define M00235_FDMA_PACKER_MEMMAP_PACKAGE_H 0009 0010 /******************************************************************* 0011 * Register Block 0012 * M00235_FDMA_PACKER_MEMMAP_PACKAGE_VHD_REGMAP 0013 *******************************************************************/ 0014 struct m00235_fdma_packer_regmap { 0015 uint32_t control; /* Reg 0x0000, Default=0x0 */ 0016 }; 0017 0018 #define M00235_FDMA_PACKER_REG_CONTROL_OFST 0 0019 0020 /******************************************************************* 0021 * Bit Mask for register 0022 * M00235_FDMA_PACKER_MEMMAP_PACKAGE_VHD_BITMAP 0023 *******************************************************************/ 0024 /* control [3:0] */ 0025 #define M00235_CONTROL_BITMAP_ENABLE_OFST (0) 0026 #define M00235_CONTROL_BITMAP_ENABLE_MSK (0x1 << M00235_CONTROL_BITMAP_ENABLE_OFST) 0027 #define M00235_CONTROL_BITMAP_PACK_FORMAT_OFST (1) 0028 #define M00235_CONTROL_BITMAP_PACK_FORMAT_MSK (0x3 << M00235_CONTROL_BITMAP_PACK_FORMAT_OFST) 0029 #define M00235_CONTROL_BITMAP_ENDIAN_FORMAT_OFST (3) 0030 #define M00235_CONTROL_BITMAP_ENDIAN_FORMAT_MSK (0x1 << M00235_CONTROL_BITMAP_ENDIAN_FORMAT_OFST) 0031 0032 #endif /*M00235_FDMA_PACKER_MEMMAP_PACKAGE_H*/
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