pci/cobalt/m00233_video_measure_memmap_package.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates.
0004  *  All rights reserved.
0005  */
0006
0007 #ifndef M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H
0008 #define M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H
0009
0010 /*******************************************************************
0011  * Register Block
0012  * M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_REGMAP
0013  *******************************************************************/
0014 struct m00233_video_measure_regmap {
0015     uint32_t irq_status;        /* Reg 0x0000 */
0016     /* The vertical counter starts on rising edge of vsync */
0017     uint32_t vsync_time;        /* Reg 0x0004 */
0018     uint32_t vback_porch;       /* Reg 0x0008 */
0019     uint32_t vactive_area;      /* Reg 0x000c */
0020     uint32_t vfront_porch;      /* Reg 0x0010 */
0021     /* The horizontal counter starts on rising edge of hsync. */
0022     uint32_t hsync_time;        /* Reg 0x0014 */
0023     uint32_t hback_porch;       /* Reg 0x0018 */
0024     uint32_t hactive_area;      /* Reg 0x001c */
0025     uint32_t hfront_porch;      /* Reg 0x0020 */
0026     uint32_t control;           /* Reg 0x0024, Default=0x0 */
0027     uint32_t irq_triggers;      /* Reg 0x0028, Default=0xff */
0028     /* Value is given in number of register bus clock periods between */
0029     /* falling and rising edge of hsync. Must be non-zero. */
0030     uint32_t hsync_timeout_val; /* Reg 0x002c, Default=0x1fff */
0031     uint32_t status;            /* Reg 0x0030 */
0032 };
0033
0034 #define M00233_VIDEO_MEASURE_REG_IRQ_STATUS_OFST 0
0035 #define M00233_VIDEO_MEASURE_REG_VSYNC_TIME_OFST 4
0036 #define M00233_VIDEO_MEASURE_REG_VBACK_PORCH_OFST 8
0037 #define M00233_VIDEO_MEASURE_REG_VACTIVE_AREA_OFST 12
0038 #define M00233_VIDEO_MEASURE_REG_VFRONT_PORCH_OFST 16
0039 #define M00233_VIDEO_MEASURE_REG_HSYNC_TIME_OFST 20
0040 #define M00233_VIDEO_MEASURE_REG_HBACK_PORCH_OFST 24
0041 #define M00233_VIDEO_MEASURE_REG_HACTIVE_AREA_OFST 28
0042 #define M00233_VIDEO_MEASURE_REG_HFRONT_PORCH_OFST 32
0043 #define M00233_VIDEO_MEASURE_REG_CONTROL_OFST 36
0044 #define M00233_VIDEO_MEASURE_REG_IRQ_TRIGGERS_OFST 40
0045 #define M00233_VIDEO_MEASURE_REG_HSYNC_TIMEOUT_VAL_OFST 44
0046 #define M00233_VIDEO_MEASURE_REG_STATUS_OFST 48
0047
0048 /*******************************************************************
0049  * Bit Mask for register
0050  * M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_BITMAP
0051  *******************************************************************/
0052 /* irq_status [7:0] */
0053 #define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST      (0)
0054 #define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_MSK       (0x1 << M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST)
0055 #define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST     (1)
0056 #define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_MSK      (0x1 << M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST)
0057 #define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST    (2)
0058 #define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST)
0059 #define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST    (3)
0060 #define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST)
0061 #define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST      (4)
0062 #define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_MSK       (0x1 << M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST)
0063 #define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST     (5)
0064 #define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_MSK      (0x1 << M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST)
0065 #define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST    (6)
0066 #define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST)
0067 #define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST    (7)
0068 #define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST)
0069 /* control [4:0] */
0070 #define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST (0)
0071 #define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK  (0x1 << M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST)
0072 #define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST (1)
0073 #define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK  (0x1 << M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST)
0074 #define M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST     (2)
0075 #define M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK      (0x1 << M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST)
0076 #define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST   (3)
0077 #define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_MSK    (0x1 << M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST)
0078 #define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST    (4)
0079 #define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_MSK     (0x1 << M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST)
0080 /* irq_triggers [7:0] */
0081 #define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST    (0)
0082 #define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_MSK     (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST)
0083 #define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST   (1)
0084 #define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_MSK    (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST)
0085 #define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST  (2)
0086 #define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST)
0087 #define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST  (3)
0088 #define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST)
0089 #define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST    (4)
0090 #define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_MSK     (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST)
0091 #define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST   (5)
0092 #define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_MSK    (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST)
0093 #define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST  (6)
0094 #define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST)
0095 #define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST  (7)
0096 #define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST)
0097 /* status [1:0] */
0098 #define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST       (0)
0099 #define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_MSK        (0x1 << M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST)
0100 #define M00233_STATUS_BITMAP_INIT_DONE_OFST           (1)
0101 #define M00233_STATUS_BITMAP_INIT_DONE_MSK            (0x1 << M00233_STATUS_BITMAP_INIT_DONE_OFST)
0102
0103 #endif /*M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H*/