pci/cobalt/cobalt-driver.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  cobalt driver internal defines and structures
0004  *
0005  *  Derived from cx18-driver.h
0006  *
0007  *  Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
0008  *  All rights reserved.
0009  */
0010
0011 #ifndef COBALT_DRIVER_H
0012 #define COBALT_DRIVER_H
0013
0014 #include <linux/bitops.h>
0015 #include <linux/module.h>
0016 #include <linux/pci.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/i2c.h>
0019 #include <linux/list.h>
0020 #include <linux/workqueue.h>
0021 #include <linux/mutex.h>
0022
0023 #include <media/v4l2-common.h>
0024 #include <media/v4l2-ioctl.h>
0025 #include <media/v4l2-device.h>
0026 #include <media/v4l2-fh.h>
0027 #include <media/videobuf2-v4l2.h>
0028 #include <media/videobuf2-dma-sg.h>
0029
0030 #include "m00233_video_measure_memmap_package.h"
0031 #include "m00235_fdma_packer_memmap_package.h"
0032 #include "m00389_cvi_memmap_package.h"
0033 #include "m00460_evcnt_memmap_package.h"
0034 #include "m00473_freewheel_memmap_package.h"
0035 #include "m00479_clk_loss_detector_memmap_package.h"
0036 #include "m00514_syncgen_flow_evcnt_memmap_package.h"
0037
0038 /* System device ID */
0039 #define PCI_DEVICE_ID_COBALT    0x2732
0040
0041 /* Number of cobalt device nodes. */
0042 #define COBALT_NUM_INPUTS   4
0043 #define COBALT_NUM_NODES    6
0044
0045 /* Number of cobalt device streams. */
0046 #define COBALT_NUM_STREAMS  12
0047
0048 #define COBALT_HSMA_IN_NODE 4
0049 #define COBALT_HSMA_OUT_NODE    5
0050
0051 /* Cobalt audio streams */
0052 #define COBALT_AUDIO_IN_STREAM  6
0053 #define COBALT_AUDIO_OUT_STREAM 11
0054
0055 /* DMA stuff */
0056 #define DMA_CHANNELS_MAX    16
0057
0058 /* i2c stuff */
0059 #define I2C_CLIENTS_MAX     16
0060 #define COBALT_NUM_ADAPTERS 5
0061
0062 #define COBALT_CLK      50000000
0063
0064 /* System status register */
0065 #define COBALT_SYSSTAT_DIP0_MSK         BIT(0)
0066 #define COBALT_SYSSTAT_DIP1_MSK         BIT(1)
0067 #define COBALT_SYSSTAT_HSMA_PRSNTN_MSK      BIT(2)
0068 #define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK    BIT(3)
0069 #define COBALT_SYSSTAT_VI0_5V_MSK       BIT(4)
0070 #define COBALT_SYSSTAT_VI0_INT1_MSK     BIT(5)
0071 #define COBALT_SYSSTAT_VI0_INT2_MSK     BIT(6)
0072 #define COBALT_SYSSTAT_VI0_LOST_DATA_MSK    BIT(7)
0073 #define COBALT_SYSSTAT_VI1_5V_MSK       BIT(8)
0074 #define COBALT_SYSSTAT_VI1_INT1_MSK     BIT(9)
0075 #define COBALT_SYSSTAT_VI1_INT2_MSK     BIT(10)
0076 #define COBALT_SYSSTAT_VI1_LOST_DATA_MSK    BIT(11)
0077 #define COBALT_SYSSTAT_VI2_5V_MSK       BIT(12)
0078 #define COBALT_SYSSTAT_VI2_INT1_MSK     BIT(13)
0079 #define COBALT_SYSSTAT_VI2_INT2_MSK     BIT(14)
0080 #define COBALT_SYSSTAT_VI2_LOST_DATA_MSK    BIT(15)
0081 #define COBALT_SYSSTAT_VI3_5V_MSK       BIT(16)
0082 #define COBALT_SYSSTAT_VI3_INT1_MSK     BIT(17)
0083 #define COBALT_SYSSTAT_VI3_INT2_MSK     BIT(18)
0084 #define COBALT_SYSSTAT_VI3_LOST_DATA_MSK    BIT(19)
0085 #define COBALT_SYSSTAT_VIHSMA_5V_MSK        BIT(20)
0086 #define COBALT_SYSSTAT_VIHSMA_INT1_MSK      BIT(21)
0087 #define COBALT_SYSSTAT_VIHSMA_INT2_MSK      BIT(22)
0088 #define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK BIT(23)
0089 #define COBALT_SYSSTAT_VOHSMA_INT1_MSK      BIT(24)
0090 #define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK    BIT(25)
0091 #define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK BIT(26)
0092 #define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK   BIT(28)
0093 #define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK BIT(29)
0094 #define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK    BIT(30)
0095 #define COBALT_SYSSTAT_PCIE_SMBCLK_MSK      BIT(31)
0096
0097 /* Cobalt memory map */
0098 #define COBALT_I2C_0_BASE           0x0
0099 #define COBALT_I2C_1_BASE           0x080
0100 #define COBALT_I2C_2_BASE           0x100
0101 #define COBALT_I2C_3_BASE           0x180
0102 #define COBALT_I2C_HSMA_BASE            0x200
0103
0104 #define COBALT_SYS_CTRL_BASE            0x400
0105 #define COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT  1
0106 #define COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(n)  (4 + 4 * (n))
0107 #define COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(n)   (5 + 4 * (n))
0108 #define COBALT_SYS_CTRL_HPD_TO_CONNECTOR_BIT(n) (6 + 4 * (n))
0109 #define COBALT_SYS_CTRL_AUDIO_IPP_RESETN_BIT(n) (7 + 4 * (n))
0110 #define COBALT_SYS_CTRL_PWRDN0_TO_HSMA_TX_BIT   24
0111 #define COBALT_SYS_CTRL_VIDEO_TX_RESETN_BIT 25
0112 #define COBALT_SYS_CTRL_AUDIO_OPP_RESETN_BIT    27
0113
0114 #define COBALT_SYS_STAT_BASE            0x500
0115 #define COBALT_SYS_STAT_MASK            (COBALT_SYS_STAT_BASE + 0x08)
0116 #define COBALT_SYS_STAT_EDGE            (COBALT_SYS_STAT_BASE + 0x0c)
0117
0118 #define COBALT_HDL_INFO_BASE            0x4800
0119 #define COBALT_HDL_INFO_SIZE            0x200
0120
0121 #define COBALT_VID_BASE             0x10000
0122 #define COBALT_VID_SIZE             0x1000
0123
0124 #define COBALT_CVI(cobalt, c) \
0125     (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE)
0126 #define COBALT_CVI_VMR(cobalt, c) \
0127     (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x100)
0128 #define COBALT_CVI_EVCNT(cobalt, c) \
0129     (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x200)
0130 #define COBALT_CVI_FREEWHEEL(cobalt, c) \
0131     (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x300)
0132 #define COBALT_CVI_CLK_LOSS(cobalt, c) \
0133     (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x400)
0134 #define COBALT_CVI_PACKER(cobalt, c) \
0135     (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x500)
0136
0137 #define COBALT_TX_BASE(cobalt) (cobalt->bar1 + COBALT_VID_BASE + 0x5000)
0138
0139 #define DMA_INTERRUPT_STATUS_REG        0x08
0140
0141 #define COBALT_HDL_SEARCH_STR           "** HDL version info **"
0142
0143 /* Cobalt CPU bus interface */
0144 #define COBALT_BUS_BAR1_BASE            0x600
0145 #define COBALT_BUS_SRAM_BASE            0x0
0146 #define COBALT_BUS_CPLD_BASE            0x00600000
0147 #define COBALT_BUS_FLASH_BASE           0x08000000
0148
0149 /* FDMA to PCIe packing */
0150 #define COBALT_BYTES_PER_PIXEL_YUYV     2
0151 #define COBALT_BYTES_PER_PIXEL_RGB24        3
0152 #define COBALT_BYTES_PER_PIXEL_RGB32        4
0153
0154 /* debugging */
0155 extern int cobalt_debug;
0156 extern int cobalt_ignore_err;
0157
0158 #define cobalt_err(fmt, arg...)  v4l2_err(&cobalt->v4l2_dev, fmt, ## arg)
0159 #define cobalt_warn(fmt, arg...) v4l2_warn(&cobalt->v4l2_dev, fmt, ## arg)
0160 #define cobalt_info(fmt, arg...) v4l2_info(&cobalt->v4l2_dev, fmt, ## arg)
0161 #define cobalt_dbg(level, fmt, arg...) \
0162     v4l2_dbg(level, cobalt_debug, &cobalt->v4l2_dev, fmt, ## arg)
0163
0164 struct cobalt;
0165 struct cobalt_i2c_regs;
0166
0167 /* Per I2C bus private algo callback data */
0168 struct cobalt_i2c_data {
0169     struct cobalt *cobalt;
0170     struct cobalt_i2c_regs __iomem *regs;
0171 };
0172
0173 struct pci_consistent_buffer {
0174     void *virt;
0175     dma_addr_t bus;
0176     size_t bytes;
0177 };
0178
0179 struct sg_dma_desc_info {
0180     void *virt;
0181     dma_addr_t bus;
0182     unsigned size;
0183     void *last_desc_virt;
0184     struct device *dev;
0185 };
0186
0187 #define COBALT_MAX_WIDTH            1920
0188 #define COBALT_MAX_HEIGHT           1200
0189 #define COBALT_MAX_BPP              3
0190 #define COBALT_MAX_FRAMESZ \
0191     (COBALT_MAX_WIDTH * COBALT_MAX_HEIGHT * COBALT_MAX_BPP)
0192
0193 #define NR_BUFS                 VIDEO_MAX_FRAME
0194
0195 #define COBALT_STREAM_FL_DMA_IRQ        0
0196 #define COBALT_STREAM_FL_ADV_IRQ        1
0197
0198 struct cobalt_buffer {
0199     struct vb2_v4l2_buffer vb;
0200     struct list_head list;
0201 };
0202
0203 static inline
0204 struct cobalt_buffer *to_cobalt_buffer(struct vb2_v4l2_buffer *vb2)
0205 {
0206     return container_of(vb2, struct cobalt_buffer, vb);
0207 }
0208
0209 struct cobalt_stream {
0210     struct video_device vdev;
0211     struct vb2_queue q;
0212     struct list_head bufs;
0213     struct i2c_adapter *i2c_adap;
0214     struct v4l2_subdev *sd;
0215     struct mutex lock;
0216     spinlock_t irqlock;
0217     struct v4l2_dv_timings timings;
0218     u32 input;
0219     u32 pad_source;
0220     u32 width, height, bpp;
0221     u32 stride;
0222     u32 pixfmt;
0223     u32 sequence;
0224     u32 colorspace;
0225     u32 xfer_func;
0226     u32 ycbcr_enc;
0227     u32 quantization;
0228
0229     u8 dma_channel;
0230     int video_channel;
0231     unsigned dma_fifo_mask;
0232     unsigned adv_irq_mask;
0233     struct sg_dma_desc_info dma_desc_info[NR_BUFS];
0234     unsigned long flags;
0235     bool unstable_frame;
0236     bool enable_cvi;
0237     bool enable_freewheel;
0238     unsigned skip_first_frames;
0239     bool is_output;
0240     bool is_audio;
0241     bool is_dummy;
0242
0243     struct cobalt *cobalt;
0244     struct snd_cobalt_card *alsa;
0245 };
0246
0247 struct snd_cobalt_card;
0248
0249 /* Struct to hold info about cobalt cards */
0250 struct cobalt {
0251     int instance;
0252     struct pci_dev *pci_dev;
0253     struct v4l2_device v4l2_dev;
0254     /* serialize PCI access in cobalt_s_bit_sysctrl() */
0255     struct mutex pci_lock;
0256
0257     void __iomem *bar0, *bar1;
0258
0259     u8 card_rev;
0260     u16 device_id;
0261
0262     /* device nodes */
0263     struct cobalt_stream streams[DMA_CHANNELS_MAX];
0264     struct i2c_adapter i2c_adap[COBALT_NUM_ADAPTERS];
0265     struct cobalt_i2c_data i2c_data[COBALT_NUM_ADAPTERS];
0266     bool have_hsma_rx;
0267     bool have_hsma_tx;
0268
0269     /* irq */
0270     struct workqueue_struct *irq_work_queues;
0271     struct work_struct irq_work_queue;              /* work entry */
0272     /* irq counters */
0273     u32 irq_adv1;
0274     u32 irq_adv2;
0275     u32 irq_advout;
0276     u32 irq_dma_tot;
0277     u32 irq_dma[COBALT_NUM_STREAMS];
0278     u32 irq_none;
0279     u32 irq_full_fifo;
0280
0281     /* omnitek dma */
0282     int dma_channels;
0283     int first_fifo_channel;
0284     bool pci_32_bit;
0285
0286     char hdl_info[COBALT_HDL_INFO_SIZE];
0287
0288     /* NOR flash */
0289     struct mtd_info *mtd;
0290 };
0291
0292 static inline struct cobalt *to_cobalt(struct v4l2_device *v4l2_dev)
0293 {
0294     return container_of(v4l2_dev, struct cobalt, v4l2_dev);
0295 }
0296
0297 static inline void cobalt_write_bar0(struct cobalt *cobalt, u32 reg, u32 val)
0298 {
0299     iowrite32(val, cobalt->bar0 + reg);
0300 }
0301
0302 static inline u32 cobalt_read_bar0(struct cobalt *cobalt, u32 reg)
0303 {
0304     return ioread32(cobalt->bar0 + reg);
0305 }
0306
0307 static inline void cobalt_write_bar1(struct cobalt *cobalt, u32 reg, u32 val)
0308 {
0309     iowrite32(val, cobalt->bar1 + reg);
0310 }
0311
0312 static inline u32 cobalt_read_bar1(struct cobalt *cobalt, u32 reg)
0313 {
0314     return ioread32(cobalt->bar1 + reg);
0315 }
0316
0317 static inline u32 cobalt_g_sysctrl(struct cobalt *cobalt)
0318 {
0319     return cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
0320 }
0321
0322 static inline void cobalt_s_bit_sysctrl(struct cobalt *cobalt,
0323                     int bit, int val)
0324 {
0325     u32 ctrl;
0326
0327     mutex_lock(&cobalt->pci_lock);
0328     ctrl = cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
0329     cobalt_write_bar1(cobalt, COBALT_SYS_CTRL_BASE,
0330             (ctrl & ~(1UL << bit)) | (val << bit));
0331     mutex_unlock(&cobalt->pci_lock);
0332 }
0333
0334 static inline u32 cobalt_g_sysstat(struct cobalt *cobalt)
0335 {
0336     return cobalt_read_bar1(cobalt, COBALT_SYS_STAT_BASE);
0337 }
0338
0339 #define ADRS_REG (bar1 + COBALT_BUS_BAR1_BASE + 0)
0340 #define LOWER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 4)
0341 #define UPPER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 6)
0342
0343 static inline u32 cobalt_bus_read32(void __iomem *bar1, u32 bus_adrs)
0344 {
0345     iowrite32(bus_adrs, ADRS_REG);
0346     return ioread32(LOWER_DATA);
0347 }
0348
0349 static inline void cobalt_bus_write16(void __iomem *bar1,
0350                       u32 bus_adrs, u16 data)
0351 {
0352     iowrite32(bus_adrs, ADRS_REG);
0353     if (bus_adrs & 2)
0354         iowrite16(data, UPPER_DATA);
0355     else
0356         iowrite16(data, LOWER_DATA);
0357 }
0358
0359 static inline void cobalt_bus_write32(void __iomem *bar1,
0360                       u32 bus_adrs, u16 data)
0361 {
0362     iowrite32(bus_adrs, ADRS_REG);
0363     if (bus_adrs & 2)
0364         iowrite32(data, UPPER_DATA);
0365     else
0366         iowrite32(data, LOWER_DATA);
0367 }
0368
0369 /*==============Prototypes==================*/
0370
0371 void cobalt_pcie_status_show(struct cobalt *cobalt);
0372
0373 #endif