media/i2c/tvp7002_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
0003  * Digitizer with Horizontal PLL registers
0004  *
0005  * Copyright (C) 2009 Texas Instruments Inc
0006  * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
0007  *
0008  * This code is partially based upon the TVP5150 driver
0009  * written by Mauro Carvalho Chehab <mchehab@kernel.org>,
0010  * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
0011  * and the TVP7002 driver in the TI LSP 2.10.00.14
0012  */
0013
0014 /* Naming conventions
0015  * ------------------
0016  *
0017  * FDBK:  Feedback
0018  * DIV:   Divider
0019  * CTL:   Control
0020  * SEL:   Select
0021  * IN:    Input
0022  * OUT:   Output
0023  * R:     Red
0024  * G:     Green
0025  * B:     Blue
0026  * OFF:   Offset
0027  * THRS:  Threshold
0028  * DGTL:  Digital
0029  * LVL:   Level
0030  * PWR:   Power
0031  * MVIS:  Macrovision
0032  * W:     Width
0033  * H:     Height
0034  * ALGN:  Alignment
0035  * CLK:   Clocks
0036  * TOL:   Tolerance
0037  * BWTH:  Bandwidth
0038  * COEF:  Coefficient
0039  * STAT:  Status
0040  * AUTO:  Automatic
0041  * FLD:   Field
0042  * L:     Line
0043  */
0044
0045 #define TVP7002_CHIP_REV        0x00
0046 #define TVP7002_HPLL_FDBK_DIV_MSBS  0x01
0047 #define TVP7002_HPLL_FDBK_DIV_LSBS  0x02
0048 #define TVP7002_HPLL_CRTL       0x03
0049 #define TVP7002_HPLL_PHASE_SEL      0x04
0050 #define TVP7002_CLAMP_START     0x05
0051 #define TVP7002_CLAMP_W         0x06
0052 #define TVP7002_HSYNC_OUT_W     0x07
0053 #define TVP7002_B_FINE_GAIN     0x08
0054 #define TVP7002_G_FINE_GAIN     0x09
0055 #define TVP7002_R_FINE_GAIN     0x0a
0056 #define TVP7002_B_FINE_OFF_MSBS     0x0b
0057 #define TVP7002_G_FINE_OFF_MSBS         0x0c
0058 #define TVP7002_R_FINE_OFF_MSBS         0x0d
0059 #define TVP7002_SYNC_CTL_1      0x0e
0060 #define TVP7002_HPLL_AND_CLAMP_CTL  0x0f
0061 #define TVP7002_SYNC_ON_G_THRS      0x10
0062 #define TVP7002_SYNC_SEPARATOR_THRS 0x11
0063 #define TVP7002_HPLL_PRE_COAST      0x12
0064 #define TVP7002_HPLL_POST_COAST     0x13
0065 #define TVP7002_SYNC_DETECT_STAT    0x14
0066 #define TVP7002_OUT_FORMATTER       0x15
0067 #define TVP7002_MISC_CTL_1      0x16
0068 #define TVP7002_MISC_CTL_2              0x17
0069 #define TVP7002_MISC_CTL_3              0x18
0070 #define TVP7002_IN_MUX_SEL_1        0x19
0071 #define TVP7002_IN_MUX_SEL_2            0x1a
0072 #define TVP7002_B_AND_G_COARSE_GAIN 0x1b
0073 #define TVP7002_R_COARSE_GAIN       0x1c
0074 #define TVP7002_FINE_OFF_LSBS       0x1d
0075 #define TVP7002_B_COARSE_OFF        0x1e
0076 #define TVP7002_G_COARSE_OFF            0x1f
0077 #define TVP7002_R_COARSE_OFF            0x20
0078 #define TVP7002_HSOUT_OUT_START     0x21
0079 #define TVP7002_MISC_CTL_4      0x22
0080 #define TVP7002_B_DGTL_ALC_OUT_LSBS 0x23
0081 #define TVP7002_G_DGTL_ALC_OUT_LSBS     0x24
0082 #define TVP7002_R_DGTL_ALC_OUT_LSBS     0x25
0083 #define TVP7002_AUTO_LVL_CTL_ENABLE 0x26
0084 #define TVP7002_DGTL_ALC_OUT_MSBS   0x27
0085 #define TVP7002_AUTO_LVL_CTL_FILTER 0x28
0086 /* Reserved 0x29*/
0087 #define TVP7002_FINE_CLAMP_CTL      0x2a
0088 #define TVP7002_PWR_CTL         0x2b
0089 #define TVP7002_ADC_SETUP       0x2c
0090 #define TVP7002_COARSE_CLAMP_CTL    0x2d
0091 #define TVP7002_SOG_CLAMP       0x2e
0092 #define TVP7002_RGB_COARSE_CLAMP_CTL    0x2f
0093 #define TVP7002_SOG_COARSE_CLAMP_CTL    0x30
0094 #define TVP7002_ALC_PLACEMENT       0x31
0095 /* Reserved 0x32 */
0096 /* Reserved 0x33 */
0097 #define TVP7002_MVIS_STRIPPER_W     0x34
0098 #define TVP7002_VSYNC_ALGN      0x35
0099 #define TVP7002_SYNC_BYPASS     0x36
0100 #define TVP7002_L_FRAME_STAT_LSBS   0x37
0101 #define TVP7002_L_FRAME_STAT_MSBS   0x38
0102 #define TVP7002_CLK_L_STAT_LSBS     0x39
0103 #define TVP7002_CLK_L_STAT_MSBS     0x3a
0104 #define TVP7002_HSYNC_W         0x3b
0105 #define TVP7002_VSYNC_W                 0x3c
0106 #define TVP7002_L_LENGTH_TOL        0x3d
0107 /* Reserved 0x3e */
0108 #define TVP7002_VIDEO_BWTH_CTL      0x3f
0109 #define TVP7002_AVID_START_PIXEL_LSBS   0x40
0110 #define TVP7002_AVID_START_PIXEL_MSBS   0x41
0111 #define TVP7002_AVID_STOP_PIXEL_LSBS    0x42
0112 #define TVP7002_AVID_STOP_PIXEL_MSBS    0x43
0113 #define TVP7002_VBLK_F_0_START_L_OFF    0x44
0114 #define TVP7002_VBLK_F_1_START_L_OFF    0x45
0115 #define TVP7002_VBLK_F_0_DURATION   0x46
0116 #define TVP7002_VBLK_F_1_DURATION       0x47
0117 #define TVP7002_FBIT_F_0_START_L_OFF    0x48
0118 #define TVP7002_FBIT_F_1_START_L_OFF    0x49
0119 #define TVP7002_YUV_Y_G_COEF_LSBS   0x4a
0120 #define TVP7002_YUV_Y_G_COEF_MSBS       0x4b
0121 #define TVP7002_YUV_Y_B_COEF_LSBS       0x4c
0122 #define TVP7002_YUV_Y_B_COEF_MSBS       0x4d
0123 #define TVP7002_YUV_Y_R_COEF_LSBS       0x4e
0124 #define TVP7002_YUV_Y_R_COEF_MSBS       0x4f
0125 #define TVP7002_YUV_U_G_COEF_LSBS       0x50
0126 #define TVP7002_YUV_U_G_COEF_MSBS       0x51
0127 #define TVP7002_YUV_U_B_COEF_LSBS       0x52
0128 #define TVP7002_YUV_U_B_COEF_MSBS       0x53
0129 #define TVP7002_YUV_U_R_COEF_LSBS       0x54
0130 #define TVP7002_YUV_U_R_COEF_MSBS       0x55
0131 #define TVP7002_YUV_V_G_COEF_LSBS       0x56
0132 #define TVP7002_YUV_V_G_COEF_MSBS       0x57
0133 #define TVP7002_YUV_V_B_COEF_LSBS       0x58
0134 #define TVP7002_YUV_V_B_COEF_MSBS       0x59
0135 #define TVP7002_YUV_V_R_COEF_LSBS       0x5a
0136 #define TVP7002_YUV_V_R_COEF_MSBS       0x5b
0137