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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
0003  * Digitizer with Horizontal PLL registers
0004  *
0005  * Copyright (C) 2009 Texas Instruments Inc
0006  * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
0007  *
0008  * This code is partially based upon the TVP5150 driver
0009  * written by Mauro Carvalho Chehab <mchehab@kernel.org>,
0010  * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
0011  * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
0012  * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
0013  */
0014 #include <linux/delay.h>
0015 #include <linux/i2c.h>
0016 #include <linux/slab.h>
0017 #include <linux/videodev2.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/of_graph.h>
0021 #include <linux/v4l2-dv-timings.h>
0022 #include <media/i2c/tvp7002.h>
0023 #include <media/v4l2-async.h>
0024 #include <media/v4l2-device.h>
0025 #include <media/v4l2-common.h>
0026 #include <media/v4l2-ctrls.h>
0027 #include <media/v4l2-fwnode.h>
0028 
0029 #include "tvp7002_reg.h"
0030 
0031 MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
0032 MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
0033 MODULE_LICENSE("GPL");
0034 
0035 /* I2C retry attempts */
0036 #define I2C_RETRY_COUNT     (5)
0037 
0038 /* End of registers */
0039 #define TVP7002_EOR     0x5c
0040 
0041 /* Read write definition for registers */
0042 #define TVP7002_READ        0
0043 #define TVP7002_WRITE       1
0044 #define TVP7002_RESERVED    2
0045 
0046 /* Interlaced vs progressive mask and shift */
0047 #define TVP7002_IP_SHIFT    5
0048 #define TVP7002_INPR_MASK   (0x01 << TVP7002_IP_SHIFT)
0049 
0050 /* Shift for CPL and LPF registers */
0051 #define TVP7002_CL_SHIFT    8
0052 #define TVP7002_CL_MASK     0x0f
0053 
0054 /* Debug functions */
0055 static bool debug;
0056 module_param(debug, bool, 0644);
0057 MODULE_PARM_DESC(debug, "Debug level (0-2)");
0058 
0059 /* Structure for register values */
0060 struct i2c_reg_value {
0061     u8 reg;
0062     u8 value;
0063     u8 type;
0064 };
0065 
0066 /*
0067  * Register default values (according to tvp7002 datasheet)
0068  * In the case of read-only registers, the value (0xff) is
0069  * never written. R/W functionality is controlled by the
0070  * writable bit in the register struct definition.
0071  */
0072 static const struct i2c_reg_value tvp7002_init_default[] = {
0073     { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
0074     { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
0075     { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
0076     { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
0077     { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
0078     { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
0079     { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
0080     { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
0081     { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
0082     { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
0083     { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
0084     { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
0085     { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
0086     { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
0087     { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
0088     { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
0089     { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
0090     { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
0091     { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
0092     { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
0093     { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
0094     { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
0095     { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
0096     { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
0097     { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
0098     { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
0099     { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
0100     { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
0101     { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
0102     { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
0103     { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
0104     { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
0105     { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
0106     { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
0107     { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
0108     { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
0109     { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
0110     { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
0111     { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
0112     { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
0113     { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
0114     { 0x29, 0x08, TVP7002_RESERVED },
0115     { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
0116     /* PWR_CTL is controlled only by the probe and reset functions */
0117     { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
0118     { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
0119     { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
0120     { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
0121     { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
0122     { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
0123     { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
0124     { 0x32, 0x18, TVP7002_RESERVED },
0125     { 0x33, 0x60, TVP7002_RESERVED },
0126     { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
0127     { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
0128     { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
0129     { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
0130     { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
0131     { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
0132     { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
0133     { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
0134     { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
0135     { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
0136     { 0x3e, 0x60, TVP7002_RESERVED },
0137     { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
0138     { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
0139     { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
0140     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
0141     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
0142     { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
0143     { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
0144     { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
0145     { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
0146     { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
0147     { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
0148     { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
0149     { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
0150     { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
0151     { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
0152     { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
0153     { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
0154     { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
0155     { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
0156     { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
0157     { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
0158     { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
0159     { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
0160     { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
0161     { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
0162     { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
0163     { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
0164     { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
0165     { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
0166     /* This signals end of register values */
0167     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0168 };
0169 
0170 /* Register parameters for 480P */
0171 static const struct i2c_reg_value tvp7002_parms_480P[] = {
0172     { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
0173     { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
0174     { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
0175     { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
0176     { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
0177     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
0178     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
0179     { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
0180     { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
0181     { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
0182     { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
0183     { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
0184     { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
0185     { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
0186     { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
0187     { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
0188     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0189 };
0190 
0191 /* Register parameters for 576P */
0192 static const struct i2c_reg_value tvp7002_parms_576P[] = {
0193     { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
0194     { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
0195     { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
0196     { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
0197     { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
0198     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
0199     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
0200     { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
0201     { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
0202     { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
0203     { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
0204     { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
0205     { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
0206     { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
0207     { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
0208     { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
0209     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0210 };
0211 
0212 /* Register parameters for 1080I60 */
0213 static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
0214     { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
0215     { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
0216     { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
0217     { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
0218     { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
0219     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
0220     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
0221     { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
0222     { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
0223     { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
0224     { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
0225     { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
0226     { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
0227     { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
0228     { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
0229     { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
0230     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0231 };
0232 
0233 /* Register parameters for 1080P60 */
0234 static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
0235     { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
0236     { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
0237     { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
0238     { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
0239     { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
0240     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
0241     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
0242     { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
0243     { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
0244     { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
0245     { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
0246     { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
0247     { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
0248     { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
0249     { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
0250     { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
0251     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0252 };
0253 
0254 /* Register parameters for 1080I50 */
0255 static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
0256     { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
0257     { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
0258     { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
0259     { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
0260     { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
0261     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
0262     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
0263     { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
0264     { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
0265     { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
0266     { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
0267     { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
0268     { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
0269     { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
0270     { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
0271     { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
0272     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0273 };
0274 
0275 /* Register parameters for 720P60 */
0276 static const struct i2c_reg_value tvp7002_parms_720P60[] = {
0277     { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
0278     { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
0279     { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
0280     { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
0281     { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
0282     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
0283     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
0284     { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
0285     { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
0286     { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
0287     { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
0288     { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
0289     { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
0290     { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
0291     { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
0292     { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
0293     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0294 };
0295 
0296 /* Register parameters for 720P50 */
0297 static const struct i2c_reg_value tvp7002_parms_720P50[] = {
0298     { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
0299     { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
0300     { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
0301     { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
0302     { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
0303     { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
0304     { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
0305     { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
0306     { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
0307     { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
0308     { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
0309     { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
0310     { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
0311     { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
0312     { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
0313     { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
0314     { TVP7002_EOR, 0xff, TVP7002_RESERVED }
0315 };
0316 
0317 /* Timings definition for handling device operation */
0318 struct tvp7002_timings_definition {
0319     struct v4l2_dv_timings timings;
0320     const struct i2c_reg_value *p_settings;
0321     enum v4l2_colorspace color_space;
0322     enum v4l2_field scanmode;
0323     u16 progressive;
0324     u16 lines_per_frame;
0325     u16 cpl_min;
0326     u16 cpl_max;
0327 };
0328 
0329 /* Struct list for digital video timings */
0330 static const struct tvp7002_timings_definition tvp7002_timings[] = {
0331     {
0332         V4L2_DV_BT_CEA_1280X720P60,
0333         tvp7002_parms_720P60,
0334         V4L2_COLORSPACE_REC709,
0335         V4L2_FIELD_NONE,
0336         1,
0337         0x2EE,
0338         135,
0339         153
0340     },
0341     {
0342         V4L2_DV_BT_CEA_1920X1080I60,
0343         tvp7002_parms_1080I60,
0344         V4L2_COLORSPACE_REC709,
0345         V4L2_FIELD_INTERLACED,
0346         0,
0347         0x465,
0348         181,
0349         205
0350     },
0351     {
0352         V4L2_DV_BT_CEA_1920X1080I50,
0353         tvp7002_parms_1080I50,
0354         V4L2_COLORSPACE_REC709,
0355         V4L2_FIELD_INTERLACED,
0356         0,
0357         0x465,
0358         217,
0359         245
0360     },
0361     {
0362         V4L2_DV_BT_CEA_1280X720P50,
0363         tvp7002_parms_720P50,
0364         V4L2_COLORSPACE_REC709,
0365         V4L2_FIELD_NONE,
0366         1,
0367         0x2EE,
0368         163,
0369         183
0370     },
0371     {
0372         V4L2_DV_BT_CEA_1920X1080P60,
0373         tvp7002_parms_1080P60,
0374         V4L2_COLORSPACE_REC709,
0375         V4L2_FIELD_NONE,
0376         1,
0377         0x465,
0378         90,
0379         102
0380     },
0381     {
0382         V4L2_DV_BT_CEA_720X480P59_94,
0383         tvp7002_parms_480P,
0384         V4L2_COLORSPACE_SMPTE170M,
0385         V4L2_FIELD_NONE,
0386         1,
0387         0x20D,
0388         0xffff,
0389         0xffff
0390     },
0391     {
0392         V4L2_DV_BT_CEA_720X576P50,
0393         tvp7002_parms_576P,
0394         V4L2_COLORSPACE_SMPTE170M,
0395         V4L2_FIELD_NONE,
0396         1,
0397         0x271,
0398         0xffff,
0399         0xffff
0400     }
0401 };
0402 
0403 #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings)
0404 
0405 /* Device definition */
0406 struct tvp7002 {
0407     struct v4l2_subdev sd;
0408     struct v4l2_ctrl_handler hdl;
0409     const struct tvp7002_config *pdata;
0410 
0411     int ver;
0412     int streaming;
0413 
0414     const struct tvp7002_timings_definition *current_timings;
0415     struct media_pad pad;
0416 };
0417 
0418 /*
0419  * to_tvp7002 - Obtain device handler TVP7002
0420  * @sd: ptr to v4l2_subdev struct
0421  *
0422  * Returns device handler tvp7002.
0423  */
0424 static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
0425 {
0426     return container_of(sd, struct tvp7002, sd);
0427 }
0428 
0429 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
0430 {
0431     return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
0432 }
0433 
0434 /*
0435  * tvp7002_read - Read a value from a register in an TVP7002
0436  * @sd: ptr to v4l2_subdev struct
0437  * @addr: TVP7002 register address
0438  * @dst: pointer to 8-bit destination
0439  *
0440  * Returns value read if successful, or non-zero (-1) otherwise.
0441  */
0442 static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
0443 {
0444     struct i2c_client *c = v4l2_get_subdevdata(sd);
0445     int retry;
0446     int error;
0447 
0448     for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
0449         error = i2c_smbus_read_byte_data(c, addr);
0450 
0451         if (error >= 0) {
0452             *dst = (u8)error;
0453             return 0;
0454         }
0455 
0456         msleep_interruptible(10);
0457     }
0458     v4l2_err(sd, "TVP7002 read error %d\n", error);
0459     return error;
0460 }
0461 
0462 /*
0463  * tvp7002_read_err() - Read a register value with error code
0464  * @sd: pointer to standard V4L2 sub-device structure
0465  * @reg: destination register
0466  * @val: value to be read
0467  * @err: pointer to error value
0468  *
0469  * Read a value in a register and save error value in pointer.
0470  * Also update the register table if successful
0471  */
0472 static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
0473                             u8 *dst, int *err)
0474 {
0475     if (!*err)
0476         *err = tvp7002_read(sd, reg, dst);
0477 }
0478 
0479 /*
0480  * tvp7002_write() - Write a value to a register in TVP7002
0481  * @sd: ptr to v4l2_subdev struct
0482  * @addr: TVP7002 register address
0483  * @value: value to be written to the register
0484  *
0485  * Write a value to a register in an TVP7002 decoder device.
0486  * Returns zero if successful, or non-zero otherwise.
0487  */
0488 static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
0489 {
0490     struct i2c_client *c;
0491     int retry;
0492     int error;
0493 
0494     c = v4l2_get_subdevdata(sd);
0495 
0496     for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
0497         error = i2c_smbus_write_byte_data(c, addr, value);
0498 
0499         if (error >= 0)
0500             return 0;
0501 
0502         v4l2_warn(sd, "Write: retry ... %d\n", retry);
0503         msleep_interruptible(10);
0504     }
0505     v4l2_err(sd, "TVP7002 write error %d\n", error);
0506     return error;
0507 }
0508 
0509 /*
0510  * tvp7002_write_err() - Write a register value with error code
0511  * @sd: pointer to standard V4L2 sub-device structure
0512  * @reg: destination register
0513  * @val: value to be written
0514  * @err: pointer to error value
0515  *
0516  * Write a value in a register and save error value in pointer.
0517  * Also update the register table if successful
0518  */
0519 static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
0520                             u8 val, int *err)
0521 {
0522     if (!*err)
0523         *err = tvp7002_write(sd, reg, val);
0524 }
0525 
0526 /*
0527  * tvp7002_write_inittab() - Write initialization values
0528  * @sd: ptr to v4l2_subdev struct
0529  * @regs: ptr to i2c_reg_value struct
0530  *
0531  * Write initialization values.
0532  * Returns zero or -EINVAL if read operation fails.
0533  */
0534 static int tvp7002_write_inittab(struct v4l2_subdev *sd,
0535                     const struct i2c_reg_value *regs)
0536 {
0537     int error = 0;
0538 
0539     /* Initialize the first (defined) registers */
0540     while (TVP7002_EOR != regs->reg) {
0541         if (TVP7002_WRITE == regs->type)
0542             tvp7002_write_err(sd, regs->reg, regs->value, &error);
0543         regs++;
0544     }
0545 
0546     return error;
0547 }
0548 
0549 static int tvp7002_s_dv_timings(struct v4l2_subdev *sd,
0550                     struct v4l2_dv_timings *dv_timings)
0551 {
0552     struct tvp7002 *device = to_tvp7002(sd);
0553     const struct v4l2_bt_timings *bt = &dv_timings->bt;
0554     int i;
0555 
0556     if (dv_timings->type != V4L2_DV_BT_656_1120)
0557         return -EINVAL;
0558     for (i = 0; i < NUM_TIMINGS; i++) {
0559         const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt;
0560 
0561         if (!memcmp(bt, t, &bt->standards - &bt->width)) {
0562             device->current_timings = &tvp7002_timings[i];
0563             return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings);
0564         }
0565     }
0566     return -EINVAL;
0567 }
0568 
0569 static int tvp7002_g_dv_timings(struct v4l2_subdev *sd,
0570                     struct v4l2_dv_timings *dv_timings)
0571 {
0572     struct tvp7002 *device = to_tvp7002(sd);
0573 
0574     *dv_timings = device->current_timings->timings;
0575     return 0;
0576 }
0577 
0578 /*
0579  * tvp7002_s_ctrl() - Set a control
0580  * @ctrl: ptr to v4l2_ctrl struct
0581  *
0582  * Set a control in TVP7002 decoder device.
0583  * Returns zero when successful or -EINVAL if register access fails.
0584  */
0585 static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
0586 {
0587     struct v4l2_subdev *sd = to_sd(ctrl);
0588     int error = 0;
0589 
0590     switch (ctrl->id) {
0591     case V4L2_CID_GAIN:
0592         tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
0593         tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
0594         tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
0595         return error;
0596     }
0597     return -EINVAL;
0598 }
0599 
0600 /*
0601  * tvp7002_query_dv() - query DV timings
0602  * @sd: pointer to standard V4L2 sub-device structure
0603  * @index: index into the tvp7002_timings array
0604  *
0605  * Returns the current DV timings detected by TVP7002. If no active input is
0606  * detected, returns -EINVAL
0607  */
0608 static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
0609 {
0610     const struct tvp7002_timings_definition *timings = tvp7002_timings;
0611     u8 progressive;
0612     u32 lpfr;
0613     u32 cpln;
0614     int error = 0;
0615     u8 lpf_lsb;
0616     u8 lpf_msb;
0617     u8 cpl_lsb;
0618     u8 cpl_msb;
0619 
0620     /* Return invalid index if no active input is detected */
0621     *index = NUM_TIMINGS;
0622 
0623     /* Read standards from device registers */
0624     tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
0625     tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
0626 
0627     if (error < 0)
0628         return error;
0629 
0630     tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
0631     tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
0632 
0633     if (error < 0)
0634         return error;
0635 
0636     /* Get lines per frame, clocks per line and interlaced/progresive */
0637     lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
0638     cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
0639     progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
0640 
0641     /* Do checking of video modes */
0642     for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++)
0643         if (lpfr == timings->lines_per_frame &&
0644             progressive == timings->progressive) {
0645             if (timings->cpl_min == 0xffff)
0646                 break;
0647             if (cpln >= timings->cpl_min && cpln <= timings->cpl_max)
0648                 break;
0649         }
0650 
0651     if (*index == NUM_TIMINGS) {
0652         v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
0653                                 lpfr, cpln);
0654         return -ENOLINK;
0655     }
0656 
0657     /* Update lines per frame and clocks per line info */
0658     v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index);
0659     return 0;
0660 }
0661 
0662 static int tvp7002_query_dv_timings(struct v4l2_subdev *sd,
0663                     struct v4l2_dv_timings *timings)
0664 {
0665     int index;
0666     int err = tvp7002_query_dv(sd, &index);
0667 
0668     if (err)
0669         return err;
0670     *timings = tvp7002_timings[index].timings;
0671     return 0;
0672 }
0673 
0674 #ifdef CONFIG_VIDEO_ADV_DEBUG
0675 /*
0676  * tvp7002_g_register() - Get the value of a register
0677  * @sd: ptr to v4l2_subdev struct
0678  * @reg: ptr to v4l2_dbg_register struct
0679  *
0680  * Get the value of a TVP7002 decoder device register.
0681  * Returns zero when successful, -EINVAL if register read fails or
0682  * access to I2C client fails.
0683  */
0684 static int tvp7002_g_register(struct v4l2_subdev *sd,
0685                         struct v4l2_dbg_register *reg)
0686 {
0687     u8 val;
0688     int ret;
0689 
0690     ret = tvp7002_read(sd, reg->reg & 0xff, &val);
0691     if (ret < 0)
0692         return ret;
0693     reg->val = val;
0694     reg->size = 1;
0695     return 0;
0696 }
0697 
0698 /*
0699  * tvp7002_s_register() - set a control
0700  * @sd: ptr to v4l2_subdev struct
0701  * @reg: ptr to v4l2_dbg_register struct
0702  *
0703  * Get the value of a TVP7002 decoder device register.
0704  * Returns zero when successful, -EINVAL if register read fails.
0705  */
0706 static int tvp7002_s_register(struct v4l2_subdev *sd,
0707                         const struct v4l2_dbg_register *reg)
0708 {
0709     return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
0710 }
0711 #endif
0712 
0713 /*
0714  * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
0715  * @sd: pointer to standard V4L2 sub-device structure
0716  * @enable: streaming enable or disable
0717  *
0718  * Sets streaming to enable or disable, if possible.
0719  */
0720 static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
0721 {
0722     struct tvp7002 *device = to_tvp7002(sd);
0723     int error;
0724 
0725     if (device->streaming == enable)
0726         return 0;
0727 
0728     /* low impedance: on, high impedance: off */
0729     error = tvp7002_write(sd, TVP7002_MISC_CTL_2, enable ? 0x00 : 0x03);
0730     if (error) {
0731         v4l2_dbg(1, debug, sd, "Fail to set streaming\n");
0732         return error;
0733     }
0734 
0735     device->streaming = enable;
0736     return 0;
0737 }
0738 
0739 /*
0740  * tvp7002_log_status() - Print information about register settings
0741  * @sd: ptr to v4l2_subdev struct
0742  *
0743  * Log register values of a TVP7002 decoder device.
0744  * Returns zero or -EINVAL if read operation fails.
0745  */
0746 static int tvp7002_log_status(struct v4l2_subdev *sd)
0747 {
0748     struct tvp7002 *device = to_tvp7002(sd);
0749     const struct v4l2_bt_timings *bt;
0750     int detected;
0751 
0752     /* Find my current timings */
0753     tvp7002_query_dv(sd, &detected);
0754 
0755     bt = &device->current_timings->timings.bt;
0756     v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height);
0757     if (detected == NUM_TIMINGS) {
0758         v4l2_info(sd, "Detected DV Timings: None\n");
0759     } else {
0760         bt = &tvp7002_timings[detected].timings.bt;
0761         v4l2_info(sd, "Detected DV Timings: %ux%u\n",
0762                 bt->width, bt->height);
0763     }
0764     v4l2_info(sd, "Streaming enabled: %s\n",
0765                     device->streaming ? "yes" : "no");
0766 
0767     /* Print the current value of the gain control */
0768     v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
0769 
0770     return 0;
0771 }
0772 
0773 static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
0774         struct v4l2_enum_dv_timings *timings)
0775 {
0776     if (timings->pad != 0)
0777         return -EINVAL;
0778 
0779     /* Check requested format index is within range */
0780     if (timings->index >= NUM_TIMINGS)
0781         return -EINVAL;
0782 
0783     timings->timings = tvp7002_timings[timings->index].timings;
0784     return 0;
0785 }
0786 
0787 static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
0788     .s_ctrl = tvp7002_s_ctrl,
0789 };
0790 
0791 /*
0792  * tvp7002_enum_mbus_code() - Enum supported digital video format on pad
0793  * @sd: pointer to standard V4L2 sub-device structure
0794  * @cfg: pad configuration
0795  * @code: pointer to subdev enum mbus code struct
0796  *
0797  * Enumerate supported digital video formats for pad.
0798  */
0799 static int
0800 tvp7002_enum_mbus_code(struct v4l2_subdev *sd,
0801                struct v4l2_subdev_state *sd_state,
0802                struct v4l2_subdev_mbus_code_enum *code)
0803 {
0804     /* Check requested format index is within range */
0805     if (code->index != 0)
0806         return -EINVAL;
0807 
0808     code->code = MEDIA_BUS_FMT_YUYV10_1X20;
0809 
0810     return 0;
0811 }
0812 
0813 /*
0814  * tvp7002_get_pad_format() - get video format on pad
0815  * @sd: pointer to standard V4L2 sub-device structure
0816  * @cfg: pad configuration
0817  * @fmt: pointer to subdev format struct
0818  *
0819  * get video format for pad.
0820  */
0821 static int
0822 tvp7002_get_pad_format(struct v4l2_subdev *sd,
0823                struct v4l2_subdev_state *sd_state,
0824                struct v4l2_subdev_format *fmt)
0825 {
0826     struct tvp7002 *tvp7002 = to_tvp7002(sd);
0827 
0828     fmt->format.code = MEDIA_BUS_FMT_YUYV10_1X20;
0829     fmt->format.width = tvp7002->current_timings->timings.bt.width;
0830     fmt->format.height = tvp7002->current_timings->timings.bt.height;
0831     fmt->format.field = tvp7002->current_timings->scanmode;
0832     fmt->format.colorspace = tvp7002->current_timings->color_space;
0833 
0834     return 0;
0835 }
0836 
0837 /*
0838  * tvp7002_set_pad_format() - set video format on pad
0839  * @sd: pointer to standard V4L2 sub-device structure
0840  * @cfg: pad configuration
0841  * @fmt: pointer to subdev format struct
0842  *
0843  * set video format for pad.
0844  */
0845 static int
0846 tvp7002_set_pad_format(struct v4l2_subdev *sd,
0847                struct v4l2_subdev_state *sd_state,
0848                struct v4l2_subdev_format *fmt)
0849 {
0850     return tvp7002_get_pad_format(sd, sd_state, fmt);
0851 }
0852 
0853 /* V4L2 core operation handlers */
0854 static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
0855     .log_status = tvp7002_log_status,
0856 #ifdef CONFIG_VIDEO_ADV_DEBUG
0857     .g_register = tvp7002_g_register,
0858     .s_register = tvp7002_s_register,
0859 #endif
0860 };
0861 
0862 /* Specific video subsystem operation handlers */
0863 static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
0864     .g_dv_timings = tvp7002_g_dv_timings,
0865     .s_dv_timings = tvp7002_s_dv_timings,
0866     .query_dv_timings = tvp7002_query_dv_timings,
0867     .s_stream = tvp7002_s_stream,
0868 };
0869 
0870 /* media pad related operation handlers */
0871 static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = {
0872     .enum_mbus_code = tvp7002_enum_mbus_code,
0873     .get_fmt = tvp7002_get_pad_format,
0874     .set_fmt = tvp7002_set_pad_format,
0875     .enum_dv_timings = tvp7002_enum_dv_timings,
0876 };
0877 
0878 /* V4L2 top level operation handlers */
0879 static const struct v4l2_subdev_ops tvp7002_ops = {
0880     .core = &tvp7002_core_ops,
0881     .video = &tvp7002_video_ops,
0882     .pad = &tvp7002_pad_ops,
0883 };
0884 
0885 static struct tvp7002_config *
0886 tvp7002_get_pdata(struct i2c_client *client)
0887 {
0888     struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
0889     struct tvp7002_config *pdata = NULL;
0890     struct device_node *endpoint;
0891     unsigned int flags;
0892 
0893     if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
0894         return client->dev.platform_data;
0895 
0896     endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
0897     if (!endpoint)
0898         return NULL;
0899 
0900     if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg))
0901         goto done;
0902 
0903     pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
0904     if (!pdata)
0905         goto done;
0906 
0907     flags = bus_cfg.bus.parallel.flags;
0908 
0909     if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
0910         pdata->hs_polarity = 1;
0911 
0912     if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
0913         pdata->vs_polarity = 1;
0914 
0915     if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
0916         pdata->clk_polarity = 1;
0917 
0918     if (flags & V4L2_MBUS_FIELD_EVEN_HIGH)
0919         pdata->fid_polarity = 1;
0920 
0921     if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH)
0922         pdata->sog_polarity = 1;
0923 
0924 done:
0925     of_node_put(endpoint);
0926     return pdata;
0927 }
0928 
0929 /*
0930  * tvp7002_probe - Probe a TVP7002 device
0931  * @c: ptr to i2c_client struct
0932  * @id: ptr to i2c_device_id struct
0933  *
0934  * Initialize the TVP7002 device
0935  * Returns zero when successful, -EINVAL if register read fails or
0936  * -EIO if i2c access is not available.
0937  */
0938 static int tvp7002_probe(struct i2c_client *c)
0939 {
0940     struct tvp7002_config *pdata = tvp7002_get_pdata(c);
0941     struct v4l2_subdev *sd;
0942     struct tvp7002 *device;
0943     struct v4l2_dv_timings timings;
0944     int polarity_a;
0945     int polarity_b;
0946     u8 revision;
0947     int error;
0948 
0949     if (pdata == NULL) {
0950         dev_err(&c->dev, "No platform data\n");
0951         return -EINVAL;
0952     }
0953 
0954     /* Check if the adapter supports the needed features */
0955     if (!i2c_check_functionality(c->adapter,
0956         I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
0957         return -EIO;
0958 
0959     device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
0960 
0961     if (!device)
0962         return -ENOMEM;
0963 
0964     sd = &device->sd;
0965     device->pdata = pdata;
0966     device->current_timings = tvp7002_timings;
0967 
0968     /* Tell v4l2 the device is ready */
0969     v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
0970     v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
0971                     c->addr, c->adapter->name);
0972 
0973     error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
0974     if (error < 0)
0975         return error;
0976 
0977     /* Get revision number */
0978     v4l2_info(sd, "Rev. %02x detected.\n", revision);
0979     if (revision != 0x02)
0980         v4l2_info(sd, "Unknown revision detected.\n");
0981 
0982     /* Initializes TVP7002 to its default values */
0983     error = tvp7002_write_inittab(sd, tvp7002_init_default);
0984 
0985     if (error < 0)
0986         return error;
0987 
0988     /* Set polarity information after registers have been set */
0989     polarity_a = 0x20 | device->pdata->hs_polarity << 5
0990             | device->pdata->vs_polarity << 2;
0991     error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
0992     if (error < 0)
0993         return error;
0994 
0995     polarity_b = 0x01  | device->pdata->fid_polarity << 2
0996             | device->pdata->sog_polarity << 1
0997             | device->pdata->clk_polarity;
0998     error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
0999     if (error < 0)
1000         return error;
1001 
1002     /* Set registers according to default video mode */
1003     timings = device->current_timings->timings;
1004     error = tvp7002_s_dv_timings(sd, &timings);
1005 
1006 #if defined(CONFIG_MEDIA_CONTROLLER)
1007     device->pad.flags = MEDIA_PAD_FL_SOURCE;
1008     device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1009     device->sd.entity.function = MEDIA_ENT_F_ATV_DECODER;
1010 
1011     error = media_entity_pads_init(&device->sd.entity, 1, &device->pad);
1012     if (error < 0)
1013         return error;
1014 #endif
1015 
1016     v4l2_ctrl_handler_init(&device->hdl, 1);
1017     v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
1018             V4L2_CID_GAIN, 0, 255, 1, 0);
1019     sd->ctrl_handler = &device->hdl;
1020     if (device->hdl.error) {
1021         error = device->hdl.error;
1022         goto error;
1023     }
1024     v4l2_ctrl_handler_setup(&device->hdl);
1025 
1026     error = v4l2_async_register_subdev(&device->sd);
1027     if (error)
1028         goto error;
1029 
1030     return 0;
1031 
1032 error:
1033     v4l2_ctrl_handler_free(&device->hdl);
1034 #if defined(CONFIG_MEDIA_CONTROLLER)
1035     media_entity_cleanup(&device->sd.entity);
1036 #endif
1037     return error;
1038 }
1039 
1040 /*
1041  * tvp7002_remove - Remove TVP7002 device support
1042  * @c: ptr to i2c_client struct
1043  *
1044  * Reset the TVP7002 device
1045  * Returns zero.
1046  */
1047 static int tvp7002_remove(struct i2c_client *c)
1048 {
1049     struct v4l2_subdev *sd = i2c_get_clientdata(c);
1050     struct tvp7002 *device = to_tvp7002(sd);
1051 
1052     v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
1053                 "on address 0x%x\n", c->addr);
1054     v4l2_async_unregister_subdev(&device->sd);
1055 #if defined(CONFIG_MEDIA_CONTROLLER)
1056     media_entity_cleanup(&device->sd.entity);
1057 #endif
1058     v4l2_ctrl_handler_free(&device->hdl);
1059     return 0;
1060 }
1061 
1062 /* I2C Device ID table */
1063 static const struct i2c_device_id tvp7002_id[] = {
1064     { "tvp7002", 0 },
1065     { }
1066 };
1067 MODULE_DEVICE_TABLE(i2c, tvp7002_id);
1068 
1069 #if IS_ENABLED(CONFIG_OF)
1070 static const struct of_device_id tvp7002_of_match[] = {
1071     { .compatible = "ti,tvp7002", },
1072     { /* sentinel */ },
1073 };
1074 MODULE_DEVICE_TABLE(of, tvp7002_of_match);
1075 #endif
1076 
1077 /* I2C driver data */
1078 static struct i2c_driver tvp7002_driver = {
1079     .driver = {
1080         .of_match_table = of_match_ptr(tvp7002_of_match),
1081         .name = TVP7002_MODULE_NAME,
1082     },
1083     .probe_new = tvp7002_probe,
1084     .remove = tvp7002_remove,
1085     .id_table = tvp7002_id,
1086 };
1087 
1088 module_i2c_driver(tvp7002_driver);
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