media/i2c/tvp514x_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * drivers/media/i2c/tvp514x_regs.h
0004  *
0005  * Copyright (C) 2008 Texas Instruments Inc
0006  * Author: Vaibhav Hiremath <hvaibhav@ti.com>
0007  *
0008  * Contributors:
0009  *     Sivaraj R <sivaraj@ti.com>
0010  *     Brijesh R Jadav <brijesh.j@ti.com>
0011  *     Hardik Shah <hardik.shah@ti.com>
0012  *     Manjunath Hadli <mrh@ti.com>
0013  *     Karicheri Muralidharan <m-karicheri2@ti.com>
0014  */
0015
0016 #ifndef _TVP514X_REGS_H
0017 #define _TVP514X_REGS_H
0018
0019 /*
0020  * TVP5146/47 registers
0021  */
0022 #define REG_INPUT_SEL           (0x00)
0023 #define REG_AFE_GAIN_CTRL       (0x01)
0024 #define REG_VIDEO_STD           (0x02)
0025 #define REG_OPERATION_MODE      (0x03)
0026 #define REG_AUTOSWITCH_MASK     (0x04)
0027
0028 #define REG_COLOR_KILLER        (0x05)
0029 #define REG_LUMA_CONTROL1       (0x06)
0030 #define REG_LUMA_CONTROL2       (0x07)
0031 #define REG_LUMA_CONTROL3       (0x08)
0032
0033 #define REG_BRIGHTNESS          (0x09)
0034 #define REG_CONTRAST            (0x0A)
0035 #define REG_SATURATION          (0x0B)
0036 #define REG_HUE             (0x0C)
0037
0038 #define REG_CHROMA_CONTROL1     (0x0D)
0039 #define REG_CHROMA_CONTROL2     (0x0E)
0040
0041 /* 0x0F Reserved */
0042
0043 #define REG_COMP_PR_SATURATION      (0x10)
0044 #define REG_COMP_Y_CONTRAST     (0x11)
0045 #define REG_COMP_PB_SATURATION      (0x12)
0046
0047 /* 0x13 Reserved */
0048
0049 #define REG_COMP_Y_BRIGHTNESS       (0x14)
0050
0051 /* 0x15 Reserved */
0052
0053 #define REG_AVID_START_PIXEL_LSB    (0x16)
0054 #define REG_AVID_START_PIXEL_MSB    (0x17)
0055 #define REG_AVID_STOP_PIXEL_LSB     (0x18)
0056 #define REG_AVID_STOP_PIXEL_MSB     (0x19)
0057
0058 #define REG_HSYNC_START_PIXEL_LSB   (0x1A)
0059 #define REG_HSYNC_START_PIXEL_MSB   (0x1B)
0060 #define REG_HSYNC_STOP_PIXEL_LSB    (0x1C)
0061 #define REG_HSYNC_STOP_PIXEL_MSB    (0x1D)
0062
0063 #define REG_VSYNC_START_LINE_LSB    (0x1E)
0064 #define REG_VSYNC_START_LINE_MSB    (0x1F)
0065 #define REG_VSYNC_STOP_LINE_LSB     (0x20)
0066 #define REG_VSYNC_STOP_LINE_MSB     (0x21)
0067
0068 #define REG_VBLK_START_LINE_LSB     (0x22)
0069 #define REG_VBLK_START_LINE_MSB     (0x23)
0070 #define REG_VBLK_STOP_LINE_LSB      (0x24)
0071 #define REG_VBLK_STOP_LINE_MSB      (0x25)
0072
0073 /* 0x26 - 0x27 Reserved */
0074
0075 #define REG_FAST_SWTICH_CONTROL     (0x28)
0076
0077 /* 0x29 Reserved */
0078
0079 #define REG_FAST_SWTICH_SCART_DELAY (0x2A)
0080
0081 /* 0x2B Reserved */
0082
0083 #define REG_SCART_DELAY         (0x2C)
0084 #define REG_CTI_DELAY           (0x2D)
0085 #define REG_CTI_CONTROL         (0x2E)
0086
0087 /* 0x2F - 0x31 Reserved */
0088
0089 #define REG_SYNC_CONTROL        (0x32)
0090 #define REG_OUTPUT_FORMATTER1       (0x33)
0091 #define REG_OUTPUT_FORMATTER2       (0x34)
0092 #define REG_OUTPUT_FORMATTER3       (0x35)
0093 #define REG_OUTPUT_FORMATTER4       (0x36)
0094 #define REG_OUTPUT_FORMATTER5       (0x37)
0095 #define REG_OUTPUT_FORMATTER6       (0x38)
0096 #define REG_CLEAR_LOST_LOCK     (0x39)
0097
0098 #define REG_STATUS1         (0x3A)
0099 #define REG_STATUS2         (0x3B)
0100
0101 #define REG_AGC_GAIN_STATUS_LSB     (0x3C)
0102 #define REG_AGC_GAIN_STATUS_MSB     (0x3D)
0103
0104 /* 0x3E Reserved */
0105
0106 #define REG_VIDEO_STD_STATUS        (0x3F)
0107 #define REG_GPIO_INPUT1         (0x40)
0108 #define REG_GPIO_INPUT2         (0x41)
0109
0110 /* 0x42 - 0x45 Reserved */
0111
0112 #define REG_AFE_COARSE_GAIN_CH1     (0x46)
0113 #define REG_AFE_COARSE_GAIN_CH2     (0x47)
0114 #define REG_AFE_COARSE_GAIN_CH3     (0x48)
0115 #define REG_AFE_COARSE_GAIN_CH4     (0x49)
0116
0117 #define REG_AFE_FINE_GAIN_PB_B_LSB  (0x4A)
0118 #define REG_AFE_FINE_GAIN_PB_B_MSB  (0x4B)
0119 #define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB    (0x4C)
0120 #define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB    (0x4D)
0121 #define REG_AFE_FINE_GAIN_PR_R_LSB  (0x4E)
0122 #define REG_AFE_FINE_GAIN_PR_R_MSB  (0x4F)
0123 #define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50)
0124 #define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51)
0125
0126 /* 0x52 - 0x68 Reserved */
0127
0128 #define REG_FBIT_VBIT_CONTROL1      (0x69)
0129
0130 /* 0x6A - 0x6B Reserved */
0131
0132 #define REG_BACKEND_AGC_CONTROL     (0x6C)
0133
0134 /* 0x6D - 0x6E Reserved */
0135
0136 #define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F)
0137 #define REG_ROM_VERSION         (0x70)
0138
0139 /* 0x71 - 0x73 Reserved */
0140
0141 #define REG_AGC_WHITE_PEAK_PROCESSING   (0x74)
0142 #define REG_FBIT_VBIT_CONTROL2      (0x75)
0143 #define REG_VCR_TRICK_MODE_CONTROL  (0x76)
0144 #define REG_HORIZONTAL_SHAKE_INCREMENT  (0x77)
0145 #define REG_AGC_INCREMENT_SPEED     (0x78)
0146 #define REG_AGC_INCREMENT_DELAY     (0x79)
0147
0148 /* 0x7A - 0x7F Reserved */
0149
0150 #define REG_CHIP_ID_MSB         (0x80)
0151 #define REG_CHIP_ID_LSB         (0x81)
0152
0153 /* 0x82 Reserved */
0154
0155 #define REG_CPLL_SPEED_CONTROL      (0x83)
0156
0157 /* 0x84 - 0x96 Reserved */
0158
0159 #define REG_STATUS_REQUEST      (0x97)
0160
0161 /* 0x98 - 0x99 Reserved */
0162
0163 #define REG_VERTICAL_LINE_COUNT_LSB (0x9A)
0164 #define REG_VERTICAL_LINE_COUNT_MSB (0x9B)
0165
0166 /* 0x9C - 0x9D Reserved */
0167
0168 #define REG_AGC_DECREMENT_DELAY     (0x9E)
0169
0170 /* 0x9F - 0xB0 Reserved */
0171
0172 #define REG_VDP_TTX_FILTER_1_MASK1  (0xB1)
0173 #define REG_VDP_TTX_FILTER_1_MASK2  (0xB2)
0174 #define REG_VDP_TTX_FILTER_1_MASK3  (0xB3)
0175 #define REG_VDP_TTX_FILTER_1_MASK4  (0xB4)
0176 #define REG_VDP_TTX_FILTER_1_MASK5  (0xB5)
0177 #define REG_VDP_TTX_FILTER_2_MASK1  (0xB6)
0178 #define REG_VDP_TTX_FILTER_2_MASK2  (0xB7)
0179 #define REG_VDP_TTX_FILTER_2_MASK3  (0xB8)
0180 #define REG_VDP_TTX_FILTER_2_MASK4  (0xB9)
0181 #define REG_VDP_TTX_FILTER_2_MASK5  (0xBA)
0182 #define REG_VDP_TTX_FILTER_CONTROL  (0xBB)
0183 #define REG_VDP_FIFO_WORD_COUNT     (0xBC)
0184 #define REG_VDP_FIFO_INTERRUPT_THRLD    (0xBD)
0185
0186 /* 0xBE Reserved */
0187
0188 #define REG_VDP_FIFO_RESET      (0xBF)
0189 #define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0)
0190 #define REG_VDP_LINE_NUMBER_INTERRUPT   (0xC1)
0191 #define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2)
0192 #define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3)
0193
0194 /* 0xC4 - 0xD5 Reserved */
0195
0196 #define REG_VDP_LINE_START      (0xD6)
0197 #define REG_VDP_LINE_STOP       (0xD7)
0198 #define REG_VDP_GLOBAL_LINE_MODE    (0xD8)
0199 #define REG_VDP_FULL_FIELD_ENABLE   (0xD9)
0200 #define REG_VDP_FULL_FIELD_MODE     (0xDA)
0201
0202 /* 0xDB - 0xDF Reserved */
0203
0204 #define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR  (0xE0)
0205 #define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1)
0206 #define REG_FIFO_READ_DATA          (0xE2)
0207
0208 /* 0xE3 - 0xE7 Reserved */
0209
0210 #define REG_VBUS_ADDRESS_ACCESS1    (0xE8)
0211 #define REG_VBUS_ADDRESS_ACCESS2    (0xE9)
0212 #define REG_VBUS_ADDRESS_ACCESS3    (0xEA)
0213
0214 /* 0xEB - 0xEF Reserved */
0215
0216 #define REG_INTERRUPT_RAW_STATUS0   (0xF0)
0217 #define REG_INTERRUPT_RAW_STATUS1   (0xF1)
0218 #define REG_INTERRUPT_STATUS0       (0xF2)
0219 #define REG_INTERRUPT_STATUS1       (0xF3)
0220 #define REG_INTERRUPT_MASK0     (0xF4)
0221 #define REG_INTERRUPT_MASK1     (0xF5)
0222 #define REG_INTERRUPT_CLEAR0        (0xF6)
0223 #define REG_INTERRUPT_CLEAR1        (0xF7)
0224
0225 /* 0xF8 - 0xFF Reserved */
0226
0227 /*
0228  * Mask and bit definitions of TVP5146/47 registers
0229  */
0230 /* The ID values we are looking for */
0231 #define TVP514X_CHIP_ID_MSB     (0x51)
0232 #define TVP5146_CHIP_ID_LSB     (0x46)
0233 #define TVP5147_CHIP_ID_LSB     (0x47)
0234
0235 #define VIDEO_STD_MASK          (0x07)
0236 #define VIDEO_STD_AUTO_SWITCH_BIT   (0x00)
0237 #define VIDEO_STD_NTSC_MJ_BIT       (0x01)
0238 #define VIDEO_STD_PAL_BDGHIN_BIT    (0x02)
0239 #define VIDEO_STD_PAL_M_BIT     (0x03)
0240 #define VIDEO_STD_PAL_COMBINATION_N_BIT (0x04)
0241 #define VIDEO_STD_NTSC_4_43_BIT     (0x05)
0242 #define VIDEO_STD_SECAM_BIT     (0x06)
0243 #define VIDEO_STD_PAL_60_BIT        (0x07)
0244
0245 /*
0246  * Status bit
0247  */
0248 #define STATUS_TV_VCR_BIT       (1<<0)
0249 #define STATUS_HORZ_SYNC_LOCK_BIT   (1<<1)
0250 #define STATUS_VIRT_SYNC_LOCK_BIT   (1<<2)
0251 #define STATUS_CLR_SUBCAR_LOCK_BIT  (1<<3)
0252 #define STATUS_LOST_LOCK_DETECT_BIT (1<<4)
0253 #define STATUS_FEILD_RATE_BIT       (1<<5)
0254 #define STATUS_LINE_ALTERNATING_BIT (1<<6)
0255 #define STATUS_PEAK_WHITE_DETECT_BIT    (1<<7)
0256
0257 /* Tokens for register write */
0258 #define TOK_WRITE                       (0)     /* token for write operation */
0259 #define TOK_TERM                        (1)     /* terminating token */
0260 #define TOK_DELAY                       (2)     /* delay token for reg list */
0261 #define TOK_SKIP                        (3)     /* token to skip a register */
0262 /**
0263  * struct tvp514x_reg - Structure for TVP5146/47 register initialization values
0264  * @token: Token: TOK_WRITE, TOK_TERM etc..
0265  * @reg: Register offset
0266  * @val: Register Value for TOK_WRITE or delay in ms for TOK_DELAY
0267  */
0268 struct tvp514x_reg {
0269     u8 token;
0270     u8 reg;
0271     u32 val;
0272 };
0273
0274 #endif              /* ifndef _TVP514X_REGS_H */