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0025 #include <linux/module.h>
0026 #include <linux/kernel.h>
0027 #include <linux/sched.h>
0028 #include <linux/string.h>
0029 #include <linux/timer.h>
0030 #include <linux/delay.h>
0031 #include <linux/errno.h>
0032 #include <linux/slab.h>
0033 #include <linux/videodev2.h>
0034 #include <linux/i2c.h>
0035 #include <linux/init.h>
0036 #include <linux/kthread.h>
0037 #include <linux/freezer.h>
0038
0039 #include <media/i2c/tvaudio.h>
0040 #include <media/v4l2-device.h>
0041 #include <media/v4l2-ctrls.h>
0042
0043
0044
0045
0046 static int debug;
0047 module_param(debug, int, 0644);
0048
0049 MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
0050 MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
0051 MODULE_LICENSE("GPL");
0052
0053 #define UNSET (-1U)
0054
0055
0056
0057
0058 #define MAXREGS 256
0059
0060 struct CHIPSTATE;
0061 typedef int (*getvalue)(int);
0062 typedef int (*checkit)(struct CHIPSTATE*);
0063 typedef int (*initialize)(struct CHIPSTATE*);
0064 typedef int (*getrxsubchans)(struct CHIPSTATE *);
0065 typedef void (*setaudmode)(struct CHIPSTATE*, int mode);
0066
0067
0068 typedef struct AUDIOCMD {
0069 int count;
0070 unsigned char bytes[MAXREGS+1];
0071 } audiocmd;
0072
0073
0074 struct CHIPDESC {
0075 char *name;
0076 int addr_lo, addr_hi;
0077 int registers;
0078
0079 int *insmodopt;
0080 checkit checkit;
0081 initialize initialize;
0082 int flags;
0083 #define CHIP_HAS_VOLUME 1
0084 #define CHIP_HAS_BASSTREBLE 2
0085 #define CHIP_HAS_INPUTSEL 4
0086 #define CHIP_NEED_CHECKMODE 8
0087
0088
0089 audiocmd init;
0090
0091
0092 int leftreg, rightreg, treblereg, bassreg;
0093
0094
0095 int volinit, trebleinit, bassinit;
0096
0097
0098 getvalue volfunc, treblefunc, bassfunc;
0099
0100
0101 getrxsubchans getrxsubchans;
0102 setaudmode setaudmode;
0103
0104
0105 int inputreg;
0106 int inputmap[4];
0107 int inputmute;
0108 int inputmask;
0109 };
0110
0111
0112 struct CHIPSTATE {
0113 struct v4l2_subdev sd;
0114 struct v4l2_ctrl_handler hdl;
0115 struct {
0116
0117 struct v4l2_ctrl *volume;
0118 struct v4l2_ctrl *balance;
0119 };
0120
0121
0122
0123 struct CHIPDESC *desc;
0124
0125
0126 audiocmd shadow;
0127
0128
0129 u16 muted;
0130 int prevmode;
0131 int radio;
0132 int input;
0133
0134
0135 struct task_struct *thread;
0136 struct timer_list wt;
0137 int audmode;
0138 };
0139
0140 static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
0141 {
0142 return container_of(sd, struct CHIPSTATE, sd);
0143 }
0144
0145 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
0146 {
0147 return &container_of(ctrl->handler, struct CHIPSTATE, hdl)->sd;
0148 }
0149
0150
0151
0152
0153
0154 static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
0155 {
0156 struct v4l2_subdev *sd = &chip->sd;
0157 struct i2c_client *c = v4l2_get_subdevdata(sd);
0158 unsigned char buffer[2];
0159 int rc;
0160
0161 if (subaddr < 0) {
0162 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
0163 chip->shadow.bytes[1] = val;
0164 buffer[0] = val;
0165 rc = i2c_master_send(c, buffer, 1);
0166 if (rc != 1) {
0167 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
0168 if (rc < 0)
0169 return rc;
0170 return -EIO;
0171 }
0172 } else {
0173 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
0174 v4l2_info(sd,
0175 "Tried to access a non-existent register: %d\n",
0176 subaddr);
0177 return -EINVAL;
0178 }
0179
0180 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
0181 subaddr, val);
0182 chip->shadow.bytes[subaddr+1] = val;
0183 buffer[0] = subaddr;
0184 buffer[1] = val;
0185 rc = i2c_master_send(c, buffer, 2);
0186 if (rc != 2) {
0187 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
0188 subaddr, val);
0189 if (rc < 0)
0190 return rc;
0191 return -EIO;
0192 }
0193 }
0194 return 0;
0195 }
0196
0197 static int chip_write_masked(struct CHIPSTATE *chip,
0198 int subaddr, int val, int mask)
0199 {
0200 struct v4l2_subdev *sd = &chip->sd;
0201
0202 if (mask != 0) {
0203 if (subaddr < 0) {
0204 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
0205 } else {
0206 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
0207 v4l2_info(sd,
0208 "Tried to access a non-existent register: %d\n",
0209 subaddr);
0210 return -EINVAL;
0211 }
0212
0213 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
0214 }
0215 }
0216 return chip_write(chip, subaddr, val);
0217 }
0218
0219 static int chip_read(struct CHIPSTATE *chip)
0220 {
0221 struct v4l2_subdev *sd = &chip->sd;
0222 struct i2c_client *c = v4l2_get_subdevdata(sd);
0223 unsigned char buffer;
0224 int rc;
0225
0226 rc = i2c_master_recv(c, &buffer, 1);
0227 if (rc != 1) {
0228 v4l2_warn(sd, "I/O error (read)\n");
0229 if (rc < 0)
0230 return rc;
0231 return -EIO;
0232 }
0233 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
0234 return buffer;
0235 }
0236
0237 static int chip_read2(struct CHIPSTATE *chip, int subaddr)
0238 {
0239 struct v4l2_subdev *sd = &chip->sd;
0240 struct i2c_client *c = v4l2_get_subdevdata(sd);
0241 int rc;
0242 unsigned char write[1];
0243 unsigned char read[1];
0244 struct i2c_msg msgs[2] = {
0245 {
0246 .addr = c->addr,
0247 .len = 1,
0248 .buf = write
0249 },
0250 {
0251 .addr = c->addr,
0252 .flags = I2C_M_RD,
0253 .len = 1,
0254 .buf = read
0255 }
0256 };
0257
0258 write[0] = subaddr;
0259
0260 rc = i2c_transfer(c->adapter, msgs, 2);
0261 if (rc != 2) {
0262 v4l2_warn(sd, "I/O error (read2)\n");
0263 if (rc < 0)
0264 return rc;
0265 return -EIO;
0266 }
0267 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
0268 subaddr, read[0]);
0269 return read[0];
0270 }
0271
0272 static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
0273 {
0274 struct v4l2_subdev *sd = &chip->sd;
0275 struct i2c_client *c = v4l2_get_subdevdata(sd);
0276 int i, rc;
0277
0278 if (0 == cmd->count)
0279 return 0;
0280
0281 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
0282 v4l2_info(sd,
0283 "Tried to access a non-existent register range: %d to %d\n",
0284 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
0285 return -EINVAL;
0286 }
0287
0288
0289
0290
0291 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
0292 name, cmd->bytes[0]);
0293 for (i = 1; i < cmd->count; i++) {
0294 if (debug)
0295 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
0296 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
0297 }
0298 if (debug)
0299 printk(KERN_CONT "\n");
0300
0301
0302 rc = i2c_master_send(c, cmd->bytes, cmd->count);
0303 if (rc != cmd->count) {
0304 v4l2_warn(sd, "I/O error (%s)\n", name);
0305 if (rc < 0)
0306 return rc;
0307 return -EIO;
0308 }
0309 return 0;
0310 }
0311
0312
0313
0314
0315
0316
0317
0318
0319 static void chip_thread_wake(struct timer_list *t)
0320 {
0321 struct CHIPSTATE *chip = from_timer(chip, t, wt);
0322 wake_up_process(chip->thread);
0323 }
0324
0325 static int chip_thread(void *data)
0326 {
0327 struct CHIPSTATE *chip = data;
0328 struct CHIPDESC *desc = chip->desc;
0329 struct v4l2_subdev *sd = &chip->sd;
0330 int mode, selected;
0331
0332 v4l2_dbg(1, debug, sd, "thread started\n");
0333 set_freezable();
0334 for (;;) {
0335 set_current_state(TASK_INTERRUPTIBLE);
0336 if (!kthread_should_stop())
0337 schedule();
0338 set_current_state(TASK_RUNNING);
0339 try_to_freeze();
0340 if (kthread_should_stop())
0341 break;
0342 v4l2_dbg(1, debug, sd, "thread wakeup\n");
0343
0344
0345 if (chip->radio)
0346 continue;
0347
0348
0349 mode = desc->getrxsubchans(chip);
0350 if (mode == chip->prevmode)
0351 continue;
0352
0353
0354 v4l2_dbg(1, debug, sd, "thread checkmode\n");
0355
0356 chip->prevmode = mode;
0357
0358 selected = V4L2_TUNER_MODE_MONO;
0359 switch (chip->audmode) {
0360 case V4L2_TUNER_MODE_MONO:
0361 if (mode & V4L2_TUNER_SUB_LANG1)
0362 selected = V4L2_TUNER_MODE_LANG1;
0363 break;
0364 case V4L2_TUNER_MODE_STEREO:
0365 case V4L2_TUNER_MODE_LANG1:
0366 if (mode & V4L2_TUNER_SUB_LANG1)
0367 selected = V4L2_TUNER_MODE_LANG1;
0368 else if (mode & V4L2_TUNER_SUB_STEREO)
0369 selected = V4L2_TUNER_MODE_STEREO;
0370 break;
0371 case V4L2_TUNER_MODE_LANG2:
0372 if (mode & V4L2_TUNER_SUB_LANG2)
0373 selected = V4L2_TUNER_MODE_LANG2;
0374 else if (mode & V4L2_TUNER_SUB_STEREO)
0375 selected = V4L2_TUNER_MODE_STEREO;
0376 break;
0377 case V4L2_TUNER_MODE_LANG1_LANG2:
0378 if (mode & V4L2_TUNER_SUB_LANG2)
0379 selected = V4L2_TUNER_MODE_LANG1_LANG2;
0380 else if (mode & V4L2_TUNER_SUB_STEREO)
0381 selected = V4L2_TUNER_MODE_STEREO;
0382 }
0383 desc->setaudmode(chip, selected);
0384
0385
0386 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
0387 }
0388
0389 v4l2_dbg(1, debug, sd, "thread exiting\n");
0390 return 0;
0391 }
0392
0393
0394
0395
0396 #define TDA9840_SW 0x00
0397 #define TDA9840_LVADJ 0x02
0398 #define TDA9840_STADJ 0x03
0399 #define TDA9840_TEST 0x04
0400
0401 #define TDA9840_MONO 0x10
0402 #define TDA9840_STEREO 0x2a
0403 #define TDA9840_DUALA 0x12
0404 #define TDA9840_DUALB 0x1e
0405 #define TDA9840_DUALAB 0x1a
0406 #define TDA9840_DUALBA 0x16
0407 #define TDA9840_EXTERNAL 0x7a
0408
0409 #define TDA9840_DS_DUAL 0x20
0410 #define TDA9840_ST_STEREO 0x40
0411 #define TDA9840_PONRES 0x80
0412
0413 #define TDA9840_TEST_INT1SN 0x1
0414 #define TDA9840_TEST_INTFU 0x02
0415
0416 static int tda9840_getrxsubchans(struct CHIPSTATE *chip)
0417 {
0418 struct v4l2_subdev *sd = &chip->sd;
0419 int val, mode;
0420
0421 mode = V4L2_TUNER_SUB_MONO;
0422
0423 val = chip_read(chip);
0424 if (val < 0)
0425 return mode;
0426
0427 if (val & TDA9840_DS_DUAL)
0428 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
0429 if (val & TDA9840_ST_STEREO)
0430 mode = V4L2_TUNER_SUB_STEREO;
0431
0432 v4l2_dbg(1, debug, sd,
0433 "tda9840_getrxsubchans(): raw chip read: %d, return: %d\n",
0434 val, mode);
0435 return mode;
0436 }
0437
0438 static void tda9840_setaudmode(struct CHIPSTATE *chip, int mode)
0439 {
0440 int update = 1;
0441 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
0442
0443 switch (mode) {
0444 case V4L2_TUNER_MODE_MONO:
0445 t |= TDA9840_MONO;
0446 break;
0447 case V4L2_TUNER_MODE_STEREO:
0448 t |= TDA9840_STEREO;
0449 break;
0450 case V4L2_TUNER_MODE_LANG1:
0451 t |= TDA9840_DUALA;
0452 break;
0453 case V4L2_TUNER_MODE_LANG2:
0454 t |= TDA9840_DUALB;
0455 break;
0456 case V4L2_TUNER_MODE_LANG1_LANG2:
0457 t |= TDA9840_DUALAB;
0458 break;
0459 default:
0460 update = 0;
0461 }
0462
0463 if (update)
0464 chip_write(chip, TDA9840_SW, t);
0465 }
0466
0467 static int tda9840_checkit(struct CHIPSTATE *chip)
0468 {
0469 int rc;
0470
0471 rc = chip_read(chip);
0472 if (rc < 0)
0473 return 0;
0474
0475
0476
0477 return ((rc & 0x1f) == 0) ? 1 : 0;
0478 }
0479
0480
0481
0482
0483
0484 #define TDA9855_VR 0x00
0485 #define TDA9855_VL 0x01
0486 #define TDA9855_BA 0x02
0487 #define TDA9855_TR 0x03
0488 #define TDA9855_SW 0x04
0489
0490
0491 #define TDA9850_C4 0x04
0492
0493
0494 #define TDA985x_C5 0x05
0495 #define TDA985x_C6 0x06
0496 #define TDA985x_C7 0x07
0497 #define TDA985x_A1 0x08
0498 #define TDA985x_A2 0x09
0499 #define TDA985x_A3 0x0a
0500
0501
0502
0503
0504
0505
0506
0507
0508
0509
0510
0511
0512
0513
0514
0515
0516
0517
0518
0519
0520
0521
0522
0523
0524
0525
0526
0527
0528
0529
0530 #define TDA9855_MUTE 1<<7
0531 #define TDA9855_AVL 1<<6
0532 #define TDA9855_LOUD 1<<5
0533 #define TDA9855_SUR 1<<3
0534
0535
0536
0537 #define TDA9855_EXT 1<<2
0538 #define TDA9855_INT 0
0539
0540
0541
0542
0543
0544
0545
0546
0547 #define TDA985x_SAP 3<<6
0548 #define TDA985x_MONOSAP 2<<6
0549 #define TDA985x_STEREO 1<<6
0550 #define TDA985x_MONO 0
0551 #define TDA985x_LMU 1<<3
0552
0553
0554 #define TDA9855_TZCM 1<<5
0555 #define TDA9855_VZCM 1<<4
0556 #define TDA9855_LINEAR 0
0557 #define TDA9855_PSEUDO 1
0558 #define TDA9855_SPAT_30 2
0559 #define TDA9855_SPAT_50 3
0560 #define TDA9855_E_MONO 7
0561
0562
0563
0564
0565
0566
0567
0568
0569
0570
0571 #define TDA985x_STP 1<<5
0572 #define TDA985x_SAPP 1<<6
0573 #define TDA985x_STS 1<<7
0574
0575
0576
0577
0578
0579 #define TDA985x_ADJ 1<<7
0580
0581 static int tda9855_volume(int val) { return val/0x2e8+0x27; }
0582 static int tda9855_bass(int val) { return val/0xccc+0x06; }
0583 static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
0584
0585 static int tda985x_getrxsubchans(struct CHIPSTATE *chip)
0586 {
0587 int mode, val;
0588
0589
0590
0591 mode = V4L2_TUNER_SUB_MONO;
0592 val = chip_read(chip);
0593 if (val < 0)
0594 return mode;
0595
0596 if (val & TDA985x_STP)
0597 mode = V4L2_TUNER_SUB_STEREO;
0598 if (val & TDA985x_SAPP)
0599 mode |= V4L2_TUNER_SUB_SAP;
0600 return mode;
0601 }
0602
0603 static void tda985x_setaudmode(struct CHIPSTATE *chip, int mode)
0604 {
0605 int update = 1;
0606 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
0607
0608 switch (mode) {
0609 case V4L2_TUNER_MODE_MONO:
0610 c6 |= TDA985x_MONO;
0611 break;
0612 case V4L2_TUNER_MODE_STEREO:
0613 case V4L2_TUNER_MODE_LANG1:
0614 c6 |= TDA985x_STEREO;
0615 break;
0616 case V4L2_TUNER_MODE_SAP:
0617 c6 |= TDA985x_SAP;
0618 break;
0619 case V4L2_TUNER_MODE_LANG1_LANG2:
0620 c6 |= TDA985x_MONOSAP;
0621 break;
0622 default:
0623 update = 0;
0624 }
0625 if (update)
0626 chip_write(chip,TDA985x_C6,c6);
0627 }
0628
0629
0630
0631
0632
0633
0634
0635 #define TDA9873_SW 0x00
0636 #define TDA9873_AD 0x01
0637 #define TDA9873_PT 0x02
0638
0639
0640
0641
0642
0643
0644
0645
0646
0647 #define TDA9873_INP_MASK 3
0648 #define TDA9873_INTERNAL 0
0649 #define TDA9873_EXT_STEREO 2
0650 #define TDA9873_EXT_MONO 1
0651
0652
0653
0654
0655
0656
0657
0658
0659
0660
0661
0662
0663 #define TDA9873_TR_MASK (7 << 2)
0664 #define TDA9873_TR_MONO 4
0665 #define TDA9873_TR_STEREO 1 << 4
0666 #define TDA9873_TR_REVERSE ((1 << 3) | (1 << 2))
0667 #define TDA9873_TR_DUALA 1 << 2
0668 #define TDA9873_TR_DUALB 1 << 3
0669 #define TDA9873_TR_DUALAB 0
0670
0671
0672
0673
0674
0675
0676
0677 #define TDA9873_GAIN_NORMAL 1 << 5
0678 #define TDA9873_MUTE 1 << 6
0679 #define TDA9873_AUTOMUTE 1 << 7
0680
0681
0682
0683
0684
0685
0686
0687 #define TDA9873_STEREO_ADJ 0x06
0688
0689
0690
0691
0692
0693
0694
0695
0696
0697
0698 #define TDA9873_BG 0
0699 #define TDA9873_M 1
0700 #define TDA9873_DK1 2
0701 #define TDA9873_DK2 3
0702 #define TDA9873_DK3 4
0703 #define TDA9873_I 5
0704
0705
0706
0707 #define TDA9873_IDR_NORM 0
0708 #define TDA9873_IDR_FAST 1 << 7
0709
0710
0711
0712
0713
0714
0715
0716
0717
0718
0719
0720 #define TDA9873_PORTS 3
0721
0722
0723 #define TDA9873_TST_PORT 1 << 2
0724
0725
0726
0727
0728
0729
0730
0731
0732 #define TDA9873_MOUT_MONO 0
0733 #define TDA9873_MOUT_FMONO 0
0734 #define TDA9873_MOUT_DUALA 0
0735 #define TDA9873_MOUT_DUALB 1 << 3
0736 #define TDA9873_MOUT_ST 1 << 4
0737 #define TDA9873_MOUT_EXTM ((1 << 4) | (1 << 3))
0738 #define TDA9873_MOUT_EXTL 1 << 5
0739 #define TDA9873_MOUT_EXTR ((1 << 5) | (1 << 3))
0740 #define TDA9873_MOUT_EXTLR ((1 << 5) | (1 << 4))
0741 #define TDA9873_MOUT_MUTE ((1 << 5) | (1 << 4) | (1 << 3))
0742
0743
0744 #define TDA9873_PONR 0
0745 #define TDA9873_STEREO 2
0746 #define TDA9873_DUAL 4
0747
0748 static int tda9873_getrxsubchans(struct CHIPSTATE *chip)
0749 {
0750 struct v4l2_subdev *sd = &chip->sd;
0751 int val,mode;
0752
0753 mode = V4L2_TUNER_SUB_MONO;
0754
0755 val = chip_read(chip);
0756 if (val < 0)
0757 return mode;
0758
0759 if (val & TDA9873_STEREO)
0760 mode = V4L2_TUNER_SUB_STEREO;
0761 if (val & TDA9873_DUAL)
0762 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
0763 v4l2_dbg(1, debug, sd,
0764 "tda9873_getrxsubchans(): raw chip read: %d, return: %d\n",
0765 val, mode);
0766 return mode;
0767 }
0768
0769 static void tda9873_setaudmode(struct CHIPSTATE *chip, int mode)
0770 {
0771 struct v4l2_subdev *sd = &chip->sd;
0772 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
0773
0774
0775 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
0776 v4l2_dbg(1, debug, sd,
0777 "tda9873_setaudmode(): external input\n");
0778 return;
0779 }
0780
0781 v4l2_dbg(1, debug, sd,
0782 "tda9873_setaudmode(): chip->shadow.bytes[%d] = %d\n",
0783 TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
0784 v4l2_dbg(1, debug, sd, "tda9873_setaudmode(): sw_data = %d\n",
0785 sw_data);
0786
0787 switch (mode) {
0788 case V4L2_TUNER_MODE_MONO:
0789 sw_data |= TDA9873_TR_MONO;
0790 break;
0791 case V4L2_TUNER_MODE_STEREO:
0792 sw_data |= TDA9873_TR_STEREO;
0793 break;
0794 case V4L2_TUNER_MODE_LANG1:
0795 sw_data |= TDA9873_TR_DUALA;
0796 break;
0797 case V4L2_TUNER_MODE_LANG2:
0798 sw_data |= TDA9873_TR_DUALB;
0799 break;
0800 case V4L2_TUNER_MODE_LANG1_LANG2:
0801 sw_data |= TDA9873_TR_DUALAB;
0802 break;
0803 default:
0804 return;
0805 }
0806
0807 chip_write(chip, TDA9873_SW, sw_data);
0808 v4l2_dbg(1, debug, sd,
0809 "tda9873_setaudmode(): req. mode %d; chip_write: %d\n",
0810 mode, sw_data);
0811 }
0812
0813 static int tda9873_checkit(struct CHIPSTATE *chip)
0814 {
0815 int rc;
0816
0817 rc = chip_read2(chip, 254);
0818 if (rc < 0)
0819 return 0;
0820 return (rc & ~0x1f) == 0x80;
0821 }
0822
0823
0824
0825
0826
0827
0828
0829 #define TDA9874A_AGCGR 0x00
0830 #define TDA9874A_GCONR 0x01
0831 #define TDA9874A_MSR 0x02
0832 #define TDA9874A_C1FRA 0x03
0833 #define TDA9874A_C1FRB 0x04
0834 #define TDA9874A_C1FRC 0x05
0835 #define TDA9874A_C2FRA 0x06
0836 #define TDA9874A_C2FRB 0x07
0837 #define TDA9874A_C2FRC 0x08
0838 #define TDA9874A_DCR 0x09
0839 #define TDA9874A_FMER 0x0a
0840 #define TDA9874A_FMMR 0x0b
0841 #define TDA9874A_C1OLAR 0x0c
0842 #define TDA9874A_C2OLAR 0x0d
0843 #define TDA9874A_NCONR 0x0e
0844 #define TDA9874A_NOLAR 0x0f
0845 #define TDA9874A_NLELR 0x10
0846 #define TDA9874A_NUELR 0x11
0847 #define TDA9874A_AMCONR 0x12
0848 #define TDA9874A_SDACOSR 0x13
0849 #define TDA9874A_AOSR 0x14
0850 #define TDA9874A_DAICONR 0x15
0851 #define TDA9874A_I2SOSR 0x16
0852 #define TDA9874A_I2SOLAR 0x17
0853 #define TDA9874A_MDACOSR 0x18
0854 #define TDA9874A_ESP 0xFF
0855
0856
0857 #define TDA9874A_DSR 0x00
0858 #define TDA9874A_NSR 0x01
0859 #define TDA9874A_NECR 0x02
0860 #define TDA9874A_DR1 0x03
0861 #define TDA9874A_DR2 0x04
0862 #define TDA9874A_LLRA 0x05
0863 #define TDA9874A_LLRB 0x06
0864 #define TDA9874A_SIFLR 0x07
0865 #define TDA9874A_TR2 252
0866 #define TDA9874A_TR1 253
0867 #define TDA9874A_DIC 254
0868 #define TDA9874A_SIC 255
0869
0870
0871 static int tda9874a_mode = 1;
0872 static int tda9874a_GCONR = 0xc0;
0873 static int tda9874a_NCONR = 0x01;
0874 static int tda9874a_ESP = 0x07;
0875 static int tda9874a_dic = -1;
0876
0877
0878 static unsigned int tda9874a_SIF = UNSET;
0879 static unsigned int tda9874a_AMSEL = UNSET;
0880 static unsigned int tda9874a_STD = UNSET;
0881 module_param(tda9874a_SIF, int, 0444);
0882 module_param(tda9874a_AMSEL, int, 0444);
0883 module_param(tda9874a_STD, int, 0444);
0884
0885
0886
0887
0888
0889
0890
0891
0892
0893 static struct tda9874a_MODES {
0894 char *name;
0895 audiocmd cmd;
0896 } tda9874a_modelist[9] = {
0897 { "A2, B/G",
0898 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
0899 { "A2, M (Korea)",
0900 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
0901 { "A2, D/K (1)",
0902 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
0903 { "A2, D/K (2)",
0904 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
0905 { "A2, D/K (3)",
0906 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
0907 { "NICAM, I",
0908 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
0909 { "NICAM, B/G",
0910 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
0911 { "NICAM, D/K",
0912 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
0913 { "NICAM, L",
0914 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
0915 };
0916
0917 static int tda9874a_setup(struct CHIPSTATE *chip)
0918 {
0919 struct v4l2_subdev *sd = &chip->sd;
0920
0921 chip_write(chip, TDA9874A_AGCGR, 0x00);
0922 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
0923 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
0924 if(tda9874a_dic == 0x11) {
0925 chip_write(chip, TDA9874A_FMMR, 0x80);
0926 } else {
0927 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
0928 chip_write(chip, TDA9874A_FMMR, 0x00);
0929 }
0930 chip_write(chip, TDA9874A_C1OLAR, 0x00);
0931 chip_write(chip, TDA9874A_C2OLAR, 0x00);
0932 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
0933 chip_write(chip, TDA9874A_NOLAR, 0x00);
0934
0935
0936
0937 chip_write(chip, TDA9874A_NLELR, 0x14);
0938 chip_write(chip, TDA9874A_NUELR, 0x50);
0939
0940 if(tda9874a_dic == 0x11) {
0941 chip_write(chip, TDA9874A_AMCONR, 0xf9);
0942 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
0943 chip_write(chip, TDA9874A_AOSR, 0x80);
0944 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
0945 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
0946 } else {
0947 chip_write(chip, TDA9874A_AMCONR, 0xfb);
0948 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
0949 chip_write(chip, TDA9874A_AOSR, 0x00);
0950 }
0951 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
0952 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
0953 return 1;
0954 }
0955
0956 static int tda9874a_getrxsubchans(struct CHIPSTATE *chip)
0957 {
0958 struct v4l2_subdev *sd = &chip->sd;
0959 int dsr,nsr,mode;
0960 int necr;
0961
0962 mode = V4L2_TUNER_SUB_MONO;
0963
0964 dsr = chip_read2(chip, TDA9874A_DSR);
0965 if (dsr < 0)
0966 return mode;
0967 nsr = chip_read2(chip, TDA9874A_NSR);
0968 if (nsr < 0)
0969 return mode;
0970 necr = chip_read2(chip, TDA9874A_NECR);
0971 if (necr < 0)
0972 return mode;
0973
0974
0975 chip->shadow.bytes[MAXREGS-2] = dsr;
0976 chip->shadow.bytes[MAXREGS-1] = nsr;
0977
0978 if(tda9874a_mode) {
0979
0980
0981
0982
0983
0984
0985
0986
0987 if(nsr & 0x02)
0988 mode = V4L2_TUNER_SUB_STEREO;
0989 if(nsr & 0x01)
0990 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
0991 } else {
0992 if(dsr & 0x02)
0993 mode = V4L2_TUNER_SUB_STEREO;
0994 if(dsr & 0x04)
0995 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
0996 }
0997
0998 v4l2_dbg(1, debug, sd,
0999 "tda9874a_getrxsubchans(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1000 dsr, nsr, necr, mode);
1001 return mode;
1002 }
1003
1004 static void tda9874a_setaudmode(struct CHIPSTATE *chip, int mode)
1005 {
1006 struct v4l2_subdev *sd = &chip->sd;
1007
1008
1009
1010 if (tda9874a_mode) {
1011 if(chip->shadow.bytes[MAXREGS-2] & 0x20)
1012 tda9874a_NCONR &= 0xfe;
1013 else
1014 tda9874a_NCONR |= 0x01;
1015 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
1016 }
1017
1018
1019
1020
1021
1022
1023
1024 if(tda9874a_dic == 0x11) {
1025 int aosr = 0x80;
1026 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
1027
1028 switch(mode) {
1029 case V4L2_TUNER_MODE_MONO:
1030 case V4L2_TUNER_MODE_STEREO:
1031 break;
1032 case V4L2_TUNER_MODE_LANG1:
1033 aosr = 0x80;
1034 mdacosr = (tda9874a_mode) ? 0x82:0x80;
1035 break;
1036 case V4L2_TUNER_MODE_LANG2:
1037 aosr = 0xa0;
1038 mdacosr = (tda9874a_mode) ? 0x83:0x81;
1039 break;
1040 case V4L2_TUNER_MODE_LANG1_LANG2:
1041 aosr = 0x00;
1042 mdacosr = (tda9874a_mode) ? 0x82:0x80;
1043 break;
1044 default:
1045 return;
1046 }
1047 chip_write(chip, TDA9874A_AOSR, aosr);
1048 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
1049
1050 v4l2_dbg(1, debug, sd,
1051 "tda9874a_setaudmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1052 mode, aosr, mdacosr);
1053
1054 } else {
1055 int fmmr,aosr;
1056
1057 switch(mode) {
1058 case V4L2_TUNER_MODE_MONO:
1059 fmmr = 0x00;
1060 aosr = 0x10;
1061 break;
1062 case V4L2_TUNER_MODE_STEREO:
1063 if(tda9874a_mode) {
1064 fmmr = 0x00;
1065 aosr = 0x00;
1066 } else {
1067 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04;
1068 aosr = 0x00;
1069 }
1070 break;
1071 case V4L2_TUNER_MODE_LANG1:
1072 fmmr = 0x02;
1073 aosr = 0x10;
1074 break;
1075 case V4L2_TUNER_MODE_LANG2:
1076 fmmr = 0x02;
1077 aosr = 0x20;
1078 break;
1079 case V4L2_TUNER_MODE_LANG1_LANG2:
1080 fmmr = 0x02;
1081 aosr = 0x00;
1082 break;
1083 default:
1084 return;
1085 }
1086 chip_write(chip, TDA9874A_FMMR, fmmr);
1087 chip_write(chip, TDA9874A_AOSR, aosr);
1088
1089 v4l2_dbg(1, debug, sd,
1090 "tda9874a_setaudmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1091 mode, fmmr, aosr);
1092 }
1093 }
1094
1095 static int tda9874a_checkit(struct CHIPSTATE *chip)
1096 {
1097 struct v4l2_subdev *sd = &chip->sd;
1098 int dic,sic;
1099
1100 dic = chip_read2(chip, TDA9874A_DIC);
1101 if (dic < 0)
1102 return 0;
1103 sic = chip_read2(chip, TDA9874A_SIC);
1104 if (sic < 0)
1105 return 0;
1106
1107 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1108
1109 if((dic == 0x11)||(dic == 0x07)) {
1110 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1111 tda9874a_dic = dic;
1112 return 1;
1113 }
1114 return 0;
1115 }
1116
1117 static int tda9874a_initialize(struct CHIPSTATE *chip)
1118 {
1119 if (tda9874a_SIF > 2)
1120 tda9874a_SIF = 1;
1121 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1122 tda9874a_STD = 0;
1123 if(tda9874a_AMSEL > 1)
1124 tda9874a_AMSEL = 0;
1125
1126 if(tda9874a_SIF == 1)
1127 tda9874a_GCONR = 0xc0;
1128 else
1129 tda9874a_GCONR = 0xc1;
1130
1131 tda9874a_ESP = tda9874a_STD;
1132 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1133
1134 if(tda9874a_AMSEL == 0)
1135 tda9874a_NCONR = 0x01;
1136 else
1137 tda9874a_NCONR = 0x05;
1138
1139 tda9874a_setup(chip);
1140 return 0;
1141 }
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152 #define TDA9875_MUT 0x12
1153 #define TDA9875_CFG 0x01
1154 #define TDA9875_DACOS 0x13
1155 #define TDA9875_LOSR 0x16
1156
1157 #define TDA9875_CH1V 0x0c
1158 #define TDA9875_CH2V 0x0d
1159 #define TDA9875_SC1 0x14
1160 #define TDA9875_SC2 0x15
1161
1162 #define TDA9875_ADCIS 0x17
1163 #define TDA9875_AER 0x19
1164 #define TDA9875_MCS 0x18
1165 #define TDA9875_MVL 0x1a
1166 #define TDA9875_MVR 0x1b
1167 #define TDA9875_MBA 0x1d
1168 #define TDA9875_MTR 0x1e
1169 #define TDA9875_ACS 0x1f
1170 #define TDA9875_AVL 0x20
1171 #define TDA9875_AVR 0x21
1172 #define TDA9875_ABA 0x22
1173 #define TDA9875_ATR 0x23
1174
1175 #define TDA9875_MSR 0x02
1176 #define TDA9875_C1MSB 0x03
1177 #define TDA9875_C1MIB 0x04
1178 #define TDA9875_C1LSB 0x05
1179 #define TDA9875_C2MSB 0x06
1180 #define TDA9875_C2MIB 0x07
1181 #define TDA9875_C2LSB 0x08
1182 #define TDA9875_DCR 0x09
1183 #define TDA9875_DEEM 0x0a
1184 #define TDA9875_FMAT 0x0b
1185
1186
1187 #define TDA9875_MUTE_ON 0xff
1188 #define TDA9875_MUTE_OFF 0xcc
1189
1190 static int tda9875_initialize(struct CHIPSTATE *chip)
1191 {
1192 chip_write(chip, TDA9875_CFG, 0xd0);
1193 chip_write(chip, TDA9875_MSR, 0x03);
1194 chip_write(chip, TDA9875_C1MSB, 0x00);
1195 chip_write(chip, TDA9875_C1MIB, 0x00);
1196 chip_write(chip, TDA9875_C1LSB, 0x00);
1197 chip_write(chip, TDA9875_C2MSB, 0x00);
1198 chip_write(chip, TDA9875_C2MIB, 0x00);
1199 chip_write(chip, TDA9875_C2LSB, 0x00);
1200 chip_write(chip, TDA9875_DCR, 0x00);
1201 chip_write(chip, TDA9875_DEEM, 0x44);
1202 chip_write(chip, TDA9875_FMAT, 0x00);
1203 chip_write(chip, TDA9875_SC1, 0x00);
1204 chip_write(chip, TDA9875_SC2, 0x01);
1205
1206 chip_write(chip, TDA9875_CH1V, 0x10);
1207 chip_write(chip, TDA9875_CH2V, 0x10);
1208 chip_write(chip, TDA9875_DACOS, 0x02);
1209 chip_write(chip, TDA9875_ADCIS, 0x6f);
1210 chip_write(chip, TDA9875_LOSR, 0x00);
1211 chip_write(chip, TDA9875_AER, 0x00);
1212 chip_write(chip, TDA9875_MCS, 0x44);
1213 chip_write(chip, TDA9875_MVL, 0x03);
1214 chip_write(chip, TDA9875_MVR, 0x03);
1215 chip_write(chip, TDA9875_MBA, 0x00);
1216 chip_write(chip, TDA9875_MTR, 0x00);
1217 chip_write(chip, TDA9875_ACS, 0x44);
1218 chip_write(chip, TDA9875_AVL, 0x00);
1219 chip_write(chip, TDA9875_AVR, 0x00);
1220 chip_write(chip, TDA9875_ABA, 0x00);
1221 chip_write(chip, TDA9875_ATR, 0x00);
1222
1223 chip_write(chip, TDA9875_MUT, 0xcc);
1224 return 0;
1225 }
1226
1227 static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1228 static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1229 static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1230
1231
1232
1233
1234
1235
1236
1237
1238 static int tda9875_checkit(struct CHIPSTATE *chip)
1239 {
1240 struct v4l2_subdev *sd = &chip->sd;
1241 int dic, rev;
1242
1243 dic = chip_read2(chip, 254);
1244 if (dic < 0)
1245 return 0;
1246 rev = chip_read2(chip, 255);
1247 if (rev < 0)
1248 return 0;
1249
1250 if (dic == 0 || dic == 2) {
1251 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1252 dic == 0 ? "" : "A", rev);
1253 return 1;
1254 }
1255 return 0;
1256 }
1257
1258
1259
1260
1261 #define TEA6300_VL 0x00
1262 #define TEA6300_VR 0x01
1263 #define TEA6300_BA 0x02
1264 #define TEA6300_TR 0x03
1265 #define TEA6300_FA 0x04
1266 #define TEA6300_S 0x05
1267
1268 #define TEA6300_S_SA 0x01
1269 #define TEA6300_S_SB 0x02
1270 #define TEA6300_S_SC 0x04
1271 #define TEA6300_S_GMU 0x80
1272
1273 #define TEA6320_V 0x00
1274 #define TEA6320_FFR 0x01
1275 #define TEA6320_FFL 0x02
1276 #define TEA6320_FRR 0x03
1277 #define TEA6320_FRL 0x04
1278 #define TEA6320_BA 0x05
1279 #define TEA6320_TR 0x06
1280 #define TEA6320_S 0x07
1281
1282 #define TEA6320_S_SA 0x07
1283 #define TEA6320_S_SB 0x06
1284 #define TEA6320_S_SC 0x05
1285 #define TEA6320_S_SD 0x04
1286 #define TEA6320_S_GMU 0x80
1287
1288 #define TEA6420_S_SA 0x00
1289 #define TEA6420_S_SB 0x01
1290 #define TEA6420_S_SC 0x02
1291 #define TEA6420_S_SD 0x03
1292 #define TEA6420_S_SE 0x04
1293 #define TEA6420_S_GMU 0x05
1294
1295 static int tea6300_shift10(int val) { return val >> 10; }
1296 static int tea6300_shift12(int val) { return val >> 12; }
1297
1298
1299
1300 static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1301 static int tea6320_shift11(int val) { return val >> 11; }
1302 static int tea6320_initialize(struct CHIPSTATE * chip)
1303 {
1304 chip_write(chip, TEA6320_FFR, 0x3f);
1305 chip_write(chip, TEA6320_FFL, 0x3f);
1306 chip_write(chip, TEA6320_FRR, 0x3f);
1307 chip_write(chip, TEA6320_FRL, 0x3f);
1308
1309 return 0;
1310 }
1311
1312
1313
1314
1315
1316 #define TDA8425_VL 0x00
1317 #define TDA8425_VR 0x01
1318 #define TDA8425_BA 0x02
1319 #define TDA8425_TR 0x03
1320 #define TDA8425_S1 0x08
1321
1322 #define TDA8425_S1_OFF 0xEE
1323 #define TDA8425_S1_CH1 0xCE
1324 #define TDA8425_S1_CH2 0xCF
1325 #define TDA8425_S1_MU 0x20
1326 #define TDA8425_S1_STEREO 0x18
1327 #define TDA8425_S1_STEREO_SPATIAL 0x18
1328 #define TDA8425_S1_STEREO_LINEAR 0x08
1329 #define TDA8425_S1_STEREO_PSEUDO 0x10
1330 #define TDA8425_S1_STEREO_MONO 0x00
1331 #define TDA8425_S1_ML 0x06
1332 #define TDA8425_S1_ML_SOUND_A 0x02
1333 #define TDA8425_S1_ML_SOUND_B 0x04
1334 #define TDA8425_S1_ML_STEREO 0x06
1335 #define TDA8425_S1_IS 0x01
1336
1337
1338 static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1339 static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1340
1341 static void tda8425_setaudmode(struct CHIPSTATE *chip, int mode)
1342 {
1343 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1344
1345 switch (mode) {
1346 case V4L2_TUNER_MODE_LANG1:
1347 s1 |= TDA8425_S1_ML_SOUND_A;
1348 s1 |= TDA8425_S1_STEREO_PSEUDO;
1349 break;
1350 case V4L2_TUNER_MODE_LANG2:
1351 s1 |= TDA8425_S1_ML_SOUND_B;
1352 s1 |= TDA8425_S1_STEREO_PSEUDO;
1353 break;
1354 case V4L2_TUNER_MODE_LANG1_LANG2:
1355 s1 |= TDA8425_S1_ML_STEREO;
1356 s1 |= TDA8425_S1_STEREO_LINEAR;
1357 break;
1358 case V4L2_TUNER_MODE_MONO:
1359 s1 |= TDA8425_S1_ML_STEREO;
1360 s1 |= TDA8425_S1_STEREO_MONO;
1361 break;
1362 case V4L2_TUNER_MODE_STEREO:
1363 s1 |= TDA8425_S1_ML_STEREO;
1364 s1 |= TDA8425_S1_STEREO_SPATIAL;
1365 break;
1366 default:
1367 return;
1368 }
1369 chip_write(chip,TDA8425_S1,s1);
1370 }
1371
1372
1373
1374
1375
1376
1377 #define PIC16C54_REG_KEY_CODE 0x01
1378 #define PIC16C54_REG_MISC 0x02
1379
1380
1381 #define PIC16C54_MISC_RESET_REMOTE_CTL 0x01
1382
1383 #define PIC16C54_MISC_MTS_MAIN 0x02
1384 #define PIC16C54_MISC_MTS_SAP 0x04
1385 #define PIC16C54_MISC_MTS_BOTH 0x08
1386 #define PIC16C54_MISC_SND_MUTE 0x10
1387 #define PIC16C54_MISC_SND_NOTMUTE 0x20
1388 #define PIC16C54_MISC_SWITCH_TUNER 0x40
1389 #define PIC16C54_MISC_SWITCH_LINE 0x80
1390
1391
1392
1393
1394
1395 #define TA8874Z_LED_STE 0x80
1396 #define TA8874Z_LED_BIL 0x40
1397 #define TA8874Z_LED_EXT 0x20
1398 #define TA8874Z_MONO_SET 0x10
1399 #define TA8874Z_MUTE 0x08
1400 #define TA8874Z_F_MONO 0x04
1401 #define TA8874Z_MODE_SUB 0x02
1402 #define TA8874Z_MODE_MAIN 0x01
1403
1404
1405
1406 #define TA8874Z_SEPARATION 0x3f
1407 #define TA8874Z_SEPARATION_DEFAULT 0x10
1408
1409
1410 #define TA8874Z_B1 0x80
1411 #define TA8874Z_B0 0x40
1412 #define TA8874Z_CHAG_FLAG 0x20
1413
1414
1415
1416
1417
1418
1419
1420 static int ta8874z_getrxsubchans(struct CHIPSTATE *chip)
1421 {
1422 int val, mode;
1423
1424 mode = V4L2_TUNER_SUB_MONO;
1425
1426 val = chip_read(chip);
1427 if (val < 0)
1428 return mode;
1429
1430 if (val & TA8874Z_B1){
1431 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1432 }else if (!(val & TA8874Z_B0)){
1433 mode = V4L2_TUNER_SUB_STEREO;
1434 }
1435
1436
1437
1438 return mode;
1439 }
1440
1441 static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1442 static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1443 static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1444 static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1445 static audiocmd ta8874z_both = {2, { TA8874Z_MODE_MAIN | TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1446
1447 static void ta8874z_setaudmode(struct CHIPSTATE *chip, int mode)
1448 {
1449 struct v4l2_subdev *sd = &chip->sd;
1450 int update = 1;
1451 audiocmd *t = NULL;
1452
1453 v4l2_dbg(1, debug, sd, "ta8874z_setaudmode(): mode: 0x%02x\n", mode);
1454
1455 switch(mode){
1456 case V4L2_TUNER_MODE_MONO:
1457 t = &ta8874z_mono;
1458 break;
1459 case V4L2_TUNER_MODE_STEREO:
1460 t = &ta8874z_stereo;
1461 break;
1462 case V4L2_TUNER_MODE_LANG1:
1463 t = &ta8874z_main;
1464 break;
1465 case V4L2_TUNER_MODE_LANG2:
1466 t = &ta8874z_sub;
1467 break;
1468 case V4L2_TUNER_MODE_LANG1_LANG2:
1469 t = &ta8874z_both;
1470 break;
1471 default:
1472 update = 0;
1473 }
1474
1475 if(update)
1476 chip_cmd(chip, "TA8874Z", t);
1477 }
1478
1479 static int ta8874z_checkit(struct CHIPSTATE *chip)
1480 {
1481 int rc;
1482
1483 rc = chip_read(chip);
1484 if (rc < 0)
1485 return rc;
1486
1487 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1488 }
1489
1490
1491
1492
1493
1494 static int tda8425 = 1;
1495 static int tda9840 = 1;
1496 static int tda9850 = 1;
1497 static int tda9855 = 1;
1498 static int tda9873 = 1;
1499 static int tda9874a = 1;
1500 static int tda9875 = 1;
1501 static int tea6300;
1502 static int tea6320;
1503 static int tea6420 = 1;
1504 static int pic16c54 = 1;
1505 static int ta8874z;
1506
1507 module_param(tda8425, int, 0444);
1508 module_param(tda9840, int, 0444);
1509 module_param(tda9850, int, 0444);
1510 module_param(tda9855, int, 0444);
1511 module_param(tda9873, int, 0444);
1512 module_param(tda9874a, int, 0444);
1513 module_param(tda9875, int, 0444);
1514 module_param(tea6300, int, 0444);
1515 module_param(tea6320, int, 0444);
1516 module_param(tea6420, int, 0444);
1517 module_param(pic16c54, int, 0444);
1518 module_param(ta8874z, int, 0444);
1519
1520 static struct CHIPDESC chiplist[] = {
1521 {
1522 .name = "tda9840",
1523 .insmodopt = &tda9840,
1524 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1525 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1526 .registers = 5,
1527 .flags = CHIP_NEED_CHECKMODE,
1528
1529
1530 .checkit = tda9840_checkit,
1531 .getrxsubchans = tda9840_getrxsubchans,
1532 .setaudmode = tda9840_setaudmode,
1533
1534 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1535 } }
1536 },
1537 {
1538 .name = "tda9873h",
1539 .insmodopt = &tda9873,
1540 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1541 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1542 .registers = 3,
1543 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1544
1545
1546 .checkit = tda9873_checkit,
1547 .getrxsubchans = tda9873_getrxsubchans,
1548 .setaudmode = tda9873_setaudmode,
1549
1550 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1551 .inputreg = TDA9873_SW,
1552 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
1553 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1554 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1555
1556 },
1557 {
1558 .name = "tda9874h/a",
1559 .insmodopt = &tda9874a,
1560 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1561 .addr_hi = I2C_ADDR_TDA9874 >> 1,
1562 .flags = CHIP_NEED_CHECKMODE,
1563
1564
1565 .initialize = tda9874a_initialize,
1566 .checkit = tda9874a_checkit,
1567 .getrxsubchans = tda9874a_getrxsubchans,
1568 .setaudmode = tda9874a_setaudmode,
1569 },
1570 {
1571 .name = "tda9875",
1572 .insmodopt = &tda9875,
1573 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1574 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1575 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1576
1577
1578 .initialize = tda9875_initialize,
1579 .checkit = tda9875_checkit,
1580 .volfunc = tda9875_volume,
1581 .bassfunc = tda9875_bass,
1582 .treblefunc = tda9875_treble,
1583 .leftreg = TDA9875_MVL,
1584 .rightreg = TDA9875_MVR,
1585 .bassreg = TDA9875_MBA,
1586 .treblereg = TDA9875_MTR,
1587 .volinit = 58880,
1588 },
1589 {
1590 .name = "tda9850",
1591 .insmodopt = &tda9850,
1592 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1593 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1594 .registers = 11,
1595
1596 .getrxsubchans = tda985x_getrxsubchans,
1597 .setaudmode = tda985x_setaudmode,
1598
1599 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1600 },
1601 {
1602 .name = "tda9855",
1603 .insmodopt = &tda9855,
1604 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1605 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1606 .registers = 11,
1607 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1608
1609 .leftreg = TDA9855_VL,
1610 .rightreg = TDA9855_VR,
1611 .bassreg = TDA9855_BA,
1612 .treblereg = TDA9855_TR,
1613
1614
1615 .volfunc = tda9855_volume,
1616 .bassfunc = tda9855_bass,
1617 .treblefunc = tda9855_treble,
1618 .getrxsubchans = tda985x_getrxsubchans,
1619 .setaudmode = tda985x_setaudmode,
1620
1621 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1622 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1623 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1624 0x07, 0x10, 0x10, 0x03 }}
1625 },
1626 {
1627 .name = "tea6300",
1628 .insmodopt = &tea6300,
1629 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1630 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1631 .registers = 6,
1632 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1633
1634 .leftreg = TEA6300_VR,
1635 .rightreg = TEA6300_VL,
1636 .bassreg = TEA6300_BA,
1637 .treblereg = TEA6300_TR,
1638
1639
1640 .volfunc = tea6300_shift10,
1641 .bassfunc = tea6300_shift12,
1642 .treblefunc = tea6300_shift12,
1643
1644 .inputreg = TEA6300_S,
1645 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1646 .inputmute = TEA6300_S_GMU,
1647 },
1648 {
1649 .name = "tea6320",
1650 .insmodopt = &tea6320,
1651 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1652 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1653 .registers = 8,
1654 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1655
1656 .leftreg = TEA6320_V,
1657 .rightreg = TEA6320_V,
1658 .bassreg = TEA6320_BA,
1659 .treblereg = TEA6320_TR,
1660
1661
1662 .initialize = tea6320_initialize,
1663 .volfunc = tea6320_volume,
1664 .bassfunc = tea6320_shift11,
1665 .treblefunc = tea6320_shift11,
1666
1667 .inputreg = TEA6320_S,
1668 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1669 .inputmute = TEA6300_S_GMU,
1670 },
1671 {
1672 .name = "tea6420",
1673 .insmodopt = &tea6420,
1674 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1675 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1676 .registers = 1,
1677 .flags = CHIP_HAS_INPUTSEL,
1678
1679 .inputreg = -1,
1680 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1681 .inputmute = TEA6420_S_GMU,
1682 .inputmask = 0x07,
1683 },
1684 {
1685 .name = "tda8425",
1686 .insmodopt = &tda8425,
1687 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1688 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1689 .registers = 9,
1690 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1691
1692 .leftreg = TDA8425_VL,
1693 .rightreg = TDA8425_VR,
1694 .bassreg = TDA8425_BA,
1695 .treblereg = TDA8425_TR,
1696
1697
1698 .volfunc = tda8425_shift10,
1699 .bassfunc = tda8425_shift12,
1700 .treblefunc = tda8425_shift12,
1701 .setaudmode = tda8425_setaudmode,
1702
1703 .inputreg = TDA8425_S1,
1704 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1705 .inputmute = TDA8425_S1_OFF,
1706
1707 },
1708 {
1709 .name = "pic16c54 (PV951)",
1710 .insmodopt = &pic16c54,
1711 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1712 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1713 .registers = 2,
1714 .flags = CHIP_HAS_INPUTSEL,
1715
1716 .inputreg = PIC16C54_REG_MISC,
1717 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1718 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1719 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1720 PIC16C54_MISC_SND_MUTE},
1721 .inputmute = PIC16C54_MISC_SND_MUTE,
1722 },
1723 {
1724 .name = "ta8874z",
1725 .checkit = ta8874z_checkit,
1726 .insmodopt = &ta8874z,
1727 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1728 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1729 .registers = 2,
1730
1731
1732 .getrxsubchans = ta8874z_getrxsubchans,
1733 .setaudmode = ta8874z_setaudmode,
1734
1735 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1736 },
1737 { .name = NULL }
1738 };
1739
1740
1741
1742
1743 static int tvaudio_s_ctrl(struct v4l2_ctrl *ctrl)
1744 {
1745 struct v4l2_subdev *sd = to_sd(ctrl);
1746 struct CHIPSTATE *chip = to_state(sd);
1747 struct CHIPDESC *desc = chip->desc;
1748
1749 switch (ctrl->id) {
1750 case V4L2_CID_AUDIO_MUTE:
1751 chip->muted = ctrl->val;
1752 if (chip->muted)
1753 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1754 else
1755 chip_write_masked(chip,desc->inputreg,
1756 desc->inputmap[chip->input],desc->inputmask);
1757 return 0;
1758 case V4L2_CID_AUDIO_VOLUME: {
1759 u32 volume, balance;
1760 u32 left, right;
1761
1762 volume = chip->volume->val;
1763 balance = chip->balance->val;
1764 left = (min(65536U - balance, 32768U) * volume) / 32768U;
1765 right = (min(balance, 32768U) * volume) / 32768U;
1766
1767 chip_write(chip, desc->leftreg, desc->volfunc(left));
1768 chip_write(chip, desc->rightreg, desc->volfunc(right));
1769 return 0;
1770 }
1771 case V4L2_CID_AUDIO_BASS:
1772 chip_write(chip, desc->bassreg, desc->bassfunc(ctrl->val));
1773 return 0;
1774 case V4L2_CID_AUDIO_TREBLE:
1775 chip_write(chip, desc->treblereg, desc->treblefunc(ctrl->val));
1776 return 0;
1777 }
1778 return -EINVAL;
1779 }
1780
1781
1782
1783
1784
1785 static int tvaudio_s_radio(struct v4l2_subdev *sd)
1786 {
1787 struct CHIPSTATE *chip = to_state(sd);
1788
1789 chip->radio = 1;
1790
1791 return 0;
1792 }
1793
1794 static int tvaudio_s_routing(struct v4l2_subdev *sd,
1795 u32 input, u32 output, u32 config)
1796 {
1797 struct CHIPSTATE *chip = to_state(sd);
1798 struct CHIPDESC *desc = chip->desc;
1799
1800 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1801 return 0;
1802 if (input >= 4)
1803 return -EINVAL;
1804
1805 chip->input = input;
1806 if (chip->muted)
1807 return 0;
1808 chip_write_masked(chip, desc->inputreg,
1809 desc->inputmap[chip->input], desc->inputmask);
1810 return 0;
1811 }
1812
1813 static int tvaudio_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
1814 {
1815 struct CHIPSTATE *chip = to_state(sd);
1816 struct CHIPDESC *desc = chip->desc;
1817
1818 if (!desc->setaudmode)
1819 return 0;
1820 if (chip->radio)
1821 return 0;
1822
1823 switch (vt->audmode) {
1824 case V4L2_TUNER_MODE_MONO:
1825 case V4L2_TUNER_MODE_STEREO:
1826 case V4L2_TUNER_MODE_LANG1:
1827 case V4L2_TUNER_MODE_LANG2:
1828 case V4L2_TUNER_MODE_LANG1_LANG2:
1829 break;
1830 default:
1831 return -EINVAL;
1832 }
1833 chip->audmode = vt->audmode;
1834
1835 if (chip->thread)
1836 wake_up_process(chip->thread);
1837 else
1838 desc->setaudmode(chip, vt->audmode);
1839
1840 return 0;
1841 }
1842
1843 static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1844 {
1845 struct CHIPSTATE *chip = to_state(sd);
1846 struct CHIPDESC *desc = chip->desc;
1847
1848 if (!desc->getrxsubchans)
1849 return 0;
1850 if (chip->radio)
1851 return 0;
1852
1853 vt->audmode = chip->audmode;
1854 vt->rxsubchans = desc->getrxsubchans(chip);
1855 vt->capability |= V4L2_TUNER_CAP_STEREO |
1856 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1857
1858 return 0;
1859 }
1860
1861 static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1862 {
1863 struct CHIPSTATE *chip = to_state(sd);
1864
1865 chip->radio = 0;
1866 return 0;
1867 }
1868
1869 static int tvaudio_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *freq)
1870 {
1871 struct CHIPSTATE *chip = to_state(sd);
1872 struct CHIPDESC *desc = chip->desc;
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882 if (chip->thread) {
1883 desc->setaudmode(chip, V4L2_TUNER_MODE_MONO);
1884 chip->prevmode = -1;
1885 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1886 }
1887 return 0;
1888 }
1889
1890 static int tvaudio_log_status(struct v4l2_subdev *sd)
1891 {
1892 struct CHIPSTATE *chip = to_state(sd);
1893 struct CHIPDESC *desc = chip->desc;
1894
1895 v4l2_info(sd, "Chip: %s\n", desc->name);
1896 v4l2_ctrl_handler_log_status(&chip->hdl, sd->name);
1897 return 0;
1898 }
1899
1900
1901
1902 static const struct v4l2_ctrl_ops tvaudio_ctrl_ops = {
1903 .s_ctrl = tvaudio_s_ctrl,
1904 };
1905
1906 static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
1907 .log_status = tvaudio_log_status,
1908 };
1909
1910 static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1911 .s_radio = tvaudio_s_radio,
1912 .s_frequency = tvaudio_s_frequency,
1913 .s_tuner = tvaudio_s_tuner,
1914 .g_tuner = tvaudio_g_tuner,
1915 };
1916
1917 static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1918 .s_routing = tvaudio_s_routing,
1919 };
1920
1921 static const struct v4l2_subdev_video_ops tvaudio_video_ops = {
1922 .s_std = tvaudio_s_std,
1923 };
1924
1925 static const struct v4l2_subdev_ops tvaudio_ops = {
1926 .core = &tvaudio_core_ops,
1927 .tuner = &tvaudio_tuner_ops,
1928 .audio = &tvaudio_audio_ops,
1929 .video = &tvaudio_video_ops,
1930 };
1931
1932
1933
1934
1935
1936
1937 static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1938 {
1939 struct CHIPSTATE *chip;
1940 struct CHIPDESC *desc;
1941 struct v4l2_subdev *sd;
1942
1943 if (debug) {
1944 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1945 printk(KERN_INFO "tvaudio: known chips: ");
1946 for (desc = chiplist; desc->name != NULL; desc++)
1947 printk(KERN_CONT "%s%s",
1948 (desc == chiplist) ? "" : ", ", desc->name);
1949 printk(KERN_CONT "\n");
1950 }
1951
1952 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1953 if (!chip)
1954 return -ENOMEM;
1955 sd = &chip->sd;
1956 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
1957
1958
1959 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1960 for (desc = chiplist; desc->name != NULL; desc++) {
1961 if (0 == *(desc->insmodopt))
1962 continue;
1963 if (client->addr < desc->addr_lo ||
1964 client->addr > desc->addr_hi)
1965 continue;
1966 if (desc->checkit && !desc->checkit(chip))
1967 continue;
1968 break;
1969 }
1970 if (desc->name == NULL) {
1971 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
1972 return -EIO;
1973 }
1974 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1975 if (desc->flags) {
1976 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1977 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1978 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1979 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1980 }
1981
1982
1983 if (!id)
1984 strscpy(client->name, desc->name, I2C_NAME_SIZE);
1985 chip->desc = desc;
1986 chip->shadow.count = desc->registers+1;
1987 chip->prevmode = -1;
1988 chip->audmode = V4L2_TUNER_MODE_LANG1;
1989
1990
1991 if (desc->initialize != NULL)
1992 desc->initialize(chip);
1993 else
1994 chip_cmd(chip, "init", &desc->init);
1995
1996 v4l2_ctrl_handler_init(&chip->hdl, 5);
1997 if (desc->flags & CHIP_HAS_INPUTSEL)
1998 v4l2_ctrl_new_std(&chip->hdl, &tvaudio_ctrl_ops,
1999 V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
2000 if (desc->flags & CHIP_HAS_VOLUME) {
2001 if (!desc->volfunc) {
2002
2003
2004
2005 v4l2_info(sd, "volume callback undefined!\n");
2006 desc->flags &= ~CHIP_HAS_VOLUME;
2007 } else {
2008 chip->volume = v4l2_ctrl_new_std(&chip->hdl,
2009 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
2010 0, 65535, 65535 / 100,
2011 desc->volinit ? desc->volinit : 65535);
2012 chip->balance = v4l2_ctrl_new_std(&chip->hdl,
2013 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BALANCE,
2014 0, 65535, 65535 / 100, 32768);
2015 v4l2_ctrl_cluster(2, &chip->volume);
2016 }
2017 }
2018 if (desc->flags & CHIP_HAS_BASSTREBLE) {
2019 if (!desc->bassfunc || !desc->treblefunc) {
2020
2021
2022
2023 v4l2_info(sd, "bass/treble callbacks undefined!\n");
2024 desc->flags &= ~CHIP_HAS_BASSTREBLE;
2025 } else {
2026 v4l2_ctrl_new_std(&chip->hdl,
2027 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BASS,
2028 0, 65535, 65535 / 100,
2029 desc->bassinit ? desc->bassinit : 32768);
2030 v4l2_ctrl_new_std(&chip->hdl,
2031 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_TREBLE,
2032 0, 65535, 65535 / 100,
2033 desc->trebleinit ? desc->trebleinit : 32768);
2034 }
2035 }
2036
2037 sd->ctrl_handler = &chip->hdl;
2038 if (chip->hdl.error) {
2039 int err = chip->hdl.error;
2040
2041 v4l2_ctrl_handler_free(&chip->hdl);
2042 return err;
2043 }
2044
2045 v4l2_ctrl_handler_setup(&chip->hdl);
2046
2047 chip->thread = NULL;
2048 timer_setup(&chip->wt, chip_thread_wake, 0);
2049 if (desc->flags & CHIP_NEED_CHECKMODE) {
2050 if (!desc->getrxsubchans || !desc->setaudmode) {
2051
2052
2053
2054 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2055 return 0;
2056 }
2057
2058 chip->thread = kthread_run(chip_thread, chip, "%s",
2059 client->name);
2060 if (IS_ERR(chip->thread)) {
2061 v4l2_warn(sd, "failed to create kthread\n");
2062 chip->thread = NULL;
2063 }
2064 }
2065 return 0;
2066 }
2067
2068 static int tvaudio_remove(struct i2c_client *client)
2069 {
2070 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2071 struct CHIPSTATE *chip = to_state(sd);
2072
2073 del_timer_sync(&chip->wt);
2074 if (chip->thread) {
2075
2076 kthread_stop(chip->thread);
2077 chip->thread = NULL;
2078 }
2079
2080 v4l2_device_unregister_subdev(sd);
2081 v4l2_ctrl_handler_free(&chip->hdl);
2082 return 0;
2083 }
2084
2085
2086
2087
2088 static const struct i2c_device_id tvaudio_id[] = {
2089 { "tvaudio", 0 },
2090 { }
2091 };
2092 MODULE_DEVICE_TABLE(i2c, tvaudio_id);
2093
2094 static struct i2c_driver tvaudio_driver = {
2095 .driver = {
2096 .name = "tvaudio",
2097 },
2098 .probe = tvaudio_probe,
2099 .remove = tvaudio_remove,
2100 .id_table = tvaudio_id,
2101 };
2102
2103 module_i2c_driver(tvaudio_driver);