media/i2c/ths8200.c

0001 /*
0002  * ths8200 - Texas Instruments THS8200 video encoder driver
0003  *
0004  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
0005  *
0006  * This program is free software; you may redistribute it and/or modify
0007  * it under the terms of the GNU General Public License as published by
0008  * the Free Software Foundation; version 2 of the License.
0009  *
0010  * This program is free software; you can redistribute it and/or
0011  * modify it under the terms of the GNU General Public License as
0012  * published by the Free Software Foundation version 2.
0013  *
0014  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
0015  * kind, whether express or implied; without even the implied warranty
0016  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0017  * GNU General Public License for more details.
0018  */
0019
0020 #include <linux/i2c.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/v4l2-dv-timings.h>
0024
0025 #include <media/v4l2-dv-timings.h>
0026 #include <media/v4l2-async.h>
0027 #include <media/v4l2-device.h>
0028
0029 #include "ths8200_regs.h"
0030
0031 static int debug;
0032 module_param(debug, int, 0644);
0033 MODULE_PARM_DESC(debug, "debug level (0-2)");
0034
0035 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver");
0036 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
0037 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>");
0038 MODULE_LICENSE("GPL v2");
0039
0040 struct ths8200_state {
0041     struct v4l2_subdev sd;
0042     uint8_t chip_version;
0043     /* Is the ths8200 powered on? */
0044     bool power_on;
0045     struct v4l2_dv_timings dv_timings;
0046 };
0047
0048 static const struct v4l2_dv_timings_cap ths8200_timings_cap = {
0049     .type = V4L2_DV_BT_656_1120,
0050     /* keep this initialization for compatibility with GCC < 4.4.6 */
0051     .reserved = { 0 },
0052     V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1080, 25000000, 148500000,
0053         V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE)
0054 };
0055
0056 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd)
0057 {
0058     return container_of(sd, struct ths8200_state, sd);
0059 }
0060
0061 static inline unsigned htotal(const struct v4l2_bt_timings *t)
0062 {
0063     return V4L2_DV_BT_FRAME_WIDTH(t);
0064 }
0065
0066 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
0067 {
0068     return V4L2_DV_BT_FRAME_HEIGHT(t);
0069 }
0070
0071 static int ths8200_read(struct v4l2_subdev *sd, u8 reg)
0072 {
0073     struct i2c_client *client = v4l2_get_subdevdata(sd);
0074
0075     return i2c_smbus_read_byte_data(client, reg);
0076 }
0077
0078 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0079 {
0080     struct i2c_client *client = v4l2_get_subdevdata(sd);
0081     int ret;
0082     int i;
0083
0084     for (i = 0; i < 3; i++) {
0085         ret = i2c_smbus_write_byte_data(client, reg, val);
0086         if (ret == 0)
0087             return 0;
0088     }
0089     v4l2_err(sd, "I2C Write Problem\n");
0090     return ret;
0091 }
0092
0093 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
0094  * and then the value-mask (to be OR-ed).
0095  */
0096 static inline void
0097 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg,
0098              uint8_t clr_mask, uint8_t val_mask)
0099 {
0100     ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask);
0101 }
0102
0103 #ifdef CONFIG_VIDEO_ADV_DEBUG
0104
0105 static int ths8200_g_register(struct v4l2_subdev *sd,
0106                   struct v4l2_dbg_register *reg)
0107 {
0108     reg->val = ths8200_read(sd, reg->reg & 0xff);
0109     reg->size = 1;
0110
0111     return 0;
0112 }
0113
0114 static int ths8200_s_register(struct v4l2_subdev *sd,
0115                   const struct v4l2_dbg_register *reg)
0116 {
0117     ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff);
0118
0119     return 0;
0120 }
0121 #endif
0122
0123 static int ths8200_log_status(struct v4l2_subdev *sd)
0124 {
0125     struct ths8200_state *state = to_state(sd);
0126     uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL);
0127
0128     v4l2_info(sd, "----- Chip status -----\n");
0129     v4l2_info(sd, "version: %u\n", state->chip_version);
0130     v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on");
0131     v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on");
0132     v4l2_info(sd, "test pattern: %s\n",
0133           (reg_03 & 0x20) ? "enabled" : "disabled");
0134     v4l2_info(sd, "format: %ux%u\n",
0135           ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 +
0136           ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB),
0137           (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 +
0138           ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB));
0139     v4l2_print_dv_timings(sd->name, "Configured format:",
0140                   &state->dv_timings, true);
0141     return 0;
0142 }
0143
0144 /* Power up/down ths8200 */
0145 static int ths8200_s_power(struct v4l2_subdev *sd, int on)
0146 {
0147     struct ths8200_state *state = to_state(sd);
0148
0149     v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
0150
0151     state->power_on = on;
0152
0153     /* Power up/down - leave in reset state until input video is present */
0154     ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c));
0155
0156     return 0;
0157 }
0158
0159 static const struct v4l2_subdev_core_ops ths8200_core_ops = {
0160     .log_status = ths8200_log_status,
0161     .s_power = ths8200_s_power,
0162 #ifdef CONFIG_VIDEO_ADV_DEBUG
0163     .g_register = ths8200_g_register,
0164     .s_register = ths8200_s_register,
0165 #endif
0166 };
0167
0168 /* -----------------------------------------------------------------------------
0169  * V4L2 subdev video operations
0170  */
0171
0172 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable)
0173 {
0174     struct ths8200_state *state = to_state(sd);
0175
0176     if (enable && !state->power_on)
0177         ths8200_s_power(sd, true);
0178
0179     ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe,
0180                  (enable ? 0x01 : 0x00));
0181
0182     v4l2_dbg(1, debug, sd, "%s: %sable\n",
0183          __func__, (enable ? "en" : "dis"));
0184
0185     return 0;
0186 }
0187
0188 static void ths8200_core_init(struct v4l2_subdev *sd)
0189 {
0190     /* setup clocks */
0191     ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0);
0192
0193     /**** Data path control (DATA) ****/
0194     /* Set FSADJ 700 mV,
0195      * bypass 422-444 interpolation,
0196      * input format 30 bit RGB444
0197      */
0198     ths8200_write(sd, THS8200_DATA_CNTL, 0x70);
0199
0200     /* DTG Mode (Video blocked during blanking
0201      * VESA slave
0202      */
0203     ths8200_write(sd, THS8200_DTG1_MODE, 0x87);
0204
0205     /**** Display Timing Generator Control, Part 1 (DTG1). ****/
0206
0207     /* Disable embedded syncs on the output by setting
0208      * the amplitude to zero for all channels.
0209      */
0210     ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00);
0211     ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00);
0212 }
0213
0214 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)
0215 {
0216     uint8_t polarity = 0;
0217     uint16_t line_start_active_video = (bt->vsync + bt->vbackporch);
0218     uint16_t line_start_front_porch  = (vtotal(bt) - bt->vfrontporch);
0219
0220     /*** System ****/
0221     /* Set chip in reset while it is configured */
0222     ths8200_s_stream(sd, false);
0223
0224     /* configure video output timings */
0225     ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync);
0226     ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch);
0227
0228     /* Zero for progressive scan formats.*/
0229     if (!bt->interlaced)
0230         ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00);
0231
0232     /* Distance from leading edge of h sync to start of active video.
0233      * MSB in 0x2b
0234      */
0235     ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB,
0236               (bt->hbackporch + bt->hsync) & 0xff);
0237     /* Zero for SDTV-mode. MSB in 0x2b */
0238     ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00);
0239     /*
0240      * MSB for dtg1_spec(d/e/h). See comment for
0241      * corresponding LSB registers.
0242      */
0243     ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB,
0244               ((bt->hbackporch + bt->hsync) & 0x100) >> 1);
0245
0246     /* h front porch */
0247     ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff);
0248     ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB,
0249               ((bt->hfrontporch) & 0x700) >> 8);
0250
0251     /* Half the line length. Used to calculate SDTV line types. */
0252     ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff);
0253     ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB,
0254               ((htotal(bt)/2) >> 8) & 0x0f);
0255
0256     /* Total pixels per line (ex. 720p: 1650) */
0257     ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8);
0258     ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff);
0259
0260     /* Frame height and field height */
0261     /* Field height should be programmed higher than frame_size for
0262      * progressive scan formats
0263      */
0264     ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB,
0265               ((vtotal(bt) >> 4) & 0xf0) + 0x7);
0266     ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff);
0267
0268     /* Should be programmed higher than frame_size
0269      * for progressive formats
0270      */
0271     if (!bt->interlaced)
0272         ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff);
0273
0274     /**** Display Timing Generator Control, Part 2 (DTG2). ****/
0275     /* Set breakpoint line numbers and types
0276      * THS8200 generates line types with different properties. A line type
0277      * that sets all the RGB-outputs to zero is used in the blanking areas,
0278      * while a line type that enable the RGB-outputs is used in active video
0279      * area. The line numbers for start of active video, start of front
0280      * porch and after the last line in the frame must be set with the
0281      * corresponding line types.
0282      *
0283      * Line types:
0284      * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off.
0285      *       Used in blanking area.
0286      * 0x0 - Active video: Video data is always passed. Used in active
0287      *       video area.
0288      */
0289     ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88,
0290                  ((line_start_active_video >> 4) & 0x70) +
0291                  ((line_start_front_porch >> 8) & 0x07));
0292     ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70);
0293     ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff);
0294     ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff);
0295     ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff);
0296
0297     /* line types */
0298     ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90);
0299     ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90);
0300
0301     /* h sync width transmitted */
0302     ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff);
0303     ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f,
0304                  (bt->hsync >> 2) & 0xc0);
0305
0306     /* The pixel value h sync is asserted on */
0307     ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0,
0308                  (htotal(bt) >> 8) & 0x1f);
0309     ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt));
0310
0311     /* v sync width transmitted (must add 1 to get correct output) */
0312     ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff);
0313     ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f,
0314                  ((bt->vsync + 1) >> 2) & 0xc0);
0315
0316     /* The pixel value v sync is asserted on (must add 1 to get correct output) */
0317     ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8,
0318                  ((vtotal(bt) + 1) >> 8) & 0x7);
0319     ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1);
0320
0321     /* For progressive video vlength2 must be set to all 0 and vdly2 must
0322      * be set to all 1.
0323      */
0324     ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00);
0325     ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07);
0326     ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff);
0327
0328     /* Internal delay factors to synchronize the sync pulses and the data */
0329     /* Experimental values delays (hor 0, ver 0) */
0330     ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0);
0331     ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0);
0332     ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0);
0333     ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0);
0334
0335     /* Polarity of received and transmitted sync signals */
0336     if (bt->polarities & V4L2_DV_HSYNC_POS_POL) {
0337         polarity |= 0x01; /* HS_IN */
0338         polarity |= 0x08; /* HS_OUT */
0339     }
0340     if (bt->polarities & V4L2_DV_VSYNC_POS_POL) {
0341         polarity |= 0x02; /* VS_IN */
0342         polarity |= 0x10; /* VS_OUT */
0343     }
0344
0345     /* RGB mode, no embedded timings */
0346     /* Timing of video input bus is derived from HS, VS, and FID dedicated
0347      * inputs
0348      */
0349     ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity);
0350
0351     /* leave reset */
0352     ths8200_s_stream(sd, true);
0353
0354     v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n"
0355          "horizontal: front porch %d, back porch %d, sync %d\n"
0356          "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt),
0357          polarity, bt->hfrontporch, bt->hbackporch,
0358          bt->hsync, bt->vsync);
0359 }
0360
0361 static int ths8200_s_dv_timings(struct v4l2_subdev *sd,
0362                 struct v4l2_dv_timings *timings)
0363 {
0364     struct ths8200_state *state = to_state(sd);
0365
0366     v4l2_dbg(1, debug, sd, "%s:\n", __func__);
0367
0368     if (!v4l2_valid_dv_timings(timings, &ths8200_timings_cap,
0369                 NULL, NULL))
0370         return -EINVAL;
0371
0372     if (!v4l2_find_dv_timings_cap(timings, &ths8200_timings_cap, 10,
0373                 NULL, NULL)) {
0374         v4l2_dbg(1, debug, sd, "Unsupported format\n");
0375         return -EINVAL;
0376     }
0377
0378     timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
0379
0380     /* save timings */
0381     state->dv_timings = *timings;
0382
0383     ths8200_setup(sd, &timings->bt);
0384
0385     return 0;
0386 }
0387
0388 static int ths8200_g_dv_timings(struct v4l2_subdev *sd,
0389                 struct v4l2_dv_timings *timings)
0390 {
0391     struct ths8200_state *state = to_state(sd);
0392
0393     v4l2_dbg(1, debug, sd, "%s:\n", __func__);
0394
0395     *timings = state->dv_timings;
0396
0397     return 0;
0398 }
0399
0400 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd,
0401                    struct v4l2_enum_dv_timings *timings)
0402 {
0403     if (timings->pad != 0)
0404         return -EINVAL;
0405
0406     return v4l2_enum_dv_timings_cap(timings, &ths8200_timings_cap,
0407             NULL, NULL);
0408 }
0409
0410 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd,
0411                   struct v4l2_dv_timings_cap *cap)
0412 {
0413     if (cap->pad != 0)
0414         return -EINVAL;
0415
0416     *cap = ths8200_timings_cap;
0417     return 0;
0418 }
0419
0420 /* Specific video subsystem operation handlers */
0421 static const struct v4l2_subdev_video_ops ths8200_video_ops = {
0422     .s_stream = ths8200_s_stream,
0423     .s_dv_timings = ths8200_s_dv_timings,
0424     .g_dv_timings = ths8200_g_dv_timings,
0425 };
0426
0427 static const struct v4l2_subdev_pad_ops ths8200_pad_ops = {
0428     .enum_dv_timings = ths8200_enum_dv_timings,
0429     .dv_timings_cap = ths8200_dv_timings_cap,
0430 };
0431
0432 /* V4L2 top level operation handlers */
0433 static const struct v4l2_subdev_ops ths8200_ops = {
0434     .core  = &ths8200_core_ops,
0435     .video = &ths8200_video_ops,
0436     .pad = &ths8200_pad_ops,
0437 };
0438
0439 static int ths8200_probe(struct i2c_client *client)
0440 {
0441     struct ths8200_state *state;
0442     struct v4l2_subdev *sd;
0443     int error;
0444
0445     /* Check if the adapter supports the needed features */
0446     if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
0447         return -EIO;
0448
0449     state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
0450     if (!state)
0451         return -ENOMEM;
0452
0453     sd = &state->sd;
0454     v4l2_i2c_subdev_init(sd, client, &ths8200_ops);
0455
0456     state->chip_version = ths8200_read(sd, THS8200_VERSION);
0457     v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version);
0458
0459     ths8200_core_init(sd);
0460
0461     error = v4l2_async_register_subdev(&state->sd);
0462     if (error)
0463         return error;
0464
0465     v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
0466           client->addr << 1, client->adapter->name);
0467
0468     return 0;
0469 }
0470
0471 static int ths8200_remove(struct i2c_client *client)
0472 {
0473     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0474     struct ths8200_state *decoder = to_state(sd);
0475
0476     v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
0477          client->addr << 1, client->adapter->name);
0478
0479     ths8200_s_power(sd, false);
0480     v4l2_async_unregister_subdev(&decoder->sd);
0481
0482     return 0;
0483 }
0484
0485 static const struct i2c_device_id ths8200_id[] = {
0486     { "ths8200", 0 },
0487     {},
0488 };
0489 MODULE_DEVICE_TABLE(i2c, ths8200_id);
0490
0491 #if IS_ENABLED(CONFIG_OF)
0492 static const struct of_device_id ths8200_of_match[] = {
0493     { .compatible = "ti,ths8200", },
0494     { /* sentinel */ },
0495 };
0496 MODULE_DEVICE_TABLE(of, ths8200_of_match);
0497 #endif
0498
0499 static struct i2c_driver ths8200_driver = {
0500     .driver = {
0501         .name = "ths8200",
0502         .of_match_table = of_match_ptr(ths8200_of_match),
0503     },
0504     .probe_new = ths8200_probe,
0505     .remove = ths8200_remove,
0506     .id_table = ths8200_id,
0507 };
0508
0509 module_i2c_driver(ths8200_driver);