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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * tc358743 - Toshiba HDMI to CSI-2 bridge
0004  *
0005  * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
0006  * reserved.
0007  */
0008 
0009 /*
0010  * References (c = chapter, p = page):
0011  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
0012  * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
0013  */
0014 
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/slab.h>
0018 #include <linux/i2c.h>
0019 #include <linux/clk.h>
0020 #include <linux/delay.h>
0021 #include <linux/gpio/consumer.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/timer.h>
0024 #include <linux/of_graph.h>
0025 #include <linux/videodev2.h>
0026 #include <linux/workqueue.h>
0027 #include <linux/v4l2-dv-timings.h>
0028 #include <linux/hdmi.h>
0029 #include <media/cec.h>
0030 #include <media/v4l2-dv-timings.h>
0031 #include <media/v4l2-device.h>
0032 #include <media/v4l2-ctrls.h>
0033 #include <media/v4l2-event.h>
0034 #include <media/v4l2-fwnode.h>
0035 #include <media/i2c/tc358743.h>
0036 
0037 #include "tc358743_regs.h"
0038 
0039 static int debug;
0040 module_param(debug, int, 0644);
0041 MODULE_PARM_DESC(debug, "debug level (0-3)");
0042 
0043 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
0044 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
0045 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
0046 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
0047 MODULE_LICENSE("GPL");
0048 
0049 #define EDID_NUM_BLOCKS_MAX 8
0050 #define EDID_BLOCK_SIZE 128
0051 
0052 #define I2C_MAX_XFER_SIZE  (EDID_BLOCK_SIZE + 2)
0053 
0054 #define POLL_INTERVAL_CEC_MS    10
0055 #define POLL_INTERVAL_MS    1000
0056 
0057 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
0058     .type = V4L2_DV_BT_656_1120,
0059     /* keep this initialization for compatibility with GCC < 4.4.6 */
0060     .reserved = { 0 },
0061     /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
0062     V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000,
0063             V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
0064             V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
0065             V4L2_DV_BT_CAP_PROGRESSIVE |
0066             V4L2_DV_BT_CAP_REDUCED_BLANKING |
0067             V4L2_DV_BT_CAP_CUSTOM)
0068 };
0069 
0070 struct tc358743_state {
0071     struct tc358743_platform_data pdata;
0072     struct v4l2_mbus_config_mipi_csi2 bus;
0073     struct v4l2_subdev sd;
0074     struct media_pad pad;
0075     struct v4l2_ctrl_handler hdl;
0076     struct i2c_client *i2c_client;
0077     /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
0078     struct mutex confctl_mutex;
0079 
0080     /* controls */
0081     struct v4l2_ctrl *detect_tx_5v_ctrl;
0082     struct v4l2_ctrl *audio_sampling_rate_ctrl;
0083     struct v4l2_ctrl *audio_present_ctrl;
0084 
0085     struct delayed_work delayed_work_enable_hotplug;
0086 
0087     struct timer_list timer;
0088     struct work_struct work_i2c_poll;
0089 
0090     /* edid  */
0091     u8 edid_blocks_written;
0092 
0093     struct v4l2_dv_timings timings;
0094     u32 mbus_fmt_code;
0095     u8 csi_lanes_in_use;
0096 
0097     struct gpio_desc *reset_gpio;
0098 
0099     struct cec_adapter *cec_adap;
0100 };
0101 
0102 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
0103         bool cable_connected);
0104 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
0105 
0106 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
0107 {
0108     return container_of(sd, struct tc358743_state, sd);
0109 }
0110 
0111 /* --------------- I2C --------------- */
0112 
0113 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
0114 {
0115     struct tc358743_state *state = to_state(sd);
0116     struct i2c_client *client = state->i2c_client;
0117     int err;
0118     u8 buf[2] = { reg >> 8, reg & 0xff };
0119     struct i2c_msg msgs[] = {
0120         {
0121             .addr = client->addr,
0122             .flags = 0,
0123             .len = 2,
0124             .buf = buf,
0125         },
0126         {
0127             .addr = client->addr,
0128             .flags = I2C_M_RD,
0129             .len = n,
0130             .buf = values,
0131         },
0132     };
0133 
0134     err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0135     if (err != ARRAY_SIZE(msgs)) {
0136         v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
0137                 __func__, reg, client->addr);
0138     }
0139 }
0140 
0141 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
0142 {
0143     struct tc358743_state *state = to_state(sd);
0144     struct i2c_client *client = state->i2c_client;
0145     int err, i;
0146     struct i2c_msg msg;
0147     u8 data[I2C_MAX_XFER_SIZE];
0148 
0149     if ((2 + n) > I2C_MAX_XFER_SIZE) {
0150         n = I2C_MAX_XFER_SIZE - 2;
0151         v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
0152               reg, 2 + n);
0153     }
0154 
0155     msg.addr = client->addr;
0156     msg.buf = data;
0157     msg.len = 2 + n;
0158     msg.flags = 0;
0159 
0160     data[0] = reg >> 8;
0161     data[1] = reg & 0xff;
0162 
0163     for (i = 0; i < n; i++)
0164         data[2 + i] = values[i];
0165 
0166     err = i2c_transfer(client->adapter, &msg, 1);
0167     if (err != 1) {
0168         v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
0169                 __func__, reg, client->addr);
0170         return;
0171     }
0172 
0173     if (debug < 3)
0174         return;
0175 
0176     switch (n) {
0177     case 1:
0178         v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
0179                 reg, data[2]);
0180         break;
0181     case 2:
0182         v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
0183                 reg, data[3], data[2]);
0184         break;
0185     case 4:
0186         v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
0187                 reg, data[5], data[4], data[3], data[2]);
0188         break;
0189     default:
0190         v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
0191                 n, reg);
0192     }
0193 }
0194 
0195 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
0196 {
0197     __le32 val = 0;
0198 
0199     i2c_rd(sd, reg, (u8 __force *)&val, n);
0200 
0201     return le32_to_cpu(val);
0202 }
0203 
0204 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
0205 {
0206     __le32 raw = cpu_to_le32(val);
0207 
0208     i2c_wr(sd, reg, (u8 __force *)&raw, n);
0209 }
0210 
0211 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
0212 {
0213     return i2c_rdreg(sd, reg, 1);
0214 }
0215 
0216 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
0217 {
0218     i2c_wrreg(sd, reg, val, 1);
0219 }
0220 
0221 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
0222         u8 mask, u8 val)
0223 {
0224     i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
0225 }
0226 
0227 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
0228 {
0229     return i2c_rdreg(sd, reg, 2);
0230 }
0231 
0232 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
0233 {
0234     i2c_wrreg(sd, reg, val, 2);
0235 }
0236 
0237 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
0238 {
0239     i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
0240 }
0241 
0242 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
0243 {
0244     return i2c_rdreg(sd, reg, 4);
0245 }
0246 
0247 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
0248 {
0249     i2c_wrreg(sd, reg, val, 4);
0250 }
0251 
0252 /* --------------- STATUS --------------- */
0253 
0254 static inline bool is_hdmi(struct v4l2_subdev *sd)
0255 {
0256     return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
0257 }
0258 
0259 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
0260 {
0261     return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
0262 }
0263 
0264 static inline bool no_signal(struct v4l2_subdev *sd)
0265 {
0266     return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
0267 }
0268 
0269 static inline bool no_sync(struct v4l2_subdev *sd)
0270 {
0271     return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
0272 }
0273 
0274 static inline bool audio_present(struct v4l2_subdev *sd)
0275 {
0276     return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
0277 }
0278 
0279 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
0280 {
0281     static const int code_to_rate[] = {
0282         44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
0283         88200, 768000, 96000, 705600, 176400, 0, 192000, 0
0284     };
0285 
0286     /* Register FS_SET is not cleared when the cable is disconnected */
0287     if (no_signal(sd))
0288         return 0;
0289 
0290     return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
0291 }
0292 
0293 /* --------------- TIMINGS --------------- */
0294 
0295 static inline unsigned fps(const struct v4l2_bt_timings *t)
0296 {
0297     if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
0298         return 0;
0299 
0300     return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
0301             V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
0302 }
0303 
0304 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
0305                      struct v4l2_dv_timings *timings)
0306 {
0307     struct v4l2_bt_timings *bt = &timings->bt;
0308     unsigned width, height, frame_width, frame_height, frame_interval, fps;
0309 
0310     memset(timings, 0, sizeof(struct v4l2_dv_timings));
0311 
0312     if (no_signal(sd)) {
0313         v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
0314         return -ENOLINK;
0315     }
0316     if (no_sync(sd)) {
0317         v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
0318         return -ENOLCK;
0319     }
0320 
0321     timings->type = V4L2_DV_BT_656_1120;
0322     bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
0323         V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
0324 
0325     width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
0326         i2c_rd8(sd, DE_WIDTH_H_LO);
0327     height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
0328         i2c_rd8(sd, DE_WIDTH_V_LO);
0329     frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
0330         i2c_rd8(sd, H_SIZE_LO);
0331     frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
0332         i2c_rd8(sd, V_SIZE_LO)) / 2;
0333     /* frame interval in milliseconds * 10
0334      * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
0335     frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
0336         i2c_rd8(sd, FV_CNT_LO);
0337     fps = (frame_interval > 0) ?
0338         DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
0339 
0340     bt->width = width;
0341     bt->height = height;
0342     bt->vsync = frame_height - height;
0343     bt->hsync = frame_width - width;
0344     bt->pixelclock = frame_width * frame_height * fps;
0345     if (bt->interlaced == V4L2_DV_INTERLACED) {
0346         bt->height *= 2;
0347         bt->il_vsync = bt->vsync + 1;
0348         bt->pixelclock /= 2;
0349     }
0350 
0351     return 0;
0352 }
0353 
0354 /* --------------- HOTPLUG / HDCP / EDID --------------- */
0355 
0356 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
0357 {
0358     struct delayed_work *dwork = to_delayed_work(work);
0359     struct tc358743_state *state = container_of(dwork,
0360             struct tc358743_state, delayed_work_enable_hotplug);
0361     struct v4l2_subdev *sd = &state->sd;
0362 
0363     v4l2_dbg(2, debug, sd, "%s:\n", __func__);
0364 
0365     i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
0366 }
0367 
0368 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
0369 {
0370     v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
0371                 "enable" : "disable");
0372 
0373     if (enable) {
0374         i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
0375 
0376         i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
0377 
0378         i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
0379                 MASK_AUTH_UNAUTH_SEL_16_FRAMES |
0380                 MASK_AUTH_UNAUTH_AUTO);
0381 
0382         i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
0383                 SET_AUTO_P3_RESET_FRAMES(0x0f));
0384     } else {
0385         i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
0386                 MASK_MANUAL_AUTHENTICATION);
0387     }
0388 }
0389 
0390 static void tc358743_disable_edid(struct v4l2_subdev *sd)
0391 {
0392     struct tc358743_state *state = to_state(sd);
0393 
0394     v4l2_dbg(2, debug, sd, "%s:\n", __func__);
0395 
0396     cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
0397 
0398     /* DDC access to EDID is also disabled when hotplug is disabled. See
0399      * register DDC_CTL */
0400     i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
0401 }
0402 
0403 static void tc358743_enable_edid(struct v4l2_subdev *sd)
0404 {
0405     struct tc358743_state *state = to_state(sd);
0406 
0407     if (state->edid_blocks_written == 0) {
0408         v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
0409         tc358743_s_ctrl_detect_tx_5v(sd);
0410         return;
0411     }
0412 
0413     v4l2_dbg(2, debug, sd, "%s:\n", __func__);
0414 
0415     /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
0416      * hotplug is enabled. See register DDC_CTL */
0417     schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
0418 
0419     tc358743_enable_interrupts(sd, true);
0420     tc358743_s_ctrl_detect_tx_5v(sd);
0421 }
0422 
0423 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
0424 {
0425     int i;
0426 
0427     for (i = 0; i < 5; i++)
0428         i2c_wr8(sd, BKSV + i, 0);
0429 }
0430 
0431 /* --------------- AVI infoframe --------------- */
0432 
0433 static void print_avi_infoframe(struct v4l2_subdev *sd)
0434 {
0435     struct i2c_client *client = v4l2_get_subdevdata(sd);
0436     struct device *dev = &client->dev;
0437     union hdmi_infoframe frame;
0438     u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
0439 
0440     if (!is_hdmi(sd)) {
0441         v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
0442         return;
0443     }
0444 
0445     i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
0446 
0447     if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
0448         v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
0449         return;
0450     }
0451 
0452     hdmi_infoframe_log(KERN_INFO, dev, &frame);
0453 }
0454 
0455 /* --------------- CTRLS --------------- */
0456 
0457 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
0458 {
0459     struct tc358743_state *state = to_state(sd);
0460 
0461     return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
0462             tx_5v_power_present(sd));
0463 }
0464 
0465 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
0466 {
0467     struct tc358743_state *state = to_state(sd);
0468 
0469     return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
0470             get_audio_sampling_rate(sd));
0471 }
0472 
0473 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
0474 {
0475     struct tc358743_state *state = to_state(sd);
0476 
0477     return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
0478             audio_present(sd));
0479 }
0480 
0481 static int tc358743_update_controls(struct v4l2_subdev *sd)
0482 {
0483     int ret = 0;
0484 
0485     ret |= tc358743_s_ctrl_detect_tx_5v(sd);
0486     ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
0487     ret |= tc358743_s_ctrl_audio_present(sd);
0488 
0489     return ret;
0490 }
0491 
0492 /* --------------- INIT --------------- */
0493 
0494 static void tc358743_reset_phy(struct v4l2_subdev *sd)
0495 {
0496     v4l2_dbg(1, debug, sd, "%s:\n", __func__);
0497 
0498     i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
0499     i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
0500 }
0501 
0502 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
0503 {
0504     u16 sysctl = i2c_rd16(sd, SYSCTL);
0505 
0506     i2c_wr16(sd, SYSCTL, sysctl | mask);
0507     i2c_wr16(sd, SYSCTL, sysctl & ~mask);
0508 }
0509 
0510 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
0511 {
0512     i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
0513             enable ? MASK_SLEEP : 0);
0514 }
0515 
0516 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
0517 {
0518     struct tc358743_state *state = to_state(sd);
0519 
0520     v4l2_dbg(3, debug, sd, "%s: %sable\n",
0521             __func__, enable ? "en" : "dis");
0522 
0523     if (enable) {
0524         /* It is critical for CSI receiver to see lane transition
0525          * LP11->HS. Set to non-continuous mode to enable clock lane
0526          * LP11 state. */
0527         i2c_wr32(sd, TXOPTIONCNTRL, 0);
0528         /* Set to continuous mode to trigger LP11->HS transition */
0529         i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
0530         /* Unmute video */
0531         i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
0532     } else {
0533         /* Mute video so that all data lanes go to LSP11 state.
0534          * No data is output to CSI Tx block. */
0535         i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
0536     }
0537 
0538     mutex_lock(&state->confctl_mutex);
0539     i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
0540             enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
0541     mutex_unlock(&state->confctl_mutex);
0542 }
0543 
0544 static void tc358743_set_pll(struct v4l2_subdev *sd)
0545 {
0546     struct tc358743_state *state = to_state(sd);
0547     struct tc358743_platform_data *pdata = &state->pdata;
0548     u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
0549     u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
0550     u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
0551         SET_PLL_FBD(pdata->pll_fbd);
0552     u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
0553 
0554     v4l2_dbg(2, debug, sd, "%s:\n", __func__);
0555 
0556     /* Only rewrite when needed (new value or disabled), since rewriting
0557      * triggers another format change event. */
0558     if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
0559         u16 pll_frs;
0560 
0561         if (hsck > 500000000)
0562             pll_frs = 0x0;
0563         else if (hsck > 250000000)
0564             pll_frs = 0x1;
0565         else if (hsck > 125000000)
0566             pll_frs = 0x2;
0567         else
0568             pll_frs = 0x3;
0569 
0570         v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
0571         tc358743_sleep_mode(sd, true);
0572         i2c_wr16(sd, PLLCTL0, pllctl0_new);
0573         i2c_wr16_and_or(sd, PLLCTL1,
0574                 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
0575                 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
0576                  MASK_PLL_EN));
0577         udelay(10); /* REF_02, Sheet "Source HDMI" */
0578         i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
0579         tc358743_sleep_mode(sd, false);
0580     }
0581 }
0582 
0583 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
0584 {
0585     struct tc358743_state *state = to_state(sd);
0586     struct tc358743_platform_data *pdata = &state->pdata;
0587     u32 sys_freq;
0588     u32 lockdet_ref;
0589     u32 cec_freq;
0590     u16 fh_min;
0591     u16 fh_max;
0592 
0593     BUG_ON(!(pdata->refclk_hz == 26000000 ||
0594          pdata->refclk_hz == 27000000 ||
0595          pdata->refclk_hz == 42000000));
0596 
0597     sys_freq = pdata->refclk_hz / 10000;
0598     i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
0599     i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
0600 
0601     i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
0602             (pdata->refclk_hz == 42000000) ?
0603             MASK_PHY_SYSCLK_IND : 0x0);
0604 
0605     fh_min = pdata->refclk_hz / 100000;
0606     i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
0607     i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
0608 
0609     fh_max = (fh_min * 66) / 10;
0610     i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
0611     i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
0612 
0613     lockdet_ref = pdata->refclk_hz / 100;
0614     i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
0615     i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
0616     i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
0617 
0618     i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
0619             (pdata->refclk_hz == 27000000) ?
0620             MASK_NCO_F0_MOD_27MHZ : 0x0);
0621 
0622     /*
0623      * Trial and error suggests that the default register value
0624      * of 656 is for a 42 MHz reference clock. Use that to derive
0625      * a new value based on the actual reference clock.
0626      */
0627     cec_freq = (656 * sys_freq) / 4200;
0628     i2c_wr16(sd, CECHCLK, cec_freq);
0629     i2c_wr16(sd, CECLCLK, cec_freq);
0630 }
0631 
0632 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
0633 {
0634     struct tc358743_state *state = to_state(sd);
0635 
0636     switch (state->mbus_fmt_code) {
0637     case MEDIA_BUS_FMT_UYVY8_1X16:
0638         v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
0639         i2c_wr8_and_or(sd, VOUT_SET2,
0640                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
0641                 MASK_SEL422 | MASK_VOUT_422FIL_100);
0642         i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
0643                 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
0644         mutex_lock(&state->confctl_mutex);
0645         i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
0646                 MASK_YCBCRFMT_422_8_BIT);
0647         mutex_unlock(&state->confctl_mutex);
0648         break;
0649     case MEDIA_BUS_FMT_RGB888_1X24:
0650         v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
0651         i2c_wr8_and_or(sd, VOUT_SET2,
0652                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
0653                 0x00);
0654         i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
0655                 MASK_VOUT_COLOR_RGB_FULL);
0656         mutex_lock(&state->confctl_mutex);
0657         i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
0658         mutex_unlock(&state->confctl_mutex);
0659         break;
0660     default:
0661         v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
0662                 __func__, state->mbus_fmt_code);
0663     }
0664 }
0665 
0666 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
0667 {
0668     struct tc358743_state *state = to_state(sd);
0669     struct v4l2_bt_timings *bt = &state->timings.bt;
0670     struct tc358743_platform_data *pdata = &state->pdata;
0671     u32 bits_pr_pixel =
0672         (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ?  16 : 24;
0673     u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
0674     u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
0675 
0676     return DIV_ROUND_UP(bps, bps_pr_lane);
0677 }
0678 
0679 static void tc358743_set_csi(struct v4l2_subdev *sd)
0680 {
0681     struct tc358743_state *state = to_state(sd);
0682     struct tc358743_platform_data *pdata = &state->pdata;
0683     unsigned lanes = tc358743_num_csi_lanes_needed(sd);
0684 
0685     v4l2_dbg(3, debug, sd, "%s:\n", __func__);
0686 
0687     state->csi_lanes_in_use = lanes;
0688 
0689     tc358743_reset(sd, MASK_CTXRST);
0690 
0691     if (lanes < 1)
0692         i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
0693     if (lanes < 1)
0694         i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
0695     if (lanes < 2)
0696         i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
0697     if (lanes < 3)
0698         i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
0699     if (lanes < 4)
0700         i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
0701 
0702     i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
0703     i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
0704     i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
0705     i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
0706     i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
0707     i2c_wr32(sd, TWAKEUP, pdata->twakeup);
0708     i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
0709     i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
0710     i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
0711 
0712     i2c_wr32(sd, HSTXVREGEN,
0713             ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
0714             ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
0715             ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
0716             ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
0717             ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
0718 
0719     i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
0720          V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE);
0721     i2c_wr32(sd, STARTCNTRL, MASK_START);
0722     i2c_wr32(sd, CSI_START, MASK_STRT);
0723 
0724     i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
0725             MASK_ADDRESS_CSI_CONTROL |
0726             MASK_CSI_MODE |
0727             MASK_TXHSMD |
0728             ((lanes == 4) ? MASK_NOL_4 :
0729              (lanes == 3) ? MASK_NOL_3 :
0730              (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
0731 
0732     i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
0733             MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
0734             MASK_WCER | MASK_INER);
0735 
0736     i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
0737             MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
0738 
0739     i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
0740             MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
0741 }
0742 
0743 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
0744 {
0745     struct tc358743_state *state = to_state(sd);
0746     struct tc358743_platform_data *pdata = &state->pdata;
0747 
0748     /* Default settings from REF_02, sheet "Source HDMI"
0749      * and custom settings as platform data */
0750     i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
0751     i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
0752             SET_FREQ_RANGE_MODE_CYCLES(1));
0753     i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
0754             (pdata->hdmi_phy_auto_reset_tmds_detected ?
0755              MASK_PHY_AUTO_RST2 : 0) |
0756             (pdata->hdmi_phy_auto_reset_tmds_in_range ?
0757              MASK_PHY_AUTO_RST3 : 0) |
0758             (pdata->hdmi_phy_auto_reset_tmds_valid ?
0759              MASK_PHY_AUTO_RST4 : 0));
0760     i2c_wr8(sd, PHY_BIAS, 0x40);
0761     i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
0762     i2c_wr8(sd, AVM_CTL, 45);
0763     i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
0764             pdata->hdmi_detection_delay << 4);
0765     i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
0766             (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
0767              MASK_H_PI_RST : 0) |
0768             (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
0769              MASK_V_PI_RST : 0));
0770     i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
0771 }
0772 
0773 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
0774 {
0775     struct tc358743_state *state = to_state(sd);
0776 
0777     /* Default settings from REF_02, sheet "Source HDMI" */
0778     i2c_wr8(sd, FORCE_MUTE, 0x00);
0779     i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
0780             MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
0781             MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
0782     i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
0783     i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
0784     i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
0785     i2c_wr8(sd, FS_MUTE, 0x00);
0786     i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
0787     i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
0788     i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
0789     i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
0790     i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
0791     i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
0792 
0793     mutex_lock(&state->confctl_mutex);
0794     i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
0795             MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
0796     mutex_unlock(&state->confctl_mutex);
0797 }
0798 
0799 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
0800 {
0801     /* Default settings from REF_02, sheet "Source HDMI" */
0802     i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
0803             MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
0804             MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
0805             MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
0806     i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
0807     i2c_wr8(sd, NO_PKT_CLR, 0x53);
0808     i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
0809     i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
0810     i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
0811 }
0812 
0813 static void tc358743_initial_setup(struct v4l2_subdev *sd)
0814 {
0815     struct tc358743_state *state = to_state(sd);
0816     struct tc358743_platform_data *pdata = &state->pdata;
0817 
0818     /*
0819      * IR is not supported by this driver.
0820      * CEC is only enabled if needed.
0821      */
0822     i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
0823                      (MASK_IRRST | MASK_CECRST));
0824 
0825     tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
0826 #ifdef CONFIG_VIDEO_TC358743_CEC
0827     tc358743_reset(sd, MASK_CECRST);
0828 #endif
0829     tc358743_sleep_mode(sd, false);
0830 
0831     i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
0832 
0833     tc358743_set_ref_clk(sd);
0834 
0835     i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
0836             pdata->ddc5v_delay & MASK_DDC5V_MODE);
0837     i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
0838 
0839     tc358743_set_hdmi_phy(sd);
0840     tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
0841     tc358743_set_hdmi_audio(sd);
0842     tc358743_set_hdmi_info_frame_mode(sd);
0843 
0844     /* All CE and IT formats are detected as RGB full range in DVI mode */
0845     i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
0846 
0847     i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
0848             MASK_VOUTCOLORMODE_AUTO);
0849     i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
0850 }
0851 
0852 /* --------------- CEC --------------- */
0853 
0854 #ifdef CONFIG_VIDEO_TC358743_CEC
0855 static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable)
0856 {
0857     struct tc358743_state *state = adap->priv;
0858     struct v4l2_subdev *sd = &state->sd;
0859 
0860     i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
0861     i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
0862     i2c_wr32(sd, CECEN, enable);
0863     if (enable)
0864         i2c_wr32(sd, CECREN, MASK_CECREN);
0865     return 0;
0866 }
0867 
0868 static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap,
0869                         bool enable)
0870 {
0871     struct tc358743_state *state = adap->priv;
0872     struct v4l2_subdev *sd = &state->sd;
0873     u32 reg;
0874 
0875     reg = i2c_rd32(sd, CECRCTL1);
0876     if (enable)
0877         reg |= MASK_CECOTH;
0878     else
0879         reg &= ~MASK_CECOTH;
0880     i2c_wr32(sd, CECRCTL1, reg);
0881     return 0;
0882 }
0883 
0884 static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
0885 {
0886     struct tc358743_state *state = adap->priv;
0887     struct v4l2_subdev *sd = &state->sd;
0888     unsigned int la = 0;
0889 
0890     if (log_addr != CEC_LOG_ADDR_INVALID) {
0891         la = i2c_rd32(sd, CECADD);
0892         la |= 1 << log_addr;
0893     }
0894     i2c_wr32(sd, CECADD, la);
0895     return 0;
0896 }
0897 
0898 static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
0899                    u32 signal_free_time, struct cec_msg *msg)
0900 {
0901     struct tc358743_state *state = adap->priv;
0902     struct v4l2_subdev *sd = &state->sd;
0903     unsigned int i;
0904 
0905     i2c_wr32(sd, CECTCTL,
0906          (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) |
0907          (signal_free_time - 1));
0908     for (i = 0; i < msg->len; i++)
0909         i2c_wr32(sd, CECTBUF1 + i * 4,
0910             msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0));
0911     i2c_wr32(sd, CECTEN, MASK_CECTEN);
0912     return 0;
0913 }
0914 
0915 static const struct cec_adap_ops tc358743_cec_adap_ops = {
0916     .adap_enable = tc358743_cec_adap_enable,
0917     .adap_log_addr = tc358743_cec_adap_log_addr,
0918     .adap_transmit = tc358743_cec_adap_transmit,
0919     .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable,
0920 };
0921 
0922 static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus,
0923                  bool *handled)
0924 {
0925     struct tc358743_state *state = to_state(sd);
0926     unsigned int cec_rxint, cec_txint;
0927     unsigned int clr = 0;
0928 
0929     cec_rxint = i2c_rd32(sd, CECRSTAT);
0930     cec_txint = i2c_rd32(sd, CECTSTAT);
0931 
0932     if (intstatus & MASK_CEC_RINT)
0933         clr |= MASK_CECRICLR;
0934     if (intstatus & MASK_CEC_TINT)
0935         clr |= MASK_CECTICLR;
0936     i2c_wr32(sd, CECICLR, clr);
0937 
0938     if ((intstatus & MASK_CEC_TINT) && cec_txint) {
0939         if (cec_txint & MASK_CECTIEND)
0940             cec_transmit_attempt_done(state->cec_adap,
0941                           CEC_TX_STATUS_OK);
0942         else if (cec_txint & MASK_CECTIAL)
0943             cec_transmit_attempt_done(state->cec_adap,
0944                           CEC_TX_STATUS_ARB_LOST);
0945         else if (cec_txint & MASK_CECTIACK)
0946             cec_transmit_attempt_done(state->cec_adap,
0947                           CEC_TX_STATUS_NACK);
0948         else if (cec_txint & MASK_CECTIUR) {
0949             /*
0950              * Not sure when this bit is set. Treat
0951              * it as an error for now.
0952              */
0953             cec_transmit_attempt_done(state->cec_adap,
0954                           CEC_TX_STATUS_ERROR);
0955         }
0956         if (handled)
0957             *handled = true;
0958     }
0959     if ((intstatus & MASK_CEC_RINT) &&
0960         (cec_rxint & MASK_CECRIEND)) {
0961         struct cec_msg msg = {};
0962         unsigned int i;
0963         unsigned int v;
0964 
0965         v = i2c_rd32(sd, CECRCTR);
0966         msg.len = v & 0x1f;
0967         for (i = 0; i < msg.len; i++) {
0968             v = i2c_rd32(sd, CECRBUF1 + i * 4);
0969             msg.msg[i] = v & 0xff;
0970         }
0971         cec_received_msg(state->cec_adap, &msg);
0972         if (handled)
0973             *handled = true;
0974     }
0975     i2c_wr16(sd, INTSTATUS,
0976          intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
0977 }
0978 
0979 #endif
0980 
0981 /* --------------- IRQ --------------- */
0982 
0983 static void tc358743_format_change(struct v4l2_subdev *sd)
0984 {
0985     struct tc358743_state *state = to_state(sd);
0986     struct v4l2_dv_timings timings;
0987     const struct v4l2_event tc358743_ev_fmt = {
0988         .type = V4L2_EVENT_SOURCE_CHANGE,
0989         .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
0990     };
0991 
0992     if (tc358743_get_detected_timings(sd, &timings)) {
0993         enable_stream(sd, false);
0994 
0995         v4l2_dbg(1, debug, sd, "%s: No signal\n",
0996                 __func__);
0997     } else {
0998         if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
0999             enable_stream(sd, false);
1000 
1001         if (debug)
1002             v4l2_print_dv_timings(sd->name,
1003                     "tc358743_format_change: New format: ",
1004                     &timings, false);
1005     }
1006 
1007     if (sd->devnode)
1008         v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
1009 }
1010 
1011 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
1012 {
1013     u16 i;
1014 
1015     /* clear interrupt status registers */
1016     for (i = SYS_INT; i <= KEY_INT; i++)
1017         i2c_wr8(sd, i, 0xff);
1018 
1019     i2c_wr16(sd, INTSTATUS, 0xffff);
1020 }
1021 
1022 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
1023         bool cable_connected)
1024 {
1025     v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1026             cable_connected);
1027 
1028     if (cable_connected) {
1029         i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
1030                     MASK_M_HDMI_DET) & 0xff);
1031         i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
1032         i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
1033                     MASK_M_AF_UNLOCK) & 0xff);
1034         i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
1035         i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
1036     } else {
1037         i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
1038         i2c_wr8(sd, CLK_INTM, 0xff);
1039         i2c_wr8(sd, CBIT_INTM, 0xff);
1040         i2c_wr8(sd, AUDIO_INTM, 0xff);
1041         i2c_wr8(sd, MISC_INTM, 0xff);
1042     }
1043 }
1044 
1045 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1046         bool *handled)
1047 {
1048     u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1049     u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1050 
1051     i2c_wr8(sd, AUDIO_INT, audio_int);
1052 
1053     v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1054 
1055     tc358743_s_ctrl_audio_sampling_rate(sd);
1056     tc358743_s_ctrl_audio_present(sd);
1057 }
1058 
1059 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
1060 {
1061     v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
1062 
1063     i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
1064 }
1065 
1066 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1067         bool *handled)
1068 {
1069     u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1070     u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1071 
1072     i2c_wr8(sd, MISC_INT, misc_int);
1073 
1074     v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1075 
1076     if (misc_int & MASK_I_SYNC_CHG) {
1077         /* Reset the HDMI PHY to try to trigger proper lock on the
1078          * incoming video format. Erase BKSV to prevent that old keys
1079          * are used when a new source is connected. */
1080         if (no_sync(sd) || no_signal(sd)) {
1081             tc358743_reset_phy(sd);
1082             tc358743_erase_bksv(sd);
1083         }
1084 
1085         tc358743_format_change(sd);
1086 
1087         misc_int &= ~MASK_I_SYNC_CHG;
1088         if (handled)
1089             *handled = true;
1090     }
1091 
1092     if (misc_int) {
1093         v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1094                 __func__, misc_int);
1095     }
1096 }
1097 
1098 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1099         bool *handled)
1100 {
1101     u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1102     u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1103 
1104     i2c_wr8(sd, CBIT_INT, cbit_int);
1105 
1106     v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1107 
1108     if (cbit_int & MASK_I_CBIT_FS) {
1109 
1110         v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1111                 __func__);
1112         tc358743_s_ctrl_audio_sampling_rate(sd);
1113 
1114         cbit_int &= ~MASK_I_CBIT_FS;
1115         if (handled)
1116             *handled = true;
1117     }
1118 
1119     if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
1120 
1121         v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1122                 __func__);
1123         tc358743_s_ctrl_audio_present(sd);
1124 
1125         cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
1126         if (handled)
1127             *handled = true;
1128     }
1129 
1130     if (cbit_int) {
1131         v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1132                 __func__, cbit_int);
1133     }
1134 }
1135 
1136 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1137 {
1138     u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1139     u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1140 
1141     /* Bit 7 and bit 6 are set even when they are masked */
1142     i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1143 
1144     v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1145 
1146     if (clk_int & (MASK_I_IN_DE_CHG)) {
1147 
1148         v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1149                 __func__);
1150 
1151         /* If the source switch to a new resolution with the same pixel
1152          * frequency as the existing (e.g. 1080p25 -> 720p50), the
1153          * I_SYNC_CHG interrupt is not always triggered, while the
1154          * I_IN_DE_CHG interrupt seems to work fine. Format change
1155          * notifications are only sent when the signal is stable to
1156          * reduce the number of notifications. */
1157         if (!no_signal(sd) && !no_sync(sd))
1158             tc358743_format_change(sd);
1159 
1160         clk_int &= ~(MASK_I_IN_DE_CHG);
1161         if (handled)
1162             *handled = true;
1163     }
1164 
1165     if (clk_int) {
1166         v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1167                 __func__, clk_int);
1168     }
1169 }
1170 
1171 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1172 {
1173     struct tc358743_state *state = to_state(sd);
1174     u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1175     u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1176 
1177     i2c_wr8(sd, SYS_INT, sys_int);
1178 
1179     v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1180 
1181     if (sys_int & MASK_I_DDC) {
1182         bool tx_5v = tx_5v_power_present(sd);
1183 
1184         v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1185                 __func__, tx_5v ?  "yes" : "no");
1186 
1187         if (tx_5v) {
1188             tc358743_enable_edid(sd);
1189         } else {
1190             tc358743_enable_interrupts(sd, false);
1191             tc358743_disable_edid(sd);
1192             memset(&state->timings, 0, sizeof(state->timings));
1193             tc358743_erase_bksv(sd);
1194             tc358743_update_controls(sd);
1195         }
1196 
1197         sys_int &= ~MASK_I_DDC;
1198         if (handled)
1199             *handled = true;
1200     }
1201 
1202     if (sys_int & MASK_I_DVI) {
1203         v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1204                 __func__);
1205 
1206         /* Reset the HDMI PHY to try to trigger proper lock on the
1207          * incoming video format. Erase BKSV to prevent that old keys
1208          * are used when a new source is connected. */
1209         if (no_sync(sd) || no_signal(sd)) {
1210             tc358743_reset_phy(sd);
1211             tc358743_erase_bksv(sd);
1212         }
1213 
1214         sys_int &= ~MASK_I_DVI;
1215         if (handled)
1216             *handled = true;
1217     }
1218 
1219     if (sys_int & MASK_I_HDMI) {
1220         v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1221                 __func__);
1222 
1223         /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1224         i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1225 
1226         sys_int &= ~MASK_I_HDMI;
1227         if (handled)
1228             *handled = true;
1229     }
1230 
1231     if (sys_int) {
1232         v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1233                 __func__, sys_int);
1234     }
1235 }
1236 
1237 /* --------------- CORE OPS --------------- */
1238 
1239 static int tc358743_log_status(struct v4l2_subdev *sd)
1240 {
1241     struct tc358743_state *state = to_state(sd);
1242     struct v4l2_dv_timings timings;
1243     uint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);
1244     uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1245     u8 vi_status3 =  i2c_rd8(sd, VI_STATUS3);
1246     const int deep_color_mode[4] = { 8, 10, 12, 16 };
1247     static const char * const input_color_space[] = {
1248         "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)",
1249         "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1250         "NA(10)", "NA(11)", "NA(12)", "opYCC 601"};
1251 
1252     v4l2_info(sd, "-----Chip status-----\n");
1253     v4l2_info(sd, "Chip ID: 0x%02x\n",
1254             (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1255     v4l2_info(sd, "Chip revision: 0x%02x\n",
1256             i2c_rd16(sd, CHIPID) & MASK_REVID);
1257     v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1258             !!(sysctl & MASK_IRRST),
1259             !!(sysctl & MASK_CECRST),
1260             !!(sysctl & MASK_CTXRST),
1261             !!(sysctl & MASK_HDMIRST));
1262     v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1263     v4l2_info(sd, "Cable detected (+5V power): %s\n",
1264             hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1265     v4l2_info(sd, "DDC lines enabled: %s\n",
1266             (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1267             "yes" : "no");
1268     v4l2_info(sd, "Hotplug enabled: %s\n",
1269             (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1270             "yes" : "no");
1271     v4l2_info(sd, "CEC enabled: %s\n",
1272             (i2c_rd16(sd, CECEN) & MASK_CECEN) ?  "yes" : "no");
1273     v4l2_info(sd, "-----Signal status-----\n");
1274     v4l2_info(sd, "TMDS signal detected: %s\n",
1275             hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1276     v4l2_info(sd, "Stable sync signal: %s\n",
1277             hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1278     v4l2_info(sd, "PHY PLL locked: %s\n",
1279             hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1280     v4l2_info(sd, "PHY DE detected: %s\n",
1281             hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1282 
1283     if (tc358743_get_detected_timings(sd, &timings)) {
1284         v4l2_info(sd, "No video detected\n");
1285     } else {
1286         v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1287                 true);
1288     }
1289     v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1290             true);
1291 
1292     v4l2_info(sd, "-----CSI-TX status-----\n");
1293     v4l2_info(sd, "Lanes needed: %d\n",
1294             tc358743_num_csi_lanes_needed(sd));
1295     v4l2_info(sd, "Lanes in use: %d\n",
1296             state->csi_lanes_in_use);
1297     v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1298             (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1299             "yes" : "no");
1300     v4l2_info(sd, "Transmit mode: %s\n",
1301             (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1302             "yes" : "no");
1303     v4l2_info(sd, "Receive mode: %s\n",
1304             (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1305             "yes" : "no");
1306     v4l2_info(sd, "Stopped: %s\n",
1307             (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1308             "yes" : "no");
1309     v4l2_info(sd, "Color space: %s\n",
1310             state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1311             "YCbCr 422 16-bit" :
1312             state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1313             "RGB 888 24-bit" : "Unsupported");
1314 
1315     v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1316     v4l2_info(sd, "HDCP encrypted content: %s\n",
1317             hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1318     v4l2_info(sd, "Input color space: %s %s range\n",
1319             input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1320             (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1321     if (!is_hdmi(sd))
1322         return 0;
1323     v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1324             "off");
1325     v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1326             deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1327                 MASK_S_DEEPCOLOR) >> 2]);
1328     print_avi_infoframe(sd);
1329 
1330     return 0;
1331 }
1332 
1333 #ifdef CONFIG_VIDEO_ADV_DEBUG
1334 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1335 {
1336     v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1337     v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1338     v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1339     v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1340     v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1341     v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1342     v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1343     v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1344     v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1345     v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1346     v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1347     v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1348     v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1349     v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1350     v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1351     v4l2_info(sd, "0x9300-      : Reserved\n");
1352 }
1353 
1354 static int tc358743_get_reg_size(u16 address)
1355 {
1356     /* REF_01 p. 66-72 */
1357     if (address <= 0x00ff)
1358         return 2;
1359     else if ((address >= 0x0100) && (address <= 0x06FF))
1360         return 4;
1361     else if ((address >= 0x0700) && (address <= 0x84ff))
1362         return 2;
1363     else
1364         return 1;
1365 }
1366 
1367 static int tc358743_g_register(struct v4l2_subdev *sd,
1368                    struct v4l2_dbg_register *reg)
1369 {
1370     if (reg->reg > 0xffff) {
1371         tc358743_print_register_map(sd);
1372         return -EINVAL;
1373     }
1374 
1375     reg->size = tc358743_get_reg_size(reg->reg);
1376 
1377     reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1378 
1379     return 0;
1380 }
1381 
1382 static int tc358743_s_register(struct v4l2_subdev *sd,
1383                    const struct v4l2_dbg_register *reg)
1384 {
1385     if (reg->reg > 0xffff) {
1386         tc358743_print_register_map(sd);
1387         return -EINVAL;
1388     }
1389 
1390     /* It should not be possible for the user to enable HDCP with a simple
1391      * v4l2-dbg command.
1392      *
1393      * DO NOT REMOVE THIS unless all other issues with HDCP have been
1394      * resolved.
1395      */
1396     if (reg->reg == HDCP_MODE ||
1397         reg->reg == HDCP_REG1 ||
1398         reg->reg == HDCP_REG2 ||
1399         reg->reg == HDCP_REG3 ||
1400         reg->reg == BCAPS)
1401         return 0;
1402 
1403     i2c_wrreg(sd, (u16)reg->reg, reg->val,
1404             tc358743_get_reg_size(reg->reg));
1405 
1406     return 0;
1407 }
1408 #endif
1409 
1410 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1411 {
1412     u16 intstatus = i2c_rd16(sd, INTSTATUS);
1413 
1414     v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1415 
1416     if (intstatus & MASK_HDMI_INT) {
1417         u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1418         u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1419 
1420         if (hdmi_int0 & MASK_I_MISC)
1421             tc358743_hdmi_misc_int_handler(sd, handled);
1422         if (hdmi_int1 & MASK_I_CBIT)
1423             tc358743_hdmi_cbit_int_handler(sd, handled);
1424         if (hdmi_int1 & MASK_I_CLK)
1425             tc358743_hdmi_clk_int_handler(sd, handled);
1426         if (hdmi_int1 & MASK_I_SYS)
1427             tc358743_hdmi_sys_int_handler(sd, handled);
1428         if (hdmi_int1 & MASK_I_AUD)
1429             tc358743_hdmi_audio_int_handler(sd, handled);
1430 
1431         i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1432         intstatus &= ~MASK_HDMI_INT;
1433     }
1434 
1435 #ifdef CONFIG_VIDEO_TC358743_CEC
1436     if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) {
1437         tc358743_cec_handler(sd, intstatus, handled);
1438         i2c_wr16(sd, INTSTATUS,
1439              intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
1440         intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT);
1441     }
1442 #endif
1443 
1444     if (intstatus & MASK_CSI_INT) {
1445         u32 csi_int = i2c_rd32(sd, CSI_INT);
1446 
1447         if (csi_int & MASK_INTER)
1448             tc358743_csi_err_int_handler(sd, handled);
1449 
1450         i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1451     }
1452 
1453     intstatus = i2c_rd16(sd, INTSTATUS);
1454     if (intstatus) {
1455         v4l2_dbg(1, debug, sd,
1456                 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1457                 __func__, intstatus);
1458     }
1459 
1460     return 0;
1461 }
1462 
1463 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1464 {
1465     struct tc358743_state *state = dev_id;
1466     bool handled = false;
1467 
1468     tc358743_isr(&state->sd, 0, &handled);
1469 
1470     return handled ? IRQ_HANDLED : IRQ_NONE;
1471 }
1472 
1473 static void tc358743_irq_poll_timer(struct timer_list *t)
1474 {
1475     struct tc358743_state *state = from_timer(state, t, timer);
1476     unsigned int msecs;
1477 
1478     schedule_work(&state->work_i2c_poll);
1479     /*
1480      * If CEC is present, then we need to poll more frequently,
1481      * otherwise we will miss CEC messages.
1482      */
1483     msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
1484     mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
1485 }
1486 
1487 static void tc358743_work_i2c_poll(struct work_struct *work)
1488 {
1489     struct tc358743_state *state = container_of(work,
1490             struct tc358743_state, work_i2c_poll);
1491     bool handled;
1492 
1493     tc358743_isr(&state->sd, 0, &handled);
1494 }
1495 
1496 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1497                     struct v4l2_event_subscription *sub)
1498 {
1499     switch (sub->type) {
1500     case V4L2_EVENT_SOURCE_CHANGE:
1501         return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1502     case V4L2_EVENT_CTRL:
1503         return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1504     default:
1505         return -EINVAL;
1506     }
1507 }
1508 
1509 /* --------------- VIDEO OPS --------------- */
1510 
1511 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1512 {
1513     *status = 0;
1514     *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1515     *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1516 
1517     v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1518 
1519     return 0;
1520 }
1521 
1522 static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1523                  struct v4l2_dv_timings *timings)
1524 {
1525     struct tc358743_state *state = to_state(sd);
1526 
1527     if (!timings)
1528         return -EINVAL;
1529 
1530     if (debug)
1531         v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1532                 timings, false);
1533 
1534     if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1535         v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1536         return 0;
1537     }
1538 
1539     if (!v4l2_valid_dv_timings(timings,
1540                 &tc358743_timings_cap, NULL, NULL)) {
1541         v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1542         return -ERANGE;
1543     }
1544 
1545     state->timings = *timings;
1546 
1547     enable_stream(sd, false);
1548     tc358743_set_pll(sd);
1549     tc358743_set_csi(sd);
1550 
1551     return 0;
1552 }
1553 
1554 static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1555                  struct v4l2_dv_timings *timings)
1556 {
1557     struct tc358743_state *state = to_state(sd);
1558 
1559     *timings = state->timings;
1560 
1561     return 0;
1562 }
1563 
1564 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1565                     struct v4l2_enum_dv_timings *timings)
1566 {
1567     if (timings->pad != 0)
1568         return -EINVAL;
1569 
1570     return v4l2_enum_dv_timings_cap(timings,
1571             &tc358743_timings_cap, NULL, NULL);
1572 }
1573 
1574 static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1575         struct v4l2_dv_timings *timings)
1576 {
1577     int ret;
1578 
1579     ret = tc358743_get_detected_timings(sd, timings);
1580     if (ret)
1581         return ret;
1582 
1583     if (debug)
1584         v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1585                 timings, false);
1586 
1587     if (!v4l2_valid_dv_timings(timings,
1588                 &tc358743_timings_cap, NULL, NULL)) {
1589         v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1590         return -ERANGE;
1591     }
1592 
1593     return 0;
1594 }
1595 
1596 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1597         struct v4l2_dv_timings_cap *cap)
1598 {
1599     if (cap->pad != 0)
1600         return -EINVAL;
1601 
1602     *cap = tc358743_timings_cap;
1603 
1604     return 0;
1605 }
1606 
1607 static int tc358743_get_mbus_config(struct v4l2_subdev *sd,
1608                     unsigned int pad,
1609                     struct v4l2_mbus_config *cfg)
1610 {
1611     struct tc358743_state *state = to_state(sd);
1612 
1613     cfg->type = V4L2_MBUS_CSI2_DPHY;
1614 
1615     /* Support for non-continuous CSI-2 clock is missing in the driver */
1616     cfg->bus.mipi_csi2.flags = 0;
1617     cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use;
1618 
1619     return 0;
1620 }
1621 
1622 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1623 {
1624     enable_stream(sd, enable);
1625     if (!enable) {
1626         /* Put all lanes in LP-11 state (STOPSTATE) */
1627         tc358743_set_csi(sd);
1628     }
1629 
1630     return 0;
1631 }
1632 
1633 /* --------------- PAD OPS --------------- */
1634 
1635 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
1636         struct v4l2_subdev_state *sd_state,
1637         struct v4l2_subdev_mbus_code_enum *code)
1638 {
1639     switch (code->index) {
1640     case 0:
1641         code->code = MEDIA_BUS_FMT_RGB888_1X24;
1642         break;
1643     case 1:
1644         code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1645         break;
1646     default:
1647         return -EINVAL;
1648     }
1649     return 0;
1650 }
1651 
1652 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1653         struct v4l2_subdev_state *sd_state,
1654         struct v4l2_subdev_format *format)
1655 {
1656     struct tc358743_state *state = to_state(sd);
1657     u8 vi_rep = i2c_rd8(sd, VI_REP);
1658 
1659     if (format->pad != 0)
1660         return -EINVAL;
1661 
1662     format->format.code = state->mbus_fmt_code;
1663     format->format.width = state->timings.bt.width;
1664     format->format.height = state->timings.bt.height;
1665     format->format.field = V4L2_FIELD_NONE;
1666 
1667     switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1668     case MASK_VOUT_COLOR_RGB_FULL:
1669     case MASK_VOUT_COLOR_RGB_LIMITED:
1670         format->format.colorspace = V4L2_COLORSPACE_SRGB;
1671         break;
1672     case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1673     case MASK_VOUT_COLOR_601_YCBCR_FULL:
1674         format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1675         break;
1676     case MASK_VOUT_COLOR_709_YCBCR_FULL:
1677     case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1678         format->format.colorspace = V4L2_COLORSPACE_REC709;
1679         break;
1680     default:
1681         format->format.colorspace = 0;
1682         break;
1683     }
1684 
1685     return 0;
1686 }
1687 
1688 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1689         struct v4l2_subdev_state *sd_state,
1690         struct v4l2_subdev_format *format)
1691 {
1692     struct tc358743_state *state = to_state(sd);
1693 
1694     u32 code = format->format.code; /* is overwritten by get_fmt */
1695     int ret = tc358743_get_fmt(sd, sd_state, format);
1696 
1697     format->format.code = code;
1698 
1699     if (ret)
1700         return ret;
1701 
1702     switch (code) {
1703     case MEDIA_BUS_FMT_RGB888_1X24:
1704     case MEDIA_BUS_FMT_UYVY8_1X16:
1705         break;
1706     default:
1707         return -EINVAL;
1708     }
1709 
1710     if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1711         return 0;
1712 
1713     state->mbus_fmt_code = format->format.code;
1714 
1715     enable_stream(sd, false);
1716     tc358743_set_pll(sd);
1717     tc358743_set_csi(sd);
1718     tc358743_set_csi_color_space(sd);
1719 
1720     return 0;
1721 }
1722 
1723 static int tc358743_g_edid(struct v4l2_subdev *sd,
1724         struct v4l2_subdev_edid *edid)
1725 {
1726     struct tc358743_state *state = to_state(sd);
1727 
1728     memset(edid->reserved, 0, sizeof(edid->reserved));
1729 
1730     if (edid->pad != 0)
1731         return -EINVAL;
1732 
1733     if (edid->start_block == 0 && edid->blocks == 0) {
1734         edid->blocks = state->edid_blocks_written;
1735         return 0;
1736     }
1737 
1738     if (state->edid_blocks_written == 0)
1739         return -ENODATA;
1740 
1741     if (edid->start_block >= state->edid_blocks_written ||
1742             edid->blocks == 0)
1743         return -EINVAL;
1744 
1745     if (edid->start_block + edid->blocks > state->edid_blocks_written)
1746         edid->blocks = state->edid_blocks_written - edid->start_block;
1747 
1748     i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1749             edid->blocks * EDID_BLOCK_SIZE);
1750 
1751     return 0;
1752 }
1753 
1754 static int tc358743_s_edid(struct v4l2_subdev *sd,
1755                 struct v4l2_subdev_edid *edid)
1756 {
1757     struct tc358743_state *state = to_state(sd);
1758     u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1759     u16 pa;
1760     int err;
1761     int i;
1762 
1763     v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1764          __func__, edid->pad, edid->start_block, edid->blocks);
1765 
1766     memset(edid->reserved, 0, sizeof(edid->reserved));
1767 
1768     if (edid->pad != 0)
1769         return -EINVAL;
1770 
1771     if (edid->start_block != 0)
1772         return -EINVAL;
1773 
1774     if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1775         edid->blocks = EDID_NUM_BLOCKS_MAX;
1776         return -E2BIG;
1777     }
1778     pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL);
1779     err = v4l2_phys_addr_validate(pa, &pa, NULL);
1780     if (err)
1781         return err;
1782 
1783     cec_phys_addr_invalidate(state->cec_adap);
1784 
1785     tc358743_disable_edid(sd);
1786 
1787     i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1788     i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1789 
1790     if (edid->blocks == 0) {
1791         state->edid_blocks_written = 0;
1792         return 0;
1793     }
1794 
1795     for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1796         i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1797 
1798     state->edid_blocks_written = edid->blocks;
1799 
1800     cec_s_phys_addr(state->cec_adap, pa, false);
1801 
1802     if (tx_5v_power_present(sd))
1803         tc358743_enable_edid(sd);
1804 
1805     return 0;
1806 }
1807 
1808 /* -------------------------------------------------------------------------- */
1809 
1810 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1811     .log_status = tc358743_log_status,
1812 #ifdef CONFIG_VIDEO_ADV_DEBUG
1813     .g_register = tc358743_g_register,
1814     .s_register = tc358743_s_register,
1815 #endif
1816     .interrupt_service_routine = tc358743_isr,
1817     .subscribe_event = tc358743_subscribe_event,
1818     .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1819 };
1820 
1821 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1822     .g_input_status = tc358743_g_input_status,
1823     .s_dv_timings = tc358743_s_dv_timings,
1824     .g_dv_timings = tc358743_g_dv_timings,
1825     .query_dv_timings = tc358743_query_dv_timings,
1826     .s_stream = tc358743_s_stream,
1827 };
1828 
1829 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1830     .enum_mbus_code = tc358743_enum_mbus_code,
1831     .set_fmt = tc358743_set_fmt,
1832     .get_fmt = tc358743_get_fmt,
1833     .get_edid = tc358743_g_edid,
1834     .set_edid = tc358743_s_edid,
1835     .enum_dv_timings = tc358743_enum_dv_timings,
1836     .dv_timings_cap = tc358743_dv_timings_cap,
1837     .get_mbus_config = tc358743_get_mbus_config,
1838 };
1839 
1840 static const struct v4l2_subdev_ops tc358743_ops = {
1841     .core = &tc358743_core_ops,
1842     .video = &tc358743_video_ops,
1843     .pad = &tc358743_pad_ops,
1844 };
1845 
1846 /* --------------- CUSTOM CTRLS --------------- */
1847 
1848 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1849     .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1850     .name = "Audio sampling rate",
1851     .type = V4L2_CTRL_TYPE_INTEGER,
1852     .min = 0,
1853     .max = 768000,
1854     .step = 1,
1855     .def = 0,
1856     .flags = V4L2_CTRL_FLAG_READ_ONLY,
1857 };
1858 
1859 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1860     .id = TC358743_CID_AUDIO_PRESENT,
1861     .name = "Audio present",
1862     .type = V4L2_CTRL_TYPE_BOOLEAN,
1863     .min = 0,
1864     .max = 1,
1865     .step = 1,
1866     .def = 0,
1867     .flags = V4L2_CTRL_FLAG_READ_ONLY,
1868 };
1869 
1870 /* --------------- PROBE / REMOVE --------------- */
1871 
1872 #ifdef CONFIG_OF
1873 static void tc358743_gpio_reset(struct tc358743_state *state)
1874 {
1875     usleep_range(5000, 10000);
1876     gpiod_set_value(state->reset_gpio, 1);
1877     usleep_range(1000, 2000);
1878     gpiod_set_value(state->reset_gpio, 0);
1879     msleep(20);
1880 }
1881 
1882 static int tc358743_probe_of(struct tc358743_state *state)
1883 {
1884     struct device *dev = &state->i2c_client->dev;
1885     struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
1886     struct device_node *ep;
1887     struct clk *refclk;
1888     u32 bps_pr_lane;
1889     int ret;
1890 
1891     refclk = devm_clk_get(dev, "refclk");
1892     if (IS_ERR(refclk)) {
1893         if (PTR_ERR(refclk) != -EPROBE_DEFER)
1894             dev_err(dev, "failed to get refclk: %ld\n",
1895                 PTR_ERR(refclk));
1896         return PTR_ERR(refclk);
1897     }
1898 
1899     ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1900     if (!ep) {
1901         dev_err(dev, "missing endpoint node\n");
1902         return -EINVAL;
1903     }
1904 
1905     ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
1906     if (ret) {
1907         dev_err(dev, "failed to parse endpoint\n");
1908         goto put_node;
1909     }
1910 
1911     if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
1912         endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
1913         endpoint.nr_of_link_frequencies == 0) {
1914         dev_err(dev, "missing CSI-2 properties in endpoint\n");
1915         ret = -EINVAL;
1916         goto free_endpoint;
1917     }
1918 
1919     if (endpoint.bus.mipi_csi2.num_data_lanes > 4) {
1920         dev_err(dev, "invalid number of lanes\n");
1921         ret = -EINVAL;
1922         goto free_endpoint;
1923     }
1924 
1925     state->bus = endpoint.bus.mipi_csi2;
1926 
1927     ret = clk_prepare_enable(refclk);
1928     if (ret) {
1929         dev_err(dev, "Failed! to enable clock\n");
1930         goto free_endpoint;
1931     }
1932 
1933     state->pdata.refclk_hz = clk_get_rate(refclk);
1934     state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1935     state->pdata.enable_hdcp = false;
1936     /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1937     state->pdata.fifo_level = 16;
1938     /*
1939      * The PLL input clock is obtained by dividing refclk by pll_prd.
1940      * It must be between 6 MHz and 40 MHz, lower frequency is better.
1941      */
1942     switch (state->pdata.refclk_hz) {
1943     case 26000000:
1944     case 27000000:
1945     case 42000000:
1946         state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1947         break;
1948     default:
1949         dev_err(dev, "unsupported refclk rate: %u Hz\n",
1950             state->pdata.refclk_hz);
1951         goto disable_clk;
1952     }
1953 
1954     /*
1955      * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1956      * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1957      */
1958     bps_pr_lane = 2 * endpoint.link_frequencies[0];
1959     if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1960         dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1961         ret = -EINVAL;
1962         goto disable_clk;
1963     }
1964 
1965     /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1966     state->pdata.pll_fbd = bps_pr_lane /
1967                    state->pdata.refclk_hz * state->pdata.pll_prd;
1968 
1969     /*
1970      * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1971      * link frequency). In principle it should be possible to calculate
1972      * them based on link frequency and resolution.
1973      */
1974     if (bps_pr_lane != 594000000U)
1975         dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1976     state->pdata.lineinitcnt = 0xe80;
1977     state->pdata.lptxtimecnt = 0x003;
1978     /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1979     state->pdata.tclk_headercnt = 0x1403;
1980     state->pdata.tclk_trailcnt = 0x00;
1981     /* ths-preparecnt: 3, ths-zerocnt: 1 */
1982     state->pdata.ths_headercnt = 0x0103;
1983     state->pdata.twakeup = 0x4882;
1984     state->pdata.tclk_postcnt = 0x008;
1985     state->pdata.ths_trailcnt = 0x2;
1986     state->pdata.hstxvregcnt = 0;
1987 
1988     state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1989                             GPIOD_OUT_LOW);
1990     if (IS_ERR(state->reset_gpio)) {
1991         dev_err(dev, "failed to get reset gpio\n");
1992         ret = PTR_ERR(state->reset_gpio);
1993         goto disable_clk;
1994     }
1995 
1996     if (state->reset_gpio)
1997         tc358743_gpio_reset(state);
1998 
1999     ret = 0;
2000     goto free_endpoint;
2001 
2002 disable_clk:
2003     clk_disable_unprepare(refclk);
2004 free_endpoint:
2005     v4l2_fwnode_endpoint_free(&endpoint);
2006 put_node:
2007     of_node_put(ep);
2008     return ret;
2009 }
2010 #else
2011 static inline int tc358743_probe_of(struct tc358743_state *state)
2012 {
2013     return -ENODEV;
2014 }
2015 #endif
2016 
2017 static int tc358743_probe(struct i2c_client *client)
2018 {
2019     static struct v4l2_dv_timings default_timing =
2020         V4L2_DV_BT_CEA_640X480P59_94;
2021     struct tc358743_state *state;
2022     struct tc358743_platform_data *pdata = client->dev.platform_data;
2023     struct v4l2_subdev *sd;
2024     u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
2025     int err;
2026 
2027     if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2028         return -EIO;
2029     v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
2030         client->addr << 1, client->adapter->name);
2031 
2032     state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
2033             GFP_KERNEL);
2034     if (!state)
2035         return -ENOMEM;
2036 
2037     state->i2c_client = client;
2038 
2039     /* platform data */
2040     if (pdata) {
2041         state->pdata = *pdata;
2042         state->bus.flags = 0;
2043     } else {
2044         err = tc358743_probe_of(state);
2045         if (err == -ENODEV)
2046             v4l_err(client, "No platform data!\n");
2047         if (err)
2048             return err;
2049     }
2050 
2051     sd = &state->sd;
2052     v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
2053     sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2054 
2055     /* i2c access */
2056     if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
2057         v4l2_info(sd, "not a TC358743 on address 0x%x\n",
2058               client->addr << 1);
2059         return -ENODEV;
2060     }
2061 
2062     /* control handlers */
2063     v4l2_ctrl_handler_init(&state->hdl, 3);
2064 
2065     state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
2066             V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2067 
2068     /* custom controls */
2069     state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2070             &tc358743_ctrl_audio_sampling_rate, NULL);
2071 
2072     state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2073             &tc358743_ctrl_audio_present, NULL);
2074 
2075     sd->ctrl_handler = &state->hdl;
2076     if (state->hdl.error) {
2077         err = state->hdl.error;
2078         goto err_hdl;
2079     }
2080 
2081     if (tc358743_update_controls(sd)) {
2082         err = -ENODEV;
2083         goto err_hdl;
2084     }
2085 
2086     state->pad.flags = MEDIA_PAD_FL_SOURCE;
2087     sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
2088     err = media_entity_pads_init(&sd->entity, 1, &state->pad);
2089     if (err < 0)
2090         goto err_hdl;
2091 
2092     state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
2093 
2094     sd->dev = &client->dev;
2095     err = v4l2_async_register_subdev(sd);
2096     if (err < 0)
2097         goto err_hdl;
2098 
2099     mutex_init(&state->confctl_mutex);
2100 
2101     INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2102             tc358743_delayed_work_enable_hotplug);
2103 
2104 #ifdef CONFIG_VIDEO_TC358743_CEC
2105     state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops,
2106         state, dev_name(&client->dev),
2107         CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS);
2108     if (IS_ERR(state->cec_adap)) {
2109         err = PTR_ERR(state->cec_adap);
2110         goto err_hdl;
2111     }
2112     irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK;
2113 #endif
2114 
2115     tc358743_initial_setup(sd);
2116 
2117     tc358743_s_dv_timings(sd, &default_timing);
2118 
2119     tc358743_set_csi_color_space(sd);
2120 
2121     tc358743_init_interrupts(sd);
2122 
2123     if (state->i2c_client->irq) {
2124         err = devm_request_threaded_irq(&client->dev,
2125                         state->i2c_client->irq,
2126                         NULL, tc358743_irq_handler,
2127                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2128                         "tc358743", state);
2129         if (err)
2130             goto err_work_queues;
2131     } else {
2132         INIT_WORK(&state->work_i2c_poll,
2133               tc358743_work_i2c_poll);
2134         timer_setup(&state->timer, tc358743_irq_poll_timer, 0);
2135         state->timer.expires = jiffies +
2136                        msecs_to_jiffies(POLL_INTERVAL_MS);
2137         add_timer(&state->timer);
2138     }
2139 
2140     err = cec_register_adapter(state->cec_adap, &client->dev);
2141     if (err < 0) {
2142         pr_err("%s: failed to register the cec device\n", __func__);
2143         cec_delete_adapter(state->cec_adap);
2144         state->cec_adap = NULL;
2145         goto err_work_queues;
2146     }
2147 
2148     tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
2149     i2c_wr16(sd, INTMASK, ~irq_mask);
2150 
2151     err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
2152     if (err)
2153         goto err_work_queues;
2154 
2155     v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2156           client->addr << 1, client->adapter->name);
2157 
2158     return 0;
2159 
2160 err_work_queues:
2161     cec_unregister_adapter(state->cec_adap);
2162     if (!state->i2c_client->irq)
2163         flush_work(&state->work_i2c_poll);
2164     cancel_delayed_work(&state->delayed_work_enable_hotplug);
2165     mutex_destroy(&state->confctl_mutex);
2166 err_hdl:
2167     media_entity_cleanup(&sd->entity);
2168     v4l2_ctrl_handler_free(&state->hdl);
2169     return err;
2170 }
2171 
2172 static int tc358743_remove(struct i2c_client *client)
2173 {
2174     struct v4l2_subdev *sd = i2c_get_clientdata(client);
2175     struct tc358743_state *state = to_state(sd);
2176 
2177     if (!state->i2c_client->irq) {
2178         del_timer_sync(&state->timer);
2179         flush_work(&state->work_i2c_poll);
2180     }
2181     cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2182     cec_unregister_adapter(state->cec_adap);
2183     v4l2_async_unregister_subdev(sd);
2184     v4l2_device_unregister_subdev(sd);
2185     mutex_destroy(&state->confctl_mutex);
2186     media_entity_cleanup(&sd->entity);
2187     v4l2_ctrl_handler_free(&state->hdl);
2188 
2189     return 0;
2190 }
2191 
2192 static const struct i2c_device_id tc358743_id[] = {
2193     {"tc358743", 0},
2194     {}
2195 };
2196 
2197 MODULE_DEVICE_TABLE(i2c, tc358743_id);
2198 
2199 #if IS_ENABLED(CONFIG_OF)
2200 static const struct of_device_id tc358743_of_match[] = {
2201     { .compatible = "toshiba,tc358743" },
2202     {},
2203 };
2204 MODULE_DEVICE_TABLE(of, tc358743_of_match);
2205 #endif
2206 
2207 static struct i2c_driver tc358743_driver = {
2208     .driver = {
2209         .name = "tc358743",
2210         .of_match_table = of_match_ptr(tc358743_of_match),
2211     },
2212     .probe_new = tc358743_probe,
2213     .remove = tc358743_remove,
2214     .id_table = tc358743_id,
2215 };
2216 
2217 module_i2c_driver(tc358743_driver);
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