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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for ST MIPID02 CSI-2 to PARALLEL bridge
0004  *
0005  * Copyright (C) STMicroelectronics SA 2019
0006  * Authors: Mickael Guene <mickael.guene@st.com>
0007  *          for STMicroelectronics.
0008  *
0009  *
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/gpio/consumer.h>
0015 #include <linux/i2c.h>
0016 #include <linux/module.h>
0017 #include <linux/of_graph.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <media/v4l2-async.h>
0020 #include <media/v4l2-ctrls.h>
0021 #include <media/v4l2-device.h>
0022 #include <media/v4l2-fwnode.h>
0023 #include <media/v4l2-subdev.h>
0024 
0025 #define MIPID02_CLK_LANE_WR_REG1            0x01
0026 #define MIPID02_CLK_LANE_REG1               0x02
0027 #define MIPID02_CLK_LANE_REG3               0x04
0028 #define MIPID02_DATA_LANE0_REG1             0x05
0029 #define MIPID02_DATA_LANE0_REG2             0x06
0030 #define MIPID02_DATA_LANE1_REG1             0x09
0031 #define MIPID02_DATA_LANE1_REG2             0x0a
0032 #define MIPID02_MODE_REG1               0x14
0033 #define MIPID02_MODE_REG2               0x15
0034 #define MIPID02_DATA_ID_RREG                0x17
0035 #define MIPID02_DATA_SELECTION_CTRL         0x19
0036 #define MIPID02_PIX_WIDTH_CTRL              0x1e
0037 #define MIPID02_PIX_WIDTH_CTRL_EMB          0x1f
0038 
0039 /* Bits definition for MIPID02_CLK_LANE_REG1 */
0040 #define CLK_ENABLE                  BIT(0)
0041 /* Bits definition for MIPID02_CLK_LANE_REG3 */
0042 #define CLK_MIPI_CSI                    BIT(1)
0043 /* Bits definition for MIPID02_DATA_LANE0_REG1 */
0044 #define DATA_ENABLE                 BIT(0)
0045 /* Bits definition for MIPID02_DATA_LANEx_REG2 */
0046 #define DATA_MIPI_CSI                   BIT(0)
0047 /* Bits definition for MIPID02_MODE_REG1 */
0048 #define MODE_DATA_SWAP                  BIT(2)
0049 #define MODE_NO_BYPASS                  BIT(6)
0050 /* Bits definition for MIPID02_MODE_REG2 */
0051 #define MODE_HSYNC_ACTIVE_HIGH              BIT(1)
0052 #define MODE_VSYNC_ACTIVE_HIGH              BIT(2)
0053 #define MODE_PCLK_SAMPLE_RISING             BIT(3)
0054 /* Bits definition for MIPID02_DATA_SELECTION_CTRL */
0055 #define SELECTION_MANUAL_DATA               BIT(2)
0056 #define SELECTION_MANUAL_WIDTH              BIT(3)
0057 
0058 static const u32 mipid02_supported_fmt_codes[] = {
0059     MEDIA_BUS_FMT_SBGGR8_1X8, MEDIA_BUS_FMT_SGBRG8_1X8,
0060     MEDIA_BUS_FMT_SGRBG8_1X8, MEDIA_BUS_FMT_SRGGB8_1X8,
0061     MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10,
0062     MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10,
0063     MEDIA_BUS_FMT_SBGGR12_1X12, MEDIA_BUS_FMT_SGBRG12_1X12,
0064     MEDIA_BUS_FMT_SGRBG12_1X12, MEDIA_BUS_FMT_SRGGB12_1X12,
0065     MEDIA_BUS_FMT_YUYV8_1X16, MEDIA_BUS_FMT_YVYU8_1X16,
0066     MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_VYUY8_1X16,
0067     MEDIA_BUS_FMT_RGB565_1X16, MEDIA_BUS_FMT_BGR888_1X24,
0068     MEDIA_BUS_FMT_RGB565_2X8_LE, MEDIA_BUS_FMT_RGB565_2X8_BE,
0069     MEDIA_BUS_FMT_YUYV8_2X8, MEDIA_BUS_FMT_YVYU8_2X8,
0070     MEDIA_BUS_FMT_UYVY8_2X8, MEDIA_BUS_FMT_VYUY8_2X8,
0071     MEDIA_BUS_FMT_JPEG_1X8
0072 };
0073 
0074 /* regulator supplies */
0075 static const char * const mipid02_supply_name[] = {
0076     "VDDE", /* 1.8V digital I/O supply */
0077     "VDDIN", /* 1V8 voltage regulator supply */
0078 };
0079 
0080 #define MIPID02_NUM_SUPPLIES        ARRAY_SIZE(mipid02_supply_name)
0081 
0082 #define MIPID02_SINK_0          0
0083 #define MIPID02_SINK_1          1
0084 #define MIPID02_SOURCE          2
0085 #define MIPID02_PAD_NB          3
0086 
0087 struct mipid02_dev {
0088     struct i2c_client *i2c_client;
0089     struct regulator_bulk_data supplies[MIPID02_NUM_SUPPLIES];
0090     struct v4l2_subdev sd;
0091     struct media_pad pad[MIPID02_PAD_NB];
0092     struct clk *xclk;
0093     struct gpio_desc *reset_gpio;
0094     /* endpoints info */
0095     struct v4l2_fwnode_endpoint rx;
0096     u64 link_frequency;
0097     struct v4l2_fwnode_endpoint tx;
0098     /* remote source */
0099     struct v4l2_async_notifier notifier;
0100     struct v4l2_subdev *s_subdev;
0101     /* registers */
0102     struct {
0103         u8 clk_lane_reg1;
0104         u8 data_lane0_reg1;
0105         u8 data_lane1_reg1;
0106         u8 mode_reg1;
0107         u8 mode_reg2;
0108         u8 data_selection_ctrl;
0109         u8 data_id_rreg;
0110         u8 pix_width_ctrl;
0111         u8 pix_width_ctrl_emb;
0112     } r;
0113     /* lock to protect all members below */
0114     struct mutex lock;
0115     bool streaming;
0116     struct v4l2_mbus_framefmt fmt;
0117 };
0118 
0119 static int bpp_from_code(__u32 code)
0120 {
0121     switch (code) {
0122     case MEDIA_BUS_FMT_SBGGR8_1X8:
0123     case MEDIA_BUS_FMT_SGBRG8_1X8:
0124     case MEDIA_BUS_FMT_SGRBG8_1X8:
0125     case MEDIA_BUS_FMT_SRGGB8_1X8:
0126         return 8;
0127     case MEDIA_BUS_FMT_SBGGR10_1X10:
0128     case MEDIA_BUS_FMT_SGBRG10_1X10:
0129     case MEDIA_BUS_FMT_SGRBG10_1X10:
0130     case MEDIA_BUS_FMT_SRGGB10_1X10:
0131         return 10;
0132     case MEDIA_BUS_FMT_SBGGR12_1X12:
0133     case MEDIA_BUS_FMT_SGBRG12_1X12:
0134     case MEDIA_BUS_FMT_SGRBG12_1X12:
0135     case MEDIA_BUS_FMT_SRGGB12_1X12:
0136         return 12;
0137     case MEDIA_BUS_FMT_YUYV8_1X16:
0138     case MEDIA_BUS_FMT_YVYU8_1X16:
0139     case MEDIA_BUS_FMT_UYVY8_1X16:
0140     case MEDIA_BUS_FMT_VYUY8_1X16:
0141     case MEDIA_BUS_FMT_RGB565_1X16:
0142     case MEDIA_BUS_FMT_YUYV8_2X8:
0143     case MEDIA_BUS_FMT_YVYU8_2X8:
0144     case MEDIA_BUS_FMT_UYVY8_2X8:
0145     case MEDIA_BUS_FMT_VYUY8_2X8:
0146     case MEDIA_BUS_FMT_RGB565_2X8_LE:
0147     case MEDIA_BUS_FMT_RGB565_2X8_BE:
0148         return 16;
0149     case MEDIA_BUS_FMT_BGR888_1X24:
0150         return 24;
0151     default:
0152         return 0;
0153     }
0154 }
0155 
0156 static u8 data_type_from_code(__u32 code)
0157 {
0158     switch (code) {
0159     case MEDIA_BUS_FMT_SBGGR8_1X8:
0160     case MEDIA_BUS_FMT_SGBRG8_1X8:
0161     case MEDIA_BUS_FMT_SGRBG8_1X8:
0162     case MEDIA_BUS_FMT_SRGGB8_1X8:
0163         return 0x2a;
0164     case MEDIA_BUS_FMT_SBGGR10_1X10:
0165     case MEDIA_BUS_FMT_SGBRG10_1X10:
0166     case MEDIA_BUS_FMT_SGRBG10_1X10:
0167     case MEDIA_BUS_FMT_SRGGB10_1X10:
0168         return 0x2b;
0169     case MEDIA_BUS_FMT_SBGGR12_1X12:
0170     case MEDIA_BUS_FMT_SGBRG12_1X12:
0171     case MEDIA_BUS_FMT_SGRBG12_1X12:
0172     case MEDIA_BUS_FMT_SRGGB12_1X12:
0173         return 0x2c;
0174     case MEDIA_BUS_FMT_YUYV8_1X16:
0175     case MEDIA_BUS_FMT_YVYU8_1X16:
0176     case MEDIA_BUS_FMT_UYVY8_1X16:
0177     case MEDIA_BUS_FMT_VYUY8_1X16:
0178     case MEDIA_BUS_FMT_YUYV8_2X8:
0179     case MEDIA_BUS_FMT_YVYU8_2X8:
0180     case MEDIA_BUS_FMT_UYVY8_2X8:
0181     case MEDIA_BUS_FMT_VYUY8_2X8:
0182         return 0x1e;
0183     case MEDIA_BUS_FMT_BGR888_1X24:
0184         return 0x24;
0185     case MEDIA_BUS_FMT_RGB565_1X16:
0186     case MEDIA_BUS_FMT_RGB565_2X8_LE:
0187     case MEDIA_BUS_FMT_RGB565_2X8_BE:
0188         return 0x22;
0189     default:
0190         return 0;
0191     }
0192 }
0193 
0194 static void init_format(struct v4l2_mbus_framefmt *fmt)
0195 {
0196     fmt->code = MEDIA_BUS_FMT_SBGGR8_1X8;
0197     fmt->field = V4L2_FIELD_NONE;
0198     fmt->colorspace = V4L2_COLORSPACE_SRGB;
0199     fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SRGB);
0200     fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
0201     fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SRGB);
0202     fmt->width = 640;
0203     fmt->height = 480;
0204 }
0205 
0206 static __u32 get_fmt_code(__u32 code)
0207 {
0208     unsigned int i;
0209 
0210     for (i = 0; i < ARRAY_SIZE(mipid02_supported_fmt_codes); i++) {
0211         if (code == mipid02_supported_fmt_codes[i])
0212             return code;
0213     }
0214 
0215     return mipid02_supported_fmt_codes[0];
0216 }
0217 
0218 static __u32 serial_to_parallel_code(__u32 serial)
0219 {
0220     if (serial == MEDIA_BUS_FMT_RGB565_1X16)
0221         return MEDIA_BUS_FMT_RGB565_2X8_LE;
0222     if (serial == MEDIA_BUS_FMT_YUYV8_1X16)
0223         return MEDIA_BUS_FMT_YUYV8_2X8;
0224     if (serial == MEDIA_BUS_FMT_YVYU8_1X16)
0225         return MEDIA_BUS_FMT_YVYU8_2X8;
0226     if (serial == MEDIA_BUS_FMT_UYVY8_1X16)
0227         return MEDIA_BUS_FMT_UYVY8_2X8;
0228     if (serial == MEDIA_BUS_FMT_VYUY8_1X16)
0229         return MEDIA_BUS_FMT_VYUY8_2X8;
0230     if (serial == MEDIA_BUS_FMT_BGR888_1X24)
0231         return MEDIA_BUS_FMT_BGR888_3X8;
0232 
0233     return serial;
0234 }
0235 
0236 static inline struct mipid02_dev *to_mipid02_dev(struct v4l2_subdev *sd)
0237 {
0238     return container_of(sd, struct mipid02_dev, sd);
0239 }
0240 
0241 static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val)
0242 {
0243     struct i2c_client *client = bridge->i2c_client;
0244     struct i2c_msg msg[2];
0245     u8 buf[2];
0246     int ret;
0247 
0248     buf[0] = reg >> 8;
0249     buf[1] = reg & 0xff;
0250 
0251     msg[0].addr = client->addr;
0252     msg[0].flags = client->flags;
0253     msg[0].buf = buf;
0254     msg[0].len = sizeof(buf);
0255 
0256     msg[1].addr = client->addr;
0257     msg[1].flags = client->flags | I2C_M_RD;
0258     msg[1].buf = val;
0259     msg[1].len = 1;
0260 
0261     ret = i2c_transfer(client->adapter, msg, 2);
0262     if (ret < 0) {
0263         dev_dbg(&client->dev, "%s: %x i2c_transfer, reg: %x => %d\n",
0264                 __func__, client->addr, reg, ret);
0265         return ret;
0266     }
0267 
0268     return 0;
0269 }
0270 
0271 static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val)
0272 {
0273     struct i2c_client *client = bridge->i2c_client;
0274     struct i2c_msg msg;
0275     u8 buf[3];
0276     int ret;
0277 
0278     buf[0] = reg >> 8;
0279     buf[1] = reg & 0xff;
0280     buf[2] = val;
0281 
0282     msg.addr = client->addr;
0283     msg.flags = client->flags;
0284     msg.buf = buf;
0285     msg.len = sizeof(buf);
0286 
0287     ret = i2c_transfer(client->adapter, &msg, 1);
0288     if (ret < 0) {
0289         dev_dbg(&client->dev, "%s: i2c_transfer, reg: %x => %d\n",
0290                 __func__, reg, ret);
0291         return ret;
0292     }
0293 
0294     return 0;
0295 }
0296 
0297 static int mipid02_get_regulators(struct mipid02_dev *bridge)
0298 {
0299     unsigned int i;
0300 
0301     for (i = 0; i < MIPID02_NUM_SUPPLIES; i++)
0302         bridge->supplies[i].supply = mipid02_supply_name[i];
0303 
0304     return devm_regulator_bulk_get(&bridge->i2c_client->dev,
0305                        MIPID02_NUM_SUPPLIES,
0306                        bridge->supplies);
0307 }
0308 
0309 static void mipid02_apply_reset(struct mipid02_dev *bridge)
0310 {
0311     gpiod_set_value_cansleep(bridge->reset_gpio, 0);
0312     usleep_range(5000, 10000);
0313     gpiod_set_value_cansleep(bridge->reset_gpio, 1);
0314     usleep_range(5000, 10000);
0315     gpiod_set_value_cansleep(bridge->reset_gpio, 0);
0316     usleep_range(5000, 10000);
0317 }
0318 
0319 static int mipid02_set_power_on(struct mipid02_dev *bridge)
0320 {
0321     struct i2c_client *client = bridge->i2c_client;
0322     int ret;
0323 
0324     ret = clk_prepare_enable(bridge->xclk);
0325     if (ret) {
0326         dev_err(&client->dev, "%s: failed to enable clock\n", __func__);
0327         return ret;
0328     }
0329 
0330     ret = regulator_bulk_enable(MIPID02_NUM_SUPPLIES,
0331                     bridge->supplies);
0332     if (ret) {
0333         dev_err(&client->dev, "%s: failed to enable regulators\n",
0334                 __func__);
0335         goto xclk_off;
0336     }
0337 
0338     if (bridge->reset_gpio) {
0339         dev_dbg(&client->dev, "apply reset");
0340         mipid02_apply_reset(bridge);
0341     } else {
0342         dev_dbg(&client->dev, "don't apply reset");
0343         usleep_range(5000, 10000);
0344     }
0345 
0346     return 0;
0347 
0348 xclk_off:
0349     clk_disable_unprepare(bridge->xclk);
0350     return ret;
0351 }
0352 
0353 static void mipid02_set_power_off(struct mipid02_dev *bridge)
0354 {
0355     regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies);
0356     clk_disable_unprepare(bridge->xclk);
0357 }
0358 
0359 static int mipid02_detect(struct mipid02_dev *bridge)
0360 {
0361     u8 reg;
0362 
0363     /*
0364      * There is no version registers. Just try to read register
0365      * MIPID02_CLK_LANE_WR_REG1.
0366      */
0367     return mipid02_read_reg(bridge, MIPID02_CLK_LANE_WR_REG1, &reg);
0368 }
0369 
0370 static u32 mipid02_get_link_freq_from_cid_link_freq(struct mipid02_dev *bridge,
0371                             struct v4l2_subdev *subdev)
0372 {
0373     struct v4l2_querymenu qm = {.id = V4L2_CID_LINK_FREQ, };
0374     struct v4l2_ctrl *ctrl;
0375     int ret;
0376 
0377     ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_LINK_FREQ);
0378     if (!ctrl)
0379         return 0;
0380     qm.index = v4l2_ctrl_g_ctrl(ctrl);
0381 
0382     ret = v4l2_querymenu(subdev->ctrl_handler, &qm);
0383     if (ret)
0384         return 0;
0385 
0386     return qm.value;
0387 }
0388 
0389 static u32 mipid02_get_link_freq_from_cid_pixel_rate(struct mipid02_dev *bridge,
0390                              struct v4l2_subdev *subdev)
0391 {
0392     struct v4l2_fwnode_endpoint *ep = &bridge->rx;
0393     struct v4l2_ctrl *ctrl;
0394     u32 pixel_clock;
0395     u32 bpp = bpp_from_code(bridge->fmt.code);
0396 
0397     ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
0398     if (!ctrl)
0399         return 0;
0400     pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
0401 
0402     return pixel_clock * bpp / (2 * ep->bus.mipi_csi2.num_data_lanes);
0403 }
0404 
0405 /*
0406  * We need to know link frequency to setup clk_lane_reg1 timings. Link frequency
0407  * will be computed using connected device V4L2_CID_PIXEL_RATE, bit per pixel
0408  * and number of lanes.
0409  */
0410 static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge)
0411 {
0412     struct i2c_client *client = bridge->i2c_client;
0413     struct v4l2_subdev *subdev = bridge->s_subdev;
0414     u32 link_freq;
0415 
0416     link_freq = mipid02_get_link_freq_from_cid_link_freq(bridge, subdev);
0417     if (!link_freq) {
0418         link_freq = mipid02_get_link_freq_from_cid_pixel_rate(bridge,
0419                                       subdev);
0420         if (!link_freq) {
0421             dev_err(&client->dev, "Failed to get link frequency");
0422             return -EINVAL;
0423         }
0424     }
0425 
0426     dev_dbg(&client->dev, "detect link_freq = %d Hz", link_freq);
0427     bridge->r.clk_lane_reg1 |= (2000000000 / link_freq) << 2;
0428 
0429     return 0;
0430 }
0431 
0432 static int mipid02_configure_clk_lane(struct mipid02_dev *bridge)
0433 {
0434     struct i2c_client *client = bridge->i2c_client;
0435     struct v4l2_fwnode_endpoint *ep = &bridge->rx;
0436     bool *polarities = ep->bus.mipi_csi2.lane_polarities;
0437 
0438     /* midid02 doesn't support clock lane remapping */
0439     if (ep->bus.mipi_csi2.clock_lane != 0) {
0440         dev_err(&client->dev, "clk lane must be map to lane 0\n");
0441         return -EINVAL;
0442     }
0443     bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
0444 
0445     return 0;
0446 }
0447 
0448 static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb,
0449                     bool are_lanes_swap, bool *polarities)
0450 {
0451     bool are_pin_swap = are_lanes_swap ? polarities[2] : polarities[1];
0452 
0453     if (nb == 1 && are_lanes_swap)
0454         return 0;
0455 
0456     /*
0457      * data lane 0 as pin swap polarity reversed compared to clock and
0458      * data lane 1
0459      */
0460     if (!are_pin_swap)
0461         bridge->r.data_lane0_reg1 = 1 << 1;
0462     bridge->r.data_lane0_reg1 |= DATA_ENABLE;
0463 
0464     return 0;
0465 }
0466 
0467 static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,
0468                     bool are_lanes_swap, bool *polarities)
0469 {
0470     bool are_pin_swap = are_lanes_swap ? polarities[1] : polarities[2];
0471 
0472     if (nb == 1 && !are_lanes_swap)
0473         return 0;
0474 
0475     if (are_pin_swap)
0476         bridge->r.data_lane1_reg1 = 1 << 1;
0477     bridge->r.data_lane1_reg1 |= DATA_ENABLE;
0478 
0479     return 0;
0480 }
0481 
0482 static int mipid02_configure_from_rx(struct mipid02_dev *bridge)
0483 {
0484     struct v4l2_fwnode_endpoint *ep = &bridge->rx;
0485     bool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2;
0486     bool *polarities = ep->bus.mipi_csi2.lane_polarities;
0487     int nb = ep->bus.mipi_csi2.num_data_lanes;
0488     int ret;
0489 
0490     ret = mipid02_configure_clk_lane(bridge);
0491     if (ret)
0492         return ret;
0493 
0494     ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,
0495                        polarities);
0496     if (ret)
0497         return ret;
0498 
0499     ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,
0500                        polarities);
0501     if (ret)
0502         return ret;
0503 
0504     bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;
0505     bridge->r.mode_reg1 |= (nb - 1) << 1;
0506 
0507     return mipid02_configure_from_rx_speed(bridge);
0508 }
0509 
0510 static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
0511 {
0512     struct v4l2_fwnode_endpoint *ep = &bridge->tx;
0513 
0514     bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH;
0515     bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width;
0516     bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width;
0517     if (ep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
0518         bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
0519     if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
0520         bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
0521     if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
0522         bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
0523 
0524     return 0;
0525 }
0526 
0527 static int mipid02_configure_from_code(struct mipid02_dev *bridge)
0528 {
0529     u8 data_type;
0530 
0531     bridge->r.data_id_rreg = 0;
0532 
0533     if (bridge->fmt.code != MEDIA_BUS_FMT_JPEG_1X8) {
0534         bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA;
0535 
0536         data_type = data_type_from_code(bridge->fmt.code);
0537         if (!data_type)
0538             return -EINVAL;
0539         bridge->r.data_id_rreg = data_type;
0540     }
0541 
0542     return 0;
0543 }
0544 
0545 static int mipid02_stream_disable(struct mipid02_dev *bridge)
0546 {
0547     struct i2c_client *client = bridge->i2c_client;
0548     int ret;
0549 
0550     /* Disable all lanes */
0551     ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1, 0);
0552     if (ret)
0553         goto error;
0554     ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1, 0);
0555     if (ret)
0556         goto error;
0557     ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1, 0);
0558     if (ret)
0559         goto error;
0560 error:
0561     if (ret)
0562         dev_err(&client->dev, "failed to stream off %d", ret);
0563 
0564     return ret;
0565 }
0566 
0567 static int mipid02_stream_enable(struct mipid02_dev *bridge)
0568 {
0569     struct i2c_client *client = bridge->i2c_client;
0570     int ret = -EINVAL;
0571 
0572     if (!bridge->s_subdev)
0573         goto error;
0574 
0575     memset(&bridge->r, 0, sizeof(bridge->r));
0576     /* build registers content */
0577     ret = mipid02_configure_from_rx(bridge);
0578     if (ret)
0579         goto error;
0580     ret = mipid02_configure_from_tx(bridge);
0581     if (ret)
0582         goto error;
0583     ret = mipid02_configure_from_code(bridge);
0584     if (ret)
0585         goto error;
0586 
0587     /* write mipi registers */
0588     ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1,
0589         bridge->r.clk_lane_reg1);
0590     if (ret)
0591         goto error;
0592     ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI);
0593     if (ret)
0594         goto error;
0595     ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1,
0596         bridge->r.data_lane0_reg1);
0597     if (ret)
0598         goto error;
0599     ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG2,
0600         DATA_MIPI_CSI);
0601     if (ret)
0602         goto error;
0603     ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1,
0604         bridge->r.data_lane1_reg1);
0605     if (ret)
0606         goto error;
0607     ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG2,
0608         DATA_MIPI_CSI);
0609     if (ret)
0610         goto error;
0611     ret = mipid02_write_reg(bridge, MIPID02_MODE_REG1,
0612         MODE_NO_BYPASS | bridge->r.mode_reg1);
0613     if (ret)
0614         goto error;
0615     ret = mipid02_write_reg(bridge, MIPID02_MODE_REG2,
0616         bridge->r.mode_reg2);
0617     if (ret)
0618         goto error;
0619     ret = mipid02_write_reg(bridge, MIPID02_DATA_ID_RREG,
0620         bridge->r.data_id_rreg);
0621     if (ret)
0622         goto error;
0623     ret = mipid02_write_reg(bridge, MIPID02_DATA_SELECTION_CTRL,
0624         bridge->r.data_selection_ctrl);
0625     if (ret)
0626         goto error;
0627     ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL,
0628         bridge->r.pix_width_ctrl);
0629     if (ret)
0630         goto error;
0631     ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL_EMB,
0632         bridge->r.pix_width_ctrl_emb);
0633     if (ret)
0634         goto error;
0635 
0636     return 0;
0637 
0638 error:
0639     dev_err(&client->dev, "failed to stream on %d", ret);
0640     mipid02_stream_disable(bridge);
0641 
0642     return ret;
0643 }
0644 
0645 static int mipid02_s_stream(struct v4l2_subdev *sd, int enable)
0646 {
0647     struct mipid02_dev *bridge = to_mipid02_dev(sd);
0648     struct i2c_client *client = bridge->i2c_client;
0649     int ret = 0;
0650 
0651     dev_dbg(&client->dev, "%s : requested %d / current = %d", __func__,
0652             enable, bridge->streaming);
0653     mutex_lock(&bridge->lock);
0654 
0655     if (bridge->streaming == enable)
0656         goto out;
0657 
0658     ret = enable ? mipid02_stream_enable(bridge) :
0659                mipid02_stream_disable(bridge);
0660     if (!ret)
0661         bridge->streaming = enable;
0662 
0663 out:
0664     dev_dbg(&client->dev, "%s current now = %d / %d", __func__,
0665             bridge->streaming, ret);
0666     mutex_unlock(&bridge->lock);
0667 
0668     return ret;
0669 }
0670 
0671 static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,
0672                  struct v4l2_subdev_state *sd_state,
0673                  struct v4l2_subdev_mbus_code_enum *code)
0674 {
0675     struct mipid02_dev *bridge = to_mipid02_dev(sd);
0676     int ret = 0;
0677 
0678     switch (code->pad) {
0679     case MIPID02_SINK_0:
0680         if (code->index >= ARRAY_SIZE(mipid02_supported_fmt_codes))
0681             ret = -EINVAL;
0682         else
0683             code->code = mipid02_supported_fmt_codes[code->index];
0684         break;
0685     case MIPID02_SOURCE:
0686         if (code->index == 0)
0687             code->code = serial_to_parallel_code(bridge->fmt.code);
0688         else
0689             ret = -EINVAL;
0690         break;
0691     default:
0692         ret = -EINVAL;
0693     }
0694 
0695     return ret;
0696 }
0697 
0698 static int mipid02_get_fmt(struct v4l2_subdev *sd,
0699                struct v4l2_subdev_state *sd_state,
0700                struct v4l2_subdev_format *format)
0701 {
0702     struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
0703     struct mipid02_dev *bridge = to_mipid02_dev(sd);
0704     struct i2c_client *client = bridge->i2c_client;
0705     struct v4l2_mbus_framefmt *fmt;
0706 
0707     dev_dbg(&client->dev, "%s probe %d", __func__, format->pad);
0708 
0709     if (format->pad >= MIPID02_PAD_NB)
0710         return -EINVAL;
0711     /* second CSI-2 pad not yet supported */
0712     if (format->pad == MIPID02_SINK_1)
0713         return -EINVAL;
0714 
0715     if (format->which == V4L2_SUBDEV_FORMAT_TRY)
0716         fmt = v4l2_subdev_get_try_format(&bridge->sd, sd_state,
0717                          format->pad);
0718     else
0719         fmt = &bridge->fmt;
0720 
0721     mutex_lock(&bridge->lock);
0722 
0723     *mbus_fmt = *fmt;
0724     /* code may need to be converted for source */
0725     if (format->pad == MIPID02_SOURCE)
0726         mbus_fmt->code = serial_to_parallel_code(mbus_fmt->code);
0727 
0728     mutex_unlock(&bridge->lock);
0729 
0730     return 0;
0731 }
0732 
0733 static void mipid02_set_fmt_source(struct v4l2_subdev *sd,
0734                    struct v4l2_subdev_state *sd_state,
0735                    struct v4l2_subdev_format *format)
0736 {
0737     struct mipid02_dev *bridge = to_mipid02_dev(sd);
0738 
0739     /* source pad mirror active sink pad */
0740     format->format = bridge->fmt;
0741     /* but code may need to be converted */
0742     format->format.code = serial_to_parallel_code(format->format.code);
0743 
0744     /* only apply format for V4L2_SUBDEV_FORMAT_TRY case */
0745     if (format->which != V4L2_SUBDEV_FORMAT_TRY)
0746         return;
0747 
0748     *v4l2_subdev_get_try_format(sd, sd_state, format->pad) = format->format;
0749 }
0750 
0751 static void mipid02_set_fmt_sink(struct v4l2_subdev *sd,
0752                  struct v4l2_subdev_state *sd_state,
0753                  struct v4l2_subdev_format *format)
0754 {
0755     struct mipid02_dev *bridge = to_mipid02_dev(sd);
0756     struct v4l2_mbus_framefmt *fmt;
0757 
0758     format->format.code = get_fmt_code(format->format.code);
0759 
0760     if (format->which == V4L2_SUBDEV_FORMAT_TRY)
0761         fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
0762     else
0763         fmt = &bridge->fmt;
0764 
0765     *fmt = format->format;
0766 }
0767 
0768 static int mipid02_set_fmt(struct v4l2_subdev *sd,
0769                struct v4l2_subdev_state *sd_state,
0770                struct v4l2_subdev_format *format)
0771 {
0772     struct mipid02_dev *bridge = to_mipid02_dev(sd);
0773     struct i2c_client *client = bridge->i2c_client;
0774     int ret = 0;
0775 
0776     dev_dbg(&client->dev, "%s for %d", __func__, format->pad);
0777 
0778     if (format->pad >= MIPID02_PAD_NB)
0779         return -EINVAL;
0780     /* second CSI-2 pad not yet supported */
0781     if (format->pad == MIPID02_SINK_1)
0782         return -EINVAL;
0783 
0784     mutex_lock(&bridge->lock);
0785 
0786     if (bridge->streaming) {
0787         ret = -EBUSY;
0788         goto error;
0789     }
0790 
0791     if (format->pad == MIPID02_SOURCE)
0792         mipid02_set_fmt_source(sd, sd_state, format);
0793     else
0794         mipid02_set_fmt_sink(sd, sd_state, format);
0795 
0796 error:
0797     mutex_unlock(&bridge->lock);
0798 
0799     return ret;
0800 }
0801 
0802 static const struct v4l2_subdev_video_ops mipid02_video_ops = {
0803     .s_stream = mipid02_s_stream,
0804 };
0805 
0806 static const struct v4l2_subdev_pad_ops mipid02_pad_ops = {
0807     .enum_mbus_code = mipid02_enum_mbus_code,
0808     .get_fmt = mipid02_get_fmt,
0809     .set_fmt = mipid02_set_fmt,
0810 };
0811 
0812 static const struct v4l2_subdev_ops mipid02_subdev_ops = {
0813     .video = &mipid02_video_ops,
0814     .pad = &mipid02_pad_ops,
0815 };
0816 
0817 static const struct media_entity_operations mipid02_subdev_entity_ops = {
0818     .link_validate = v4l2_subdev_link_validate,
0819 };
0820 
0821 static int mipid02_async_bound(struct v4l2_async_notifier *notifier,
0822                    struct v4l2_subdev *s_subdev,
0823                    struct v4l2_async_subdev *asd)
0824 {
0825     struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
0826     struct i2c_client *client = bridge->i2c_client;
0827     int source_pad;
0828     int ret;
0829 
0830     dev_dbg(&client->dev, "sensor_async_bound call %p", s_subdev);
0831 
0832     source_pad = media_entity_get_fwnode_pad(&s_subdev->entity,
0833                          s_subdev->fwnode,
0834                          MEDIA_PAD_FL_SOURCE);
0835     if (source_pad < 0) {
0836         dev_err(&client->dev, "Couldn't find output pad for subdev %s\n",
0837             s_subdev->name);
0838         return source_pad;
0839     }
0840 
0841     ret = media_create_pad_link(&s_subdev->entity, source_pad,
0842                     &bridge->sd.entity, 0,
0843                     MEDIA_LNK_FL_ENABLED |
0844                     MEDIA_LNK_FL_IMMUTABLE);
0845     if (ret) {
0846         dev_err(&client->dev, "Couldn't create media link %d", ret);
0847         return ret;
0848     }
0849 
0850     bridge->s_subdev = s_subdev;
0851 
0852     return 0;
0853 }
0854 
0855 static void mipid02_async_unbind(struct v4l2_async_notifier *notifier,
0856                  struct v4l2_subdev *s_subdev,
0857                  struct v4l2_async_subdev *asd)
0858 {
0859     struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
0860 
0861     bridge->s_subdev = NULL;
0862 }
0863 
0864 static const struct v4l2_async_notifier_operations mipid02_notifier_ops = {
0865     .bound      = mipid02_async_bound,
0866     .unbind     = mipid02_async_unbind,
0867 };
0868 
0869 static int mipid02_parse_rx_ep(struct mipid02_dev *bridge)
0870 {
0871     struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
0872     struct i2c_client *client = bridge->i2c_client;
0873     struct v4l2_async_subdev *asd;
0874     struct device_node *ep_node;
0875     int ret;
0876 
0877     /* parse rx (endpoint 0) */
0878     ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
0879                         0, 0);
0880     if (!ep_node) {
0881         dev_err(&client->dev, "unable to find port0 ep");
0882         ret = -EINVAL;
0883         goto error;
0884     }
0885 
0886     ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
0887     if (ret) {
0888         dev_err(&client->dev, "Could not parse v4l2 endpoint %d\n",
0889             ret);
0890         goto error_of_node_put;
0891     }
0892 
0893     /* do some sanity checks */
0894     if (ep.bus.mipi_csi2.num_data_lanes > 2) {
0895         dev_err(&client->dev, "max supported data lanes is 2 / got %d",
0896             ep.bus.mipi_csi2.num_data_lanes);
0897         ret = -EINVAL;
0898         goto error_of_node_put;
0899     }
0900 
0901     /* register it for later use */
0902     bridge->rx = ep;
0903 
0904     /* register async notifier so we get noticed when sensor is connected */
0905     v4l2_async_nf_init(&bridge->notifier);
0906     asd = v4l2_async_nf_add_fwnode_remote(&bridge->notifier,
0907                           of_fwnode_handle(ep_node),
0908                           struct v4l2_async_subdev);
0909     of_node_put(ep_node);
0910 
0911     if (IS_ERR(asd)) {
0912         dev_err(&client->dev, "fail to register asd to notifier %ld",
0913             PTR_ERR(asd));
0914         return PTR_ERR(asd);
0915     }
0916     bridge->notifier.ops = &mipid02_notifier_ops;
0917 
0918     ret = v4l2_async_subdev_nf_register(&bridge->sd, &bridge->notifier);
0919     if (ret)
0920         v4l2_async_nf_cleanup(&bridge->notifier);
0921 
0922     return ret;
0923 
0924 error_of_node_put:
0925     of_node_put(ep_node);
0926 error:
0927 
0928     return ret;
0929 }
0930 
0931 static int mipid02_parse_tx_ep(struct mipid02_dev *bridge)
0932 {
0933     struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_PARALLEL };
0934     struct i2c_client *client = bridge->i2c_client;
0935     struct device_node *ep_node;
0936     int ret;
0937 
0938     /* parse tx (endpoint 2) */
0939     ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
0940                         2, 0);
0941     if (!ep_node) {
0942         dev_err(&client->dev, "unable to find port1 ep");
0943         ret = -EINVAL;
0944         goto error;
0945     }
0946 
0947     ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
0948     if (ret) {
0949         dev_err(&client->dev, "Could not parse v4l2 endpoint\n");
0950         goto error_of_node_put;
0951     }
0952 
0953     of_node_put(ep_node);
0954     bridge->tx = ep;
0955 
0956     return 0;
0957 
0958 error_of_node_put:
0959     of_node_put(ep_node);
0960 error:
0961 
0962     return -EINVAL;
0963 }
0964 
0965 static int mipid02_probe(struct i2c_client *client)
0966 {
0967     struct device *dev = &client->dev;
0968     struct mipid02_dev *bridge;
0969     u32 clk_freq;
0970     int ret;
0971 
0972     bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
0973     if (!bridge)
0974         return -ENOMEM;
0975 
0976     init_format(&bridge->fmt);
0977 
0978     bridge->i2c_client = client;
0979     v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops);
0980 
0981     /* got and check clock */
0982     bridge->xclk = devm_clk_get(dev, "xclk");
0983     if (IS_ERR(bridge->xclk)) {
0984         dev_err(dev, "failed to get xclk\n");
0985         return PTR_ERR(bridge->xclk);
0986     }
0987 
0988     clk_freq = clk_get_rate(bridge->xclk);
0989     if (clk_freq < 6000000 || clk_freq > 27000000) {
0990         dev_err(dev, "xclk freq must be in 6-27 Mhz range. got %d Hz\n",
0991             clk_freq);
0992         return -EINVAL;
0993     }
0994 
0995     bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset",
0996                              GPIOD_OUT_HIGH);
0997 
0998     if (IS_ERR(bridge->reset_gpio)) {
0999         dev_err(dev, "failed to get reset GPIO\n");
1000         return PTR_ERR(bridge->reset_gpio);
1001     }
1002 
1003     ret = mipid02_get_regulators(bridge);
1004     if (ret) {
1005         dev_err(dev, "failed to get regulators %d", ret);
1006         return ret;
1007     }
1008 
1009     mutex_init(&bridge->lock);
1010     bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1011     bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1012     bridge->sd.entity.ops = &mipid02_subdev_entity_ops;
1013     bridge->pad[0].flags = MEDIA_PAD_FL_SINK;
1014     bridge->pad[1].flags = MEDIA_PAD_FL_SINK;
1015     bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE;
1016     ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB,
1017                      bridge->pad);
1018     if (ret) {
1019         dev_err(&client->dev, "pads init failed %d", ret);
1020         goto mutex_cleanup;
1021     }
1022 
1023     /* enable clock, power and reset device if available */
1024     ret = mipid02_set_power_on(bridge);
1025     if (ret)
1026         goto entity_cleanup;
1027 
1028     ret = mipid02_detect(bridge);
1029     if (ret) {
1030         dev_err(&client->dev, "failed to detect mipid02 %d", ret);
1031         goto power_off;
1032     }
1033 
1034     ret = mipid02_parse_tx_ep(bridge);
1035     if (ret) {
1036         dev_err(&client->dev, "failed to parse tx %d", ret);
1037         goto power_off;
1038     }
1039 
1040     ret = mipid02_parse_rx_ep(bridge);
1041     if (ret) {
1042         dev_err(&client->dev, "failed to parse rx %d", ret);
1043         goto power_off;
1044     }
1045 
1046     ret = v4l2_async_register_subdev(&bridge->sd);
1047     if (ret < 0) {
1048         dev_err(&client->dev, "v4l2_async_register_subdev failed %d",
1049                 ret);
1050         goto unregister_notifier;
1051     }
1052 
1053     dev_info(&client->dev, "mipid02 device probe successfully");
1054 
1055     return 0;
1056 
1057 unregister_notifier:
1058     v4l2_async_nf_unregister(&bridge->notifier);
1059     v4l2_async_nf_cleanup(&bridge->notifier);
1060 power_off:
1061     mipid02_set_power_off(bridge);
1062 entity_cleanup:
1063     media_entity_cleanup(&bridge->sd.entity);
1064 mutex_cleanup:
1065     mutex_destroy(&bridge->lock);
1066 
1067     return ret;
1068 }
1069 
1070 static int mipid02_remove(struct i2c_client *client)
1071 {
1072     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1073     struct mipid02_dev *bridge = to_mipid02_dev(sd);
1074 
1075     v4l2_async_nf_unregister(&bridge->notifier);
1076     v4l2_async_nf_cleanup(&bridge->notifier);
1077     v4l2_async_unregister_subdev(&bridge->sd);
1078     mipid02_set_power_off(bridge);
1079     media_entity_cleanup(&bridge->sd.entity);
1080     mutex_destroy(&bridge->lock);
1081 
1082     return 0;
1083 }
1084 
1085 static const struct of_device_id mipid02_dt_ids[] = {
1086     { .compatible = "st,st-mipid02" },
1087     { /* sentinel */ }
1088 };
1089 MODULE_DEVICE_TABLE(of, mipid02_dt_ids);
1090 
1091 static struct i2c_driver mipid02_i2c_driver = {
1092     .driver = {
1093         .name  = "st-mipid02",
1094         .of_match_table = mipid02_dt_ids,
1095     },
1096     .probe_new = mipid02_probe,
1097     .remove = mipid02_remove,
1098 };
1099 
1100 module_i2c_driver(mipid02_i2c_driver);
1101 
1102 MODULE_AUTHOR("Mickael Guene <mickael.guene@st.com>");
1103 MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver");
1104 MODULE_LICENSE("GPL v2");
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