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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
0004  *
0005  * Copyright (C) 2010 Samsung Electronics Co., Ltd
0006  * Author: Sylwester Nawrocki, s.nawrocki@samsung.com
0007  *
0008  * Based on original driver authored by Dongsoo Nathaniel Kim
0009  * and HeungJun Kim <riverful.kim@samsung.com>.
0010  *
0011  * Based on mt9v011 Micron Digital Image Sensor driver
0012  * Copyright (c) 2009 Mauro Carvalho Chehab
0013  */
0014 
0015 #include <linux/i2c.h>
0016 #include <linux/delay.h>
0017 #include <linux/slab.h>
0018 #include <linux/module.h>
0019 #include <media/v4l2-device.h>
0020 #include <media/v4l2-subdev.h>
0021 #include <media/v4l2-mediabus.h>
0022 #include <media/v4l2-ctrls.h>
0023 #include <media/i2c/sr030pc30.h>
0024 
0025 static int debug;
0026 module_param(debug, int, 0644);
0027 
0028 #define MODULE_NAME "SR030PC30"
0029 
0030 /*
0031  * Register offsets within a page
0032  * b15..b8 - page id, b7..b0 - register address
0033  */
0034 #define POWER_CTRL_REG      0x0001
0035 #define PAGEMODE_REG        0x03
0036 #define DEVICE_ID_REG       0x0004
0037 #define NOON010PC30_ID      0x86
0038 #define SR030PC30_ID        0x8C
0039 #define VDO_CTL1_REG        0x0010
0040 #define SUBSAMPL_NONE_VGA   0
0041 #define SUBSAMPL_QVGA       0x10
0042 #define SUBSAMPL_QQVGA      0x20
0043 #define VDO_CTL2_REG        0x0011
0044 #define SYNC_CTL_REG        0x0012
0045 #define WIN_ROWH_REG        0x0020
0046 #define WIN_ROWL_REG        0x0021
0047 #define WIN_COLH_REG        0x0022
0048 #define WIN_COLL_REG        0x0023
0049 #define WIN_HEIGHTH_REG     0x0024
0050 #define WIN_HEIGHTL_REG     0x0025
0051 #define WIN_WIDTHH_REG      0x0026
0052 #define WIN_WIDTHL_REG      0x0027
0053 #define HBLANKH_REG     0x0040
0054 #define HBLANKL_REG     0x0041
0055 #define VSYNCH_REG      0x0042
0056 #define VSYNCL_REG      0x0043
0057 /* page 10 */
0058 #define ISP_CTL_REG(n)      (0x1010 + (n))
0059 #define YOFS_REG        0x1040
0060 #define DARK_YOFS_REG       0x1041
0061 #define AG_ABRTH_REG        0x1050
0062 #define SAT_CTL_REG     0x1060
0063 #define BSAT_REG        0x1061
0064 #define RSAT_REG        0x1062
0065 #define AG_SAT_TH_REG       0x1063
0066 /* page 11 */
0067 #define ZLPF_CTRL_REG       0x1110
0068 #define ZLPF_CTRL2_REG      0x1112
0069 #define ZLPF_AGH_THR_REG    0x1121
0070 #define ZLPF_THR_REG        0x1160
0071 #define ZLPF_DYN_THR_REG    0x1160
0072 /* page 12 */
0073 #define YCLPF_CTL1_REG      0x1240
0074 #define YCLPF_CTL2_REG      0x1241
0075 #define YCLPF_THR_REG       0x1250
0076 #define BLPF_CTL_REG        0x1270
0077 #define BLPF_THR1_REG       0x1274
0078 #define BLPF_THR2_REG       0x1275
0079 /* page 14 - Lens Shading Compensation */
0080 #define LENS_CTRL_REG       0x1410
0081 #define LENS_XCEN_REG       0x1420
0082 #define LENS_YCEN_REG       0x1421
0083 #define LENS_R_COMP_REG     0x1422
0084 #define LENS_G_COMP_REG     0x1423
0085 #define LENS_B_COMP_REG     0x1424
0086 /* page 15 - Color correction */
0087 #define CMC_CTL_REG     0x1510
0088 #define CMC_OFSGH_REG       0x1514
0089 #define CMC_OFSGL_REG       0x1516
0090 #define CMC_SIGN_REG        0x1517
0091 /* Color correction coefficients */
0092 #define CMC_COEF_REG(n)     (0x1530 + (n))
0093 /* Color correction offset coefficients */
0094 #define CMC_OFS_REG(n)      (0x1540 + (n))
0095 /* page 16 - Gamma correction */
0096 #define GMA_CTL_REG     0x1610
0097 /* Gamma correction coefficients 0.14 */
0098 #define GMA_COEF_REG(n)     (0x1630 + (n))
0099 /* page 20 - Auto Exposure */
0100 #define AE_CTL1_REG     0x2010
0101 #define AE_CTL2_REG     0x2011
0102 #define AE_FRM_CTL_REG      0x2020
0103 #define AE_FINE_CTL_REG(n)  (0x2028 + (n))
0104 #define EXP_TIMEH_REG       0x2083
0105 #define EXP_TIMEM_REG       0x2084
0106 #define EXP_TIMEL_REG       0x2085
0107 #define EXP_MMINH_REG       0x2086
0108 #define EXP_MMINL_REG       0x2087
0109 #define EXP_MMAXH_REG       0x2088
0110 #define EXP_MMAXM_REG       0x2089
0111 #define EXP_MMAXL_REG       0x208A
0112 /* page 22 - Auto White Balance */
0113 #define AWB_CTL1_REG        0x2210
0114 #define AWB_ENABLE      0x80
0115 #define AWB_CTL2_REG        0x2211
0116 #define MWB_ENABLE      0x01
0117 /* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
0118 #define AWB_RGAIN_REG       0x2280
0119 #define AWB_GGAIN_REG       0x2281
0120 #define AWB_BGAIN_REG       0x2282
0121 #define AWB_RMAX_REG        0x2283
0122 #define AWB_RMIN_REG        0x2284
0123 #define AWB_BMAX_REG        0x2285
0124 #define AWB_BMIN_REG        0x2286
0125 /* R, B gain range in bright light conditions */
0126 #define AWB_RMAXB_REG       0x2287
0127 #define AWB_RMINB_REG       0x2288
0128 #define AWB_BMAXB_REG       0x2289
0129 #define AWB_BMINB_REG       0x228A
0130 /* manual white balance, when AWB_CTL2[0]=1 */
0131 #define MWB_RGAIN_REG       0x22B2
0132 #define MWB_BGAIN_REG       0x22B3
0133 /* the token to mark an array end */
0134 #define REG_TERM        0xFFFF
0135 
0136 /* Minimum and maximum exposure time in ms */
0137 #define EXPOS_MIN_MS        1
0138 #define EXPOS_MAX_MS        125
0139 
0140 struct sr030pc30_info {
0141     struct v4l2_subdev sd;
0142     struct v4l2_ctrl_handler hdl;
0143     const struct sr030pc30_platform_data *pdata;
0144     const struct sr030pc30_format *curr_fmt;
0145     const struct sr030pc30_frmsize *curr_win;
0146     unsigned int hflip:1;
0147     unsigned int vflip:1;
0148     unsigned int sleep:1;
0149     struct {
0150         /* auto whitebalance control cluster */
0151         struct v4l2_ctrl *awb;
0152         struct v4l2_ctrl *red;
0153         struct v4l2_ctrl *blue;
0154     };
0155     struct {
0156         /* auto exposure control cluster */
0157         struct v4l2_ctrl *autoexp;
0158         struct v4l2_ctrl *exp;
0159     };
0160     u8 i2c_reg_page;
0161 };
0162 
0163 struct sr030pc30_format {
0164     u32 code;
0165     enum v4l2_colorspace colorspace;
0166     u16 ispctl1_reg;
0167 };
0168 
0169 struct sr030pc30_frmsize {
0170     u16 width;
0171     u16 height;
0172     int vid_ctl1;
0173 };
0174 
0175 struct i2c_regval {
0176     u16 addr;
0177     u16 val;
0178 };
0179 
0180 /* supported resolutions */
0181 static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
0182     {
0183         .width      = 640,
0184         .height     = 480,
0185         .vid_ctl1   = SUBSAMPL_NONE_VGA,
0186     }, {
0187         .width      = 320,
0188         .height     = 240,
0189         .vid_ctl1   = SUBSAMPL_QVGA,
0190     }, {
0191         .width      = 160,
0192         .height     = 120,
0193         .vid_ctl1   = SUBSAMPL_QQVGA,
0194     },
0195 };
0196 
0197 /* supported pixel formats */
0198 static const struct sr030pc30_format sr030pc30_formats[] = {
0199     {
0200         .code       = MEDIA_BUS_FMT_YUYV8_2X8,
0201         .colorspace = V4L2_COLORSPACE_JPEG,
0202         .ispctl1_reg    = 0x03,
0203     }, {
0204         .code       = MEDIA_BUS_FMT_YVYU8_2X8,
0205         .colorspace = V4L2_COLORSPACE_JPEG,
0206         .ispctl1_reg    = 0x02,
0207     }, {
0208         .code       = MEDIA_BUS_FMT_VYUY8_2X8,
0209         .colorspace = V4L2_COLORSPACE_JPEG,
0210         .ispctl1_reg    = 0,
0211     }, {
0212         .code       = MEDIA_BUS_FMT_UYVY8_2X8,
0213         .colorspace = V4L2_COLORSPACE_JPEG,
0214         .ispctl1_reg    = 0x01,
0215     }, {
0216         .code       = MEDIA_BUS_FMT_RGB565_2X8_BE,
0217         .colorspace = V4L2_COLORSPACE_JPEG,
0218         .ispctl1_reg    = 0x40,
0219     },
0220 };
0221 
0222 static const struct i2c_regval sr030pc30_base_regs[] = {
0223     /* Window size and position within pixel matrix */
0224     { WIN_ROWH_REG,     0x00 }, { WIN_ROWL_REG,     0x06 },
0225     { WIN_COLH_REG,     0x00 }, { WIN_COLL_REG,     0x06 },
0226     { WIN_HEIGHTH_REG,  0x01 }, { WIN_HEIGHTL_REG,  0xE0 },
0227     { WIN_WIDTHH_REG,   0x02 }, { WIN_WIDTHL_REG,   0x80 },
0228     { HBLANKH_REG,      0x01 }, { HBLANKL_REG,      0x50 },
0229     { VSYNCH_REG,       0x00 }, { VSYNCL_REG,       0x14 },
0230     { SYNC_CTL_REG,     0 },
0231     /* Color corection and saturation */
0232     { ISP_CTL_REG(0),   0x30 }, { YOFS_REG,     0x80 },
0233     { DARK_YOFS_REG,    0x04 }, { AG_ABRTH_REG,     0x78 },
0234     { SAT_CTL_REG,      0x1F }, { BSAT_REG,     0x90 },
0235     { AG_SAT_TH_REG,    0xF0 }, { 0x1064,       0x80 },
0236     { CMC_CTL_REG,      0x03 }, { CMC_OFSGH_REG,    0x3C },
0237     { CMC_OFSGL_REG,    0x2C }, { CMC_SIGN_REG,     0x2F },
0238     { CMC_COEF_REG(0),  0xCB }, { CMC_OFS_REG(0),   0x87 },
0239     { CMC_COEF_REG(1),  0x61 }, { CMC_OFS_REG(1),   0x18 },
0240     { CMC_COEF_REG(2),  0x16 }, { CMC_OFS_REG(2),   0x91 },
0241     { CMC_COEF_REG(3),  0x23 }, { CMC_OFS_REG(3),   0x94 },
0242     { CMC_COEF_REG(4),  0xCE }, { CMC_OFS_REG(4),   0x9f },
0243     { CMC_COEF_REG(5),  0x2B }, { CMC_OFS_REG(5),   0x33 },
0244     { CMC_COEF_REG(6),  0x01 }, { CMC_OFS_REG(6),   0x00 },
0245     { CMC_COEF_REG(7),  0x34 }, { CMC_OFS_REG(7),   0x94 },
0246     { CMC_COEF_REG(8),  0x75 }, { CMC_OFS_REG(8),   0x14 },
0247     /* Color corection coefficients */
0248     { GMA_CTL_REG,      0x03 }, { GMA_COEF_REG(0),  0x00 },
0249     { GMA_COEF_REG(1),  0x19 }, { GMA_COEF_REG(2),  0x26 },
0250     { GMA_COEF_REG(3),  0x3B }, { GMA_COEF_REG(4),  0x5D },
0251     { GMA_COEF_REG(5),  0x79 }, { GMA_COEF_REG(6),  0x8E },
0252     { GMA_COEF_REG(7),  0x9F }, { GMA_COEF_REG(8),  0xAF },
0253     { GMA_COEF_REG(9),  0xBD }, { GMA_COEF_REG(10), 0xCA },
0254     { GMA_COEF_REG(11), 0xDD }, { GMA_COEF_REG(12), 0xEC },
0255     { GMA_COEF_REG(13), 0xF7 }, { GMA_COEF_REG(14), 0xFF },
0256     /* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
0257     { ZLPF_CTRL_REG,    0x99 }, { ZLPF_CTRL2_REG,   0x0E },
0258     { ZLPF_AGH_THR_REG, 0x29 }, { ZLPF_THR_REG,     0x0F },
0259     { ZLPF_DYN_THR_REG, 0x63 }, { YCLPF_CTL1_REG,   0x23 },
0260     { YCLPF_CTL2_REG,   0x3B }, { YCLPF_THR_REG,    0x05 },
0261     { BLPF_CTL_REG,     0x1D }, { BLPF_THR1_REG,    0x05 },
0262     { BLPF_THR2_REG,    0x04 },
0263     /* Automatic white balance */
0264     { AWB_CTL1_REG,     0xFB }, { AWB_CTL2_REG,     0x26 },
0265     { AWB_RMAX_REG,     0x54 }, { AWB_RMIN_REG,     0x2B },
0266     { AWB_BMAX_REG,     0x57 }, { AWB_BMIN_REG,     0x29 },
0267     { AWB_RMAXB_REG,    0x50 }, { AWB_RMINB_REG,    0x43 },
0268     { AWB_BMAXB_REG,    0x30 }, { AWB_BMINB_REG,    0x22 },
0269     /* Auto exposure */
0270     { AE_CTL1_REG,      0x8C }, { AE_CTL2_REG,      0x04 },
0271     { AE_FRM_CTL_REG,   0x01 }, { AE_FINE_CTL_REG(0),   0x3F },
0272     { AE_FINE_CTL_REG(1),   0xA3 }, { AE_FINE_CTL_REG(3),   0x34 },
0273     /* Lens shading compensation */
0274     { LENS_CTRL_REG,    0x01 }, { LENS_XCEN_REG,    0x80 },
0275     { LENS_YCEN_REG,    0x70 }, { LENS_R_COMP_REG,  0x53 },
0276     { LENS_G_COMP_REG,  0x40 }, { LENS_B_COMP_REG,  0x3e },
0277     { REG_TERM,     0 },
0278 };
0279 
0280 static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
0281 {
0282     return container_of(sd, struct sr030pc30_info, sd);
0283 }
0284 
0285 static inline int set_i2c_page(struct sr030pc30_info *info,
0286                    struct i2c_client *client, unsigned int reg)
0287 {
0288     int ret = 0;
0289     u32 page = reg >> 8 & 0xFF;
0290 
0291     if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
0292         ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
0293         if (!ret)
0294             info->i2c_reg_page = page;
0295     }
0296     return ret;
0297 }
0298 
0299 static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
0300 {
0301     struct i2c_client *client = v4l2_get_subdevdata(sd);
0302     struct sr030pc30_info *info = to_sr030pc30(sd);
0303 
0304     int ret = set_i2c_page(info, client, reg_addr);
0305     if (!ret)
0306         ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
0307     return ret;
0308 }
0309 
0310 static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
0311 {
0312     struct i2c_client *client = v4l2_get_subdevdata(sd);
0313     struct sr030pc30_info *info = to_sr030pc30(sd);
0314 
0315     int ret = set_i2c_page(info, client, reg_addr);
0316     if (!ret)
0317         ret = i2c_smbus_write_byte_data(
0318             client, reg_addr & 0xFF, val);
0319     return ret;
0320 }
0321 
0322 static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
0323                 const struct i2c_regval *msg)
0324 {
0325     while (msg->addr != REG_TERM) {
0326         int ret = cam_i2c_write(sd, msg->addr, msg->val);
0327         if (ret)
0328             return ret;
0329         msg++;
0330     }
0331     return 0;
0332 }
0333 
0334 /* Device reset and sleep mode control */
0335 static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
0336                      bool reset, bool sleep)
0337 {
0338     struct sr030pc30_info *info = to_sr030pc30(sd);
0339     u8 reg = sleep ? 0xF1 : 0xF0;
0340     int ret = 0;
0341 
0342     if (reset)
0343         ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
0344     if (!ret) {
0345         ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
0346         if (!ret) {
0347             info->sleep = sleep;
0348             if (reset)
0349                 info->i2c_reg_page = -1;
0350         }
0351     }
0352     return ret;
0353 }
0354 
0355 static int sr030pc30_set_flip(struct v4l2_subdev *sd)
0356 {
0357     struct sr030pc30_info *info = to_sr030pc30(sd);
0358 
0359     s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
0360     if (reg < 0)
0361         return reg;
0362 
0363     reg &= 0x7C;
0364     if (info->hflip)
0365         reg |= 0x01;
0366     if (info->vflip)
0367         reg |= 0x02;
0368     return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
0369 }
0370 
0371 /* Configure resolution, color format and image flip */
0372 static int sr030pc30_set_params(struct v4l2_subdev *sd)
0373 {
0374     struct sr030pc30_info *info = to_sr030pc30(sd);
0375     int ret;
0376 
0377     if (!info->curr_win)
0378         return -EINVAL;
0379 
0380     /* Configure the resolution through subsampling */
0381     ret = cam_i2c_write(sd, VDO_CTL1_REG,
0382                 info->curr_win->vid_ctl1);
0383 
0384     if (!ret && info->curr_fmt)
0385         ret = cam_i2c_write(sd, ISP_CTL_REG(0),
0386                 info->curr_fmt->ispctl1_reg);
0387     if (!ret)
0388         ret = sr030pc30_set_flip(sd);
0389 
0390     return ret;
0391 }
0392 
0393 /* Find nearest matching image pixel size. */
0394 static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
0395 {
0396     unsigned int min_err = ~0;
0397     int i = ARRAY_SIZE(sr030pc30_sizes);
0398     const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
0399                     *match = NULL;
0400     while (i--) {
0401         int err = abs(fsize->width - mf->width)
0402                 + abs(fsize->height - mf->height);
0403         if (err < min_err) {
0404             min_err = err;
0405             match = fsize;
0406         }
0407         fsize++;
0408     }
0409     if (match) {
0410         mf->width  = match->width;
0411         mf->height = match->height;
0412         return 0;
0413     }
0414     return -EINVAL;
0415 }
0416 
0417 static int sr030pc30_s_ctrl(struct v4l2_ctrl *ctrl)
0418 {
0419     struct sr030pc30_info *info =
0420         container_of(ctrl->handler, struct sr030pc30_info, hdl);
0421     struct v4l2_subdev *sd = &info->sd;
0422     int ret = 0;
0423 
0424     v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
0425              __func__, ctrl->id, ctrl->val);
0426 
0427     switch (ctrl->id) {
0428     case V4L2_CID_AUTO_WHITE_BALANCE:
0429         if (ctrl->is_new) {
0430             ret = cam_i2c_write(sd, AWB_CTL2_REG,
0431                     ctrl->val ? 0x2E : 0x2F);
0432             if (!ret)
0433                 ret = cam_i2c_write(sd, AWB_CTL1_REG,
0434                         ctrl->val ? 0xFB : 0x7B);
0435         }
0436         if (!ret && info->blue->is_new)
0437             ret = cam_i2c_write(sd, MWB_BGAIN_REG, info->blue->val);
0438         if (!ret && info->red->is_new)
0439             ret = cam_i2c_write(sd, MWB_RGAIN_REG, info->red->val);
0440         return ret;
0441 
0442     case V4L2_CID_EXPOSURE_AUTO:
0443         /* auto anti-flicker is also enabled here */
0444         if (ctrl->is_new)
0445             ret = cam_i2c_write(sd, AE_CTL1_REG,
0446                 ctrl->val == V4L2_EXPOSURE_AUTO ? 0xDC : 0x0C);
0447         if (info->exp->is_new) {
0448             unsigned long expos = info->exp->val;
0449 
0450             expos = expos * info->pdata->clk_rate / (8 * 1000);
0451 
0452             if (!ret)
0453                 ret = cam_i2c_write(sd, EXP_TIMEH_REG,
0454                         expos >> 16 & 0xFF);
0455             if (!ret)
0456                 ret = cam_i2c_write(sd, EXP_TIMEM_REG,
0457                         expos >> 8 & 0xFF);
0458             if (!ret)
0459                 ret = cam_i2c_write(sd, EXP_TIMEL_REG,
0460                         expos & 0xFF);
0461         }
0462         return ret;
0463     default:
0464         return -EINVAL;
0465     }
0466 
0467     return 0;
0468 }
0469 
0470 static int sr030pc30_enum_mbus_code(struct v4l2_subdev *sd,
0471         struct v4l2_subdev_state *sd_state,
0472         struct v4l2_subdev_mbus_code_enum *code)
0473 {
0474     if (!code || code->pad ||
0475         code->index >= ARRAY_SIZE(sr030pc30_formats))
0476         return -EINVAL;
0477 
0478     code->code = sr030pc30_formats[code->index].code;
0479     return 0;
0480 }
0481 
0482 static int sr030pc30_get_fmt(struct v4l2_subdev *sd,
0483         struct v4l2_subdev_state *sd_state,
0484         struct v4l2_subdev_format *format)
0485 {
0486     struct v4l2_mbus_framefmt *mf;
0487     struct sr030pc30_info *info = to_sr030pc30(sd);
0488 
0489     if (!format || format->pad)
0490         return -EINVAL;
0491 
0492     mf = &format->format;
0493 
0494     if (!info->curr_win || !info->curr_fmt)
0495         return -EINVAL;
0496 
0497     mf->width   = info->curr_win->width;
0498     mf->height  = info->curr_win->height;
0499     mf->code    = info->curr_fmt->code;
0500     mf->colorspace  = info->curr_fmt->colorspace;
0501     mf->field   = V4L2_FIELD_NONE;
0502 
0503     return 0;
0504 }
0505 
0506 /* Return nearest media bus frame format. */
0507 static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
0508                           struct v4l2_mbus_framefmt *mf)
0509 {
0510     int i;
0511 
0512     sr030pc30_try_frame_size(mf);
0513 
0514     for (i = 0; i < ARRAY_SIZE(sr030pc30_formats); i++) {
0515         if (mf->code == sr030pc30_formats[i].code)
0516             break;
0517     }
0518     if (i == ARRAY_SIZE(sr030pc30_formats))
0519         i = 0;
0520 
0521     mf->code = sr030pc30_formats[i].code;
0522 
0523     return &sr030pc30_formats[i];
0524 }
0525 
0526 /* Return nearest media bus frame format. */
0527 static int sr030pc30_set_fmt(struct v4l2_subdev *sd,
0528         struct v4l2_subdev_state *sd_state,
0529         struct v4l2_subdev_format *format)
0530 {
0531     struct sr030pc30_info *info = sd ? to_sr030pc30(sd) : NULL;
0532     const struct sr030pc30_format *fmt;
0533     struct v4l2_mbus_framefmt *mf;
0534 
0535     if (!sd || !format)
0536         return -EINVAL;
0537 
0538     mf = &format->format;
0539     if (format->pad)
0540         return -EINVAL;
0541 
0542     fmt = try_fmt(sd, mf);
0543     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
0544         sd_state->pads->try_fmt = *mf;
0545         return 0;
0546     }
0547 
0548     info->curr_fmt = fmt;
0549 
0550     return sr030pc30_set_params(sd);
0551 }
0552 
0553 static int sr030pc30_base_config(struct v4l2_subdev *sd)
0554 {
0555     struct sr030pc30_info *info = to_sr030pc30(sd);
0556     int ret;
0557     unsigned long expmin, expmax;
0558 
0559     ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
0560     if (!ret) {
0561         info->curr_fmt = &sr030pc30_formats[0];
0562         info->curr_win = &sr030pc30_sizes[0];
0563         ret = sr030pc30_set_params(sd);
0564     }
0565     if (!ret)
0566         ret = sr030pc30_pwr_ctrl(sd, false, false);
0567 
0568     if (ret)
0569         return ret;
0570 
0571     expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
0572     expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
0573 
0574     v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
0575          expmin, expmax);
0576 
0577     /* Setting up manual exposure time range */
0578     ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
0579     if (!ret)
0580         ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
0581     if (!ret)
0582         ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
0583     if (!ret)
0584         ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
0585     if (!ret)
0586         ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
0587 
0588     return ret;
0589 }
0590 
0591 static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
0592 {
0593     struct i2c_client *client = v4l2_get_subdevdata(sd);
0594     struct sr030pc30_info *info = to_sr030pc30(sd);
0595     const struct sr030pc30_platform_data *pdata = info->pdata;
0596     int ret;
0597 
0598     if (pdata == NULL) {
0599         WARN(1, "No platform data!\n");
0600         return -EINVAL;
0601     }
0602 
0603     /*
0604      * Put sensor into power sleep mode before switching off
0605      * power and disabling MCLK.
0606      */
0607     if (!on)
0608         sr030pc30_pwr_ctrl(sd, false, true);
0609 
0610     /* set_power controls sensor's power and clock */
0611     if (pdata->set_power) {
0612         ret = pdata->set_power(&client->dev, on);
0613         if (ret)
0614             return ret;
0615     }
0616 
0617     if (on) {
0618         ret = sr030pc30_base_config(sd);
0619     } else {
0620         ret = 0;
0621         info->curr_win = NULL;
0622         info->curr_fmt = NULL;
0623     }
0624 
0625     return ret;
0626 }
0627 
0628 static const struct v4l2_ctrl_ops sr030pc30_ctrl_ops = {
0629     .s_ctrl = sr030pc30_s_ctrl,
0630 };
0631 
0632 static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
0633     .s_power    = sr030pc30_s_power,
0634 };
0635 
0636 static const struct v4l2_subdev_pad_ops sr030pc30_pad_ops = {
0637     .enum_mbus_code = sr030pc30_enum_mbus_code,
0638     .get_fmt    = sr030pc30_get_fmt,
0639     .set_fmt    = sr030pc30_set_fmt,
0640 };
0641 
0642 static const struct v4l2_subdev_ops sr030pc30_ops = {
0643     .core   = &sr030pc30_core_ops,
0644     .pad    = &sr030pc30_pad_ops,
0645 };
0646 
0647 /*
0648  * Detect sensor type. Return 0 if SR030PC30 was detected
0649  * or -ENODEV otherwise.
0650  */
0651 static int sr030pc30_detect(struct i2c_client *client)
0652 {
0653     const struct sr030pc30_platform_data *pdata
0654         = client->dev.platform_data;
0655     int ret;
0656 
0657     /* Enable sensor's power and clock */
0658     if (pdata->set_power) {
0659         ret = pdata->set_power(&client->dev, 1);
0660         if (ret)
0661             return ret;
0662     }
0663 
0664     ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
0665 
0666     if (pdata->set_power)
0667         pdata->set_power(&client->dev, 0);
0668 
0669     if (ret < 0) {
0670         dev_err(&client->dev, "%s: I2C read failed\n", __func__);
0671         return ret;
0672     }
0673 
0674     return ret == SR030PC30_ID ? 0 : -ENODEV;
0675 }
0676 
0677 
0678 static int sr030pc30_probe(struct i2c_client *client,
0679                const struct i2c_device_id *id)
0680 {
0681     struct sr030pc30_info *info;
0682     struct v4l2_subdev *sd;
0683     struct v4l2_ctrl_handler *hdl;
0684     const struct sr030pc30_platform_data *pdata
0685         = client->dev.platform_data;
0686     int ret;
0687 
0688     if (!pdata) {
0689         dev_err(&client->dev, "No platform data!");
0690         return -EIO;
0691     }
0692 
0693     ret = sr030pc30_detect(client);
0694     if (ret)
0695         return ret;
0696 
0697     info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
0698     if (!info)
0699         return -ENOMEM;
0700 
0701     sd = &info->sd;
0702     info->pdata = client->dev.platform_data;
0703 
0704     v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
0705 
0706     hdl = &info->hdl;
0707     v4l2_ctrl_handler_init(hdl, 6);
0708     info->awb = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
0709             V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
0710     info->red = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
0711             V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
0712     info->blue = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
0713             V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
0714     info->autoexp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
0715             V4L2_CID_EXPOSURE_AUTO, 0, 1, 1, 1);
0716     info->exp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
0717             V4L2_CID_EXPOSURE, EXPOS_MIN_MS, EXPOS_MAX_MS, 1, 30);
0718     sd->ctrl_handler = hdl;
0719     if (hdl->error) {
0720         int err = hdl->error;
0721 
0722         v4l2_ctrl_handler_free(hdl);
0723         return err;
0724     }
0725     v4l2_ctrl_auto_cluster(3, &info->awb, 0, false);
0726     v4l2_ctrl_auto_cluster(2, &info->autoexp, V4L2_EXPOSURE_MANUAL, false);
0727     v4l2_ctrl_handler_setup(hdl);
0728 
0729     info->i2c_reg_page  = -1;
0730     info->hflip     = 1;
0731 
0732     return 0;
0733 }
0734 
0735 static int sr030pc30_remove(struct i2c_client *client)
0736 {
0737     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0738 
0739     v4l2_device_unregister_subdev(sd);
0740     v4l2_ctrl_handler_free(sd->ctrl_handler);
0741     return 0;
0742 }
0743 
0744 static const struct i2c_device_id sr030pc30_id[] = {
0745     { MODULE_NAME, 0 },
0746     { },
0747 };
0748 MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
0749 
0750 
0751 static struct i2c_driver sr030pc30_i2c_driver = {
0752     .driver = {
0753         .name = MODULE_NAME
0754     },
0755     .probe      = sr030pc30_probe,
0756     .remove     = sr030pc30_remove,
0757     .id_table   = sr030pc30_id,
0758 };
0759 
0760 module_i2c_driver(sr030pc30_i2c_driver);
0761 
0762 MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
0763 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
0764 MODULE_LICENSE("GPL");
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