Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * saa711x - Philips SAA711x video decoder register specifications
0004  *
0005  * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@kernel.org>
0006  */
0007 
0008 #define R_00_CHIP_VERSION                             0x00
0009 /* Video Decoder */
0010     /* Video Decoder - Frontend part */
0011 #define R_01_INC_DELAY                                0x01
0012 #define R_02_INPUT_CNTL_1                             0x02
0013 #define R_03_INPUT_CNTL_2                             0x03
0014 #define R_04_INPUT_CNTL_3                             0x04
0015 #define R_05_INPUT_CNTL_4                             0x05
0016     /* Video Decoder - Decoder part */
0017 #define R_06_H_SYNC_START                             0x06
0018 #define R_07_H_SYNC_STOP                              0x07
0019 #define R_08_SYNC_CNTL                                0x08
0020 #define R_09_LUMA_CNTL                                0x09
0021 #define R_0A_LUMA_BRIGHT_CNTL                         0x0a
0022 #define R_0B_LUMA_CONTRAST_CNTL                       0x0b
0023 #define R_0C_CHROMA_SAT_CNTL                          0x0c
0024 #define R_0D_CHROMA_HUE_CNTL                          0x0d
0025 #define R_0E_CHROMA_CNTL_1                            0x0e
0026 #define R_0F_CHROMA_GAIN_CNTL                         0x0f
0027 #define R_10_CHROMA_CNTL_2                            0x10
0028 #define R_11_MODE_DELAY_CNTL                          0x11
0029 #define R_12_RT_SIGNAL_CNTL                           0x12
0030 #define R_13_RT_X_PORT_OUT_CNTL                       0x13
0031 #define R_14_ANAL_ADC_COMPAT_CNTL                     0x14
0032 #define R_15_VGATE_START_FID_CHG                      0x15
0033 #define R_16_VGATE_STOP                               0x16
0034 #define R_17_MISC_VGATE_CONF_AND_MSB                  0x17
0035 #define R_18_RAW_DATA_GAIN_CNTL                       0x18
0036 #define R_19_RAW_DATA_OFF_CNTL                        0x19
0037 #define R_1A_COLOR_KILL_LVL_CNTL                      0x1a
0038 #define R_1B_MISC_TVVCRDET                            0x1b
0039 #define R_1C_ENHAN_COMB_CTRL1                         0x1c
0040 #define R_1D_ENHAN_COMB_CTRL2                         0x1d
0041 #define R_1E_STATUS_BYTE_1_VD_DEC                     0x1e
0042 #define R_1F_STATUS_BYTE_2_VD_DEC                     0x1f
0043 
0044 /* Component processing and interrupt masking part */
0045 #define R_23_INPUT_CNTL_5                             0x23
0046 #define R_24_INPUT_CNTL_6                             0x24
0047 #define R_25_INPUT_CNTL_7                             0x25
0048 #define R_29_COMP_DELAY                               0x29
0049 #define R_2A_COMP_BRIGHT_CNTL                         0x2a
0050 #define R_2B_COMP_CONTRAST_CNTL                       0x2b
0051 #define R_2C_COMP_SAT_CNTL                            0x2c
0052 #define R_2D_INTERRUPT_MASK_1                         0x2d
0053 #define R_2E_INTERRUPT_MASK_2                         0x2e
0054 #define R_2F_INTERRUPT_MASK_3                         0x2f
0055 
0056 /* Audio clock generator part */
0057 #define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD            0x30
0058 #define R_34_AUD_MAST_CLK_NOMINAL_INC                 0x34
0059 #define R_38_CLK_RATIO_AMXCLK_TO_ASCLK                0x38
0060 #define R_39_CLK_RATIO_ASCLK_TO_ALRCLK                0x39
0061 #define R_3A_AUD_CLK_GEN_BASIC_SETUP                  0x3a
0062 
0063 /* General purpose VBI data slicer part */
0064 #define R_40_SLICER_CNTL_1                            0x40
0065 #define R_41_LCR_BASE                                 0x41
0066 #define R_58_PROGRAM_FRAMING_CODE                     0x58
0067 #define R_59_H_OFF_FOR_SLICER                         0x59
0068 #define R_5A_V_OFF_FOR_SLICER                         0x5a
0069 #define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF          0x5b
0070 #define R_5D_DID                                      0x5d
0071 #define R_5E_SDID                                     0x5e
0072 #define R_60_SLICER_STATUS_BYTE_0                     0x60
0073 #define R_61_SLICER_STATUS_BYTE_1                     0x61
0074 #define R_62_SLICER_STATUS_BYTE_2                     0x62
0075 
0076 /* X port, I port and the scaler part */
0077     /* Task independent global settings */
0078 #define R_80_GLOBAL_CNTL_1                            0x80
0079 #define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F    0x81
0080 #define R_83_X_PORT_I_O_ENA_AND_OUT_CLK               0x83
0081 #define R_84_I_PORT_SIGNAL_DEF                        0x84
0082 #define R_85_I_PORT_SIGNAL_POLAR                      0x85
0083 #define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT          0x86
0084 #define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED         0x87
0085 #define R_88_POWER_SAVE_ADC_PORT_CNTL                 0x88
0086 #define R_8F_STATUS_INFO_SCALER                       0x8f
0087     /* Task A definition */
0088         /* Basic settings and acquisition window definition */
0089 #define R_90_A_TASK_HANDLING_CNTL                     0x90
0090 #define R_91_A_X_PORT_FORMATS_AND_CONF                0x91
0091 #define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL          0x92
0092 #define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF         0x93
0093 #define R_94_A_HORIZ_INPUT_WINDOW_START               0x94
0094 #define R_95_A_HORIZ_INPUT_WINDOW_START_MSB           0x95
0095 #define R_96_A_HORIZ_INPUT_WINDOW_LENGTH              0x96
0096 #define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB          0x97
0097 #define R_98_A_VERT_INPUT_WINDOW_START                0x98
0098 #define R_99_A_VERT_INPUT_WINDOW_START_MSB            0x99
0099 #define R_9A_A_VERT_INPUT_WINDOW_LENGTH               0x9a
0100 #define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB           0x9b
0101 #define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH             0x9c
0102 #define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0x9d
0103 #define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH              0x9e
0104 #define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB          0x9f
0105         /* FIR filtering and prescaling */
0106 #define R_A0_A_HORIZ_PRESCALING                       0xa0
0107 #define R_A1_A_ACCUMULATION_LENGTH                    0xa1
0108 #define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xa2
0109 #define R_A4_A_LUMA_BRIGHTNESS_CNTL                   0xa4
0110 #define R_A5_A_LUMA_CONTRAST_CNTL                     0xa5
0111 #define R_A6_A_CHROMA_SATURATION_CNTL                 0xa6
0112         /* Horizontal phase scaling */
0113 #define R_A8_A_HORIZ_LUMA_SCALING_INC                 0xa8
0114 #define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB             0xa9
0115 #define R_AA_A_HORIZ_LUMA_PHASE_OFF                   0xaa
0116 #define R_AC_A_HORIZ_CHROMA_SCALING_INC               0xac
0117 #define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB           0xad
0118 #define R_AE_A_HORIZ_CHROMA_PHASE_OFF                 0xae
0119 #define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB             0xaf
0120         /* Vertical scaling */
0121 #define R_B0_A_VERT_LUMA_SCALING_INC                  0xb0
0122 #define R_B1_A_VERT_LUMA_SCALING_INC_MSB              0xb1
0123 #define R_B2_A_VERT_CHROMA_SCALING_INC                0xb2
0124 #define R_B3_A_VERT_CHROMA_SCALING_INC_MSB            0xb3
0125 #define R_B4_A_VERT_SCALING_MODE_CNTL                 0xb4
0126 #define R_B8_A_VERT_CHROMA_PHASE_OFF_00               0xb8
0127 #define R_B9_A_VERT_CHROMA_PHASE_OFF_01               0xb9
0128 #define R_BA_A_VERT_CHROMA_PHASE_OFF_10               0xba
0129 #define R_BB_A_VERT_CHROMA_PHASE_OFF_11               0xbb
0130 #define R_BC_A_VERT_LUMA_PHASE_OFF_00                 0xbc
0131 #define R_BD_A_VERT_LUMA_PHASE_OFF_01                 0xbd
0132 #define R_BE_A_VERT_LUMA_PHASE_OFF_10                 0xbe
0133 #define R_BF_A_VERT_LUMA_PHASE_OFF_11                 0xbf
0134     /* Task B definition */
0135         /* Basic settings and acquisition window definition */
0136 #define R_C0_B_TASK_HANDLING_CNTL                     0xc0
0137 #define R_C1_B_X_PORT_FORMATS_AND_CONF                0xc1
0138 #define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION      0xc2
0139 #define R_C3_B_I_PORT_FORMATS_AND_CONF                0xc3
0140 #define R_C4_B_HORIZ_INPUT_WINDOW_START               0xc4
0141 #define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB           0xc5
0142 #define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH              0xc6
0143 #define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB          0xc7
0144 #define R_C8_B_VERT_INPUT_WINDOW_START                0xc8
0145 #define R_C9_B_VERT_INPUT_WINDOW_START_MSB            0xc9
0146 #define R_CA_B_VERT_INPUT_WINDOW_LENGTH               0xca
0147 #define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB           0xcb
0148 #define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH             0xcc
0149 #define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0xcd
0150 #define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH              0xce
0151 #define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB          0xcf
0152         /* FIR filtering and prescaling */
0153 #define R_D0_B_HORIZ_PRESCALING                       0xd0
0154 #define R_D1_B_ACCUMULATION_LENGTH                    0xd1
0155 #define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xd2
0156 #define R_D4_B_LUMA_BRIGHTNESS_CNTL                   0xd4
0157 #define R_D5_B_LUMA_CONTRAST_CNTL                     0xd5
0158 #define R_D6_B_CHROMA_SATURATION_CNTL                 0xd6
0159         /* Horizontal phase scaling */
0160 #define R_D8_B_HORIZ_LUMA_SCALING_INC                 0xd8
0161 #define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB             0xd9
0162 #define R_DA_B_HORIZ_LUMA_PHASE_OFF                   0xda
0163 #define R_DC_B_HORIZ_CHROMA_SCALING                   0xdc
0164 #define R_DD_B_HORIZ_CHROMA_SCALING_MSB               0xdd
0165 #define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA              0xde
0166         /* Vertical scaling */
0167 #define R_E0_B_VERT_LUMA_SCALING_INC                  0xe0
0168 #define R_E1_B_VERT_LUMA_SCALING_INC_MSB              0xe1
0169 #define R_E2_B_VERT_CHROMA_SCALING_INC                0xe2
0170 #define R_E3_B_VERT_CHROMA_SCALING_INC_MSB            0xe3
0171 #define R_E4_B_VERT_SCALING_MODE_CNTL                 0xe4
0172 #define R_E8_B_VERT_CHROMA_PHASE_OFF_00               0xe8
0173 #define R_E9_B_VERT_CHROMA_PHASE_OFF_01               0xe9
0174 #define R_EA_B_VERT_CHROMA_PHASE_OFF_10               0xea
0175 #define R_EB_B_VERT_CHROMA_PHASE_OFF_11               0xeb
0176 #define R_EC_B_VERT_LUMA_PHASE_OFF_00                 0xec
0177 #define R_ED_B_VERT_LUMA_PHASE_OFF_01                 0xed
0178 #define R_EE_B_VERT_LUMA_PHASE_OFF_10                 0xee
0179 #define R_EF_B_VERT_LUMA_PHASE_OFF_11                 0xef
0180 
0181 /* second PLL (PLL2) and Pulsegenerator Programming */
0182 #define R_F0_LFCO_PER_LINE                            0xf0
0183 #define R_F1_P_I_PARAM_SELECT                         0xf1
0184 #define R_F2_NOMINAL_PLL2_DTO                         0xf2
0185 #define R_F3_PLL_INCREMENT                            0xf3
0186 #define R_F4_PLL2_STATUS                              0xf4
0187 #define R_F5_PULSGEN_LINE_LENGTH                      0xf5
0188 #define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG      0xf6
0189 #define R_F7_PULSE_A_POS_MSB                          0xf7
0190 #define R_F8_PULSE_B_POS                              0xf8
0191 #define R_F9_PULSE_B_POS_MSB                          0xf9
0192 #define R_FA_PULSE_C_POS                              0xfa
0193 #define R_FB_PULSE_C_POS_MSB                          0xfb
0194 #define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES     0xff
0195 
0196 /* SAA7113 bit-masks */
0197 #define SAA7113_R_08_HTC_OFFSET 3
0198 #define SAA7113_R_08_HTC_MASK (0x3 << SAA7113_R_08_HTC_OFFSET)
0199 #define SAA7113_R_08_FSEL 0x40
0200 #define SAA7113_R_08_AUFD 0x80
0201 
0202 #define SAA7113_R_10_VRLN_OFFSET 3
0203 #define SAA7113_R_10_VRLN_MASK (0x1 << SAA7113_R_10_VRLN_OFFSET)
0204 #define SAA7113_R_10_OFTS_OFFSET 6
0205 #define SAA7113_R_10_OFTS_MASK (0x3 << SAA7113_R_10_OFTS_OFFSET)
0206 
0207 #define SAA7113_R_12_RTS0_OFFSET 0
0208 #define SAA7113_R_12_RTS0_MASK (0xf << SAA7113_R_12_RTS0_OFFSET)
0209 #define SAA7113_R_12_RTS1_OFFSET 4
0210 #define SAA7113_R_12_RTS1_MASK (0xf << SAA7113_R_12_RTS1_OFFSET)
0211 
0212 #define SAA7113_R_13_ADLSB_OFFSET 7
0213 #define SAA7113_R_13_ADLSB_MASK (0x1 << SAA7113_R_13_ADLSB_OFFSET)
0214 
0215 #if 0
0216 /* Those structs will be used in the future for debug purposes */
0217 struct saa711x_reg_descr {
0218     u8 reg;
0219     int count;
0220     char *name;
0221 };
0222 
0223 struct saa711x_reg_descr saa711x_regs[] = {
0224     /* REG COUNT NAME */
0225     {R_00_CHIP_VERSION,1,
0226      "Chip version"},
0227 
0228     /* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */
0229 
0230     /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
0231     {R_01_INC_DELAY,1,
0232      "Increment delay"},
0233     {R_02_INPUT_CNTL_1,1,
0234      "Analog input control 1"},
0235     {R_03_INPUT_CNTL_2,1,
0236      "Analog input control 2"},
0237     {R_04_INPUT_CNTL_3,1,
0238      "Analog input control 3"},
0239     {R_05_INPUT_CNTL_4,1,
0240      "Analog input control 4"},
0241 
0242     /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
0243     {R_06_H_SYNC_START,1,
0244      "Horizontal sync start"},
0245     {R_07_H_SYNC_STOP,1,
0246      "Horizontal sync stop"},
0247     {R_08_SYNC_CNTL,1,
0248      "Sync control"},
0249     {R_09_LUMA_CNTL,1,
0250      "Luminance control"},
0251     {R_0A_LUMA_BRIGHT_CNTL,1,
0252      "Luminance brightness control"},
0253     {R_0B_LUMA_CONTRAST_CNTL,1,
0254      "Luminance contrast control"},
0255     {R_0C_CHROMA_SAT_CNTL,1,
0256      "Chrominance saturation control"},
0257     {R_0D_CHROMA_HUE_CNTL,1,
0258      "Chrominance hue control"},
0259     {R_0E_CHROMA_CNTL_1,1,
0260      "Chrominance control 1"},
0261     {R_0F_CHROMA_GAIN_CNTL,1,
0262      "Chrominance gain control"},
0263     {R_10_CHROMA_CNTL_2,1,
0264      "Chrominance control 2"},
0265     {R_11_MODE_DELAY_CNTL,1,
0266      "Mode/delay control"},
0267     {R_12_RT_SIGNAL_CNTL,1,
0268      "RT signal control"},
0269     {R_13_RT_X_PORT_OUT_CNTL,1,
0270      "RT/X port output control"},
0271     {R_14_ANAL_ADC_COMPAT_CNTL,1,
0272      "Analog/ADC/compatibility control"},
0273     {R_15_VGATE_START_FID_CHG,  1,
0274      "VGATE start FID change"},
0275     {R_16_VGATE_STOP,1,
0276      "VGATE stop"},
0277     {R_17_MISC_VGATE_CONF_AND_MSB,  1,
0278      "Miscellaneous VGATE configuration and MSBs"},
0279     {R_18_RAW_DATA_GAIN_CNTL,1,
0280      "Raw data gain control",},
0281     {R_19_RAW_DATA_OFF_CNTL,1,
0282      "Raw data offset control",},
0283     {R_1A_COLOR_KILL_LVL_CNTL,1,
0284      "Color Killer Level Control"},
0285     { R_1B_MISC_TVVCRDET, 1,
0286       "MISC /TVVCRDET"},
0287     { R_1C_ENHAN_COMB_CTRL1, 1,
0288      "Enhanced comb ctrl1"},
0289     { R_1D_ENHAN_COMB_CTRL2, 1,
0290      "Enhanced comb ctrl1"},
0291     {R_1E_STATUS_BYTE_1_VD_DEC,1,
0292      "Status byte 1 video decoder"},
0293     {R_1F_STATUS_BYTE_2_VD_DEC,1,
0294      "Status byte 2 video decoder"},
0295 
0296     /* Component processing and interrupt masking part:  0x20h to R_2F_INTERRUPT_MASK_3 */
0297     /* 0x20 to 0x22 - Reserved */
0298     {R_23_INPUT_CNTL_5,1,
0299      "Analog input control 5"},
0300     {R_24_INPUT_CNTL_6,1,
0301      "Analog input control 6"},
0302     {R_25_INPUT_CNTL_7,1,
0303      "Analog input control 7"},
0304     /* 0x26 to 0x28 - Reserved */
0305     {R_29_COMP_DELAY,1,
0306      "Component delay"},
0307     {R_2A_COMP_BRIGHT_CNTL,1,
0308      "Component brightness control"},
0309     {R_2B_COMP_CONTRAST_CNTL,1,
0310      "Component contrast control"},
0311     {R_2C_COMP_SAT_CNTL,1,
0312      "Component saturation control"},
0313     {R_2D_INTERRUPT_MASK_1,1,
0314      "Interrupt mask 1"},
0315     {R_2E_INTERRUPT_MASK_2,1,
0316      "Interrupt mask 2"},
0317     {R_2F_INTERRUPT_MASK_3,1,
0318      "Interrupt mask 3"},
0319 
0320     /* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
0321     {R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
0322      "Audio master clock cycles per field"},
0323     /* 0x33 - Reserved */
0324     {R_34_AUD_MAST_CLK_NOMINAL_INC,3,
0325      "Audio master clock nominal increment"},
0326     /* 0x37 - Reserved */
0327     {R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
0328      "Clock ratio AMXCLK to ASCLK"},
0329     {R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
0330      "Clock ratio ASCLK to ALRCLK"},
0331     {R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
0332      "Audio clock generator basic setup"},
0333     /* 0x3b-0x3f - Reserved */
0334 
0335     /* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
0336     {R_40_SLICER_CNTL_1,1,
0337      "Slicer control 1"},
0338     {R_41_LCR,23,
0339      "R_41_LCR"},
0340     {R_58_PROGRAM_FRAMING_CODE,1,
0341      "Programmable framing code"},
0342     {R_59_H_OFF_FOR_SLICER,1,
0343      "Horizontal offset for slicer"},
0344     {R_5A_V_OFF_FOR_SLICER,1,
0345      "Vertical offset for slicer"},
0346     {R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
0347      "Field offset and MSBs for horizontal and vertical offset"},
0348     {R_5D_DID,1,
0349      "Header and data identification (R_5D_DID)"},
0350     {R_5E_SDID,1,
0351      "Sliced data identification (R_5E_SDID) code"},
0352     {R_60_SLICER_STATUS_BYTE_0,1,
0353      "Slicer status byte 0"},
0354     {R_61_SLICER_STATUS_BYTE_1,1,
0355      "Slicer status byte 1"},
0356     {R_62_SLICER_STATUS_BYTE_2,1,
0357      "Slicer status byte 2"},
0358     /* 0x63-0x7f - Reserved */
0359 
0360     /* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
0361     /* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
0362     {R_80_GLOBAL_CNTL_1,1,
0363      "Global control 1"},
0364     {R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
0365      "Vertical sync and Field ID source selection, retimed V and F signals"},
0366     /* 0x82 - Reserved */
0367     {R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
0368      "X port I/O enable and output clock"},
0369     {R_84_I_PORT_SIGNAL_DEF,1,
0370      "I port signal definitions"},
0371     {R_85_I_PORT_SIGNAL_POLAR,1,
0372      "I port signal polarities"},
0373     {R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
0374      "I port FIFO flag control and arbitration"},
0375     {R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,  1,
0376      "I port I/O enable output clock and gated"},
0377     {R_88_POWER_SAVE_ADC_PORT_CNTL,1,
0378      "Power save/ADC port control"},
0379     /* 089-0x8e - Reserved */
0380     {R_8F_STATUS_INFO_SCALER,1,
0381      "Status information scaler part"},
0382 
0383     /* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
0384     /* Task A: Basic settings and acquisition window definition */
0385     {R_90_A_TASK_HANDLING_CNTL,1,
0386      "Task A: Task handling control"},
0387     {R_91_A_X_PORT_FORMATS_AND_CONF,1,
0388      "Task A: X port formats and configuration"},
0389     {R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
0390      "Task A: X port input reference signal definition"},
0391     {R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
0392      "Task A: I port output formats and configuration"},
0393     {R_94_A_HORIZ_INPUT_WINDOW_START,2,
0394      "Task A: Horizontal input window start"},
0395     {R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
0396      "Task A: Horizontal input window length"},
0397     {R_98_A_VERT_INPUT_WINDOW_START,2,
0398      "Task A: Vertical input window start"},
0399     {R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
0400      "Task A: Vertical input window length"},
0401     {R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
0402      "Task A: Horizontal output window length"},
0403     {R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
0404      "Task A: Vertical output window length"},
0405 
0406     /* Task A: FIR filtering and prescaling */
0407     {R_A0_A_HORIZ_PRESCALING,1,
0408      "Task A: Horizontal prescaling"},
0409     {R_A1_A_ACCUMULATION_LENGTH,1,
0410      "Task A: Accumulation length"},
0411     {R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
0412      "Task A: Prescaler DC gain and FIR prefilter"},
0413     /* 0xa3 - Reserved */
0414     {R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
0415      "Task A: Luminance brightness control"},
0416     {R_A5_A_LUMA_CONTRAST_CNTL,1,
0417      "Task A: Luminance contrast control"},
0418     {R_A6_A_CHROMA_SATURATION_CNTL,1,
0419      "Task A: Chrominance saturation control"},
0420     /* 0xa7 - Reserved */
0421 
0422     /* Task A: Horizontal phase scaling */
0423     {R_A8_A_HORIZ_LUMA_SCALING_INC,2,
0424      "Task A: Horizontal luminance scaling increment"},
0425     {R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
0426      "Task A: Horizontal luminance phase offset"},
0427     /* 0xab - Reserved */
0428     {R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
0429      "Task A: Horizontal chrominance scaling increment"},
0430     {R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
0431      "Task A: Horizontal chrominance phase offset"},
0432     /* 0xaf - Reserved */
0433 
0434     /* Task A: Vertical scaling */
0435     {R_B0_A_VERT_LUMA_SCALING_INC,2,
0436      "Task A: Vertical luminance scaling increment"},
0437     {R_B2_A_VERT_CHROMA_SCALING_INC,2,
0438      "Task A: Vertical chrominance scaling increment"},
0439     {R_B4_A_VERT_SCALING_MODE_CNTL,1,
0440      "Task A: Vertical scaling mode control"},
0441     /* 0xb5-0xb7 - Reserved */
0442     {R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
0443      "Task A: Vertical chrominance phase offset '00'"},
0444     {R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
0445      "Task A: Vertical chrominance phase offset '01'"},
0446     {R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
0447      "Task A: Vertical chrominance phase offset '10'"},
0448     {R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
0449      "Task A: Vertical chrominance phase offset '11'"},
0450     {R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
0451      "Task A: Vertical luminance phase offset '00'"},
0452     {R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
0453      "Task A: Vertical luminance phase offset '01'"},
0454     {R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
0455      "Task A: Vertical luminance phase offset '10'"},
0456     {R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
0457      "Task A: Vertical luminance phase offset '11'"},
0458 
0459     /* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
0460     /* Task B: Basic settings and acquisition window definition */
0461     {R_C0_B_TASK_HANDLING_CNTL,1,
0462      "Task B: Task handling control"},
0463     {R_C1_B_X_PORT_FORMATS_AND_CONF,1,
0464      "Task B: X port formats and configuration"},
0465     {R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
0466      "Task B: Input reference signal definition"},
0467     {R_C3_B_I_PORT_FORMATS_AND_CONF,1,
0468      "Task B: I port formats and configuration"},
0469     {R_C4_B_HORIZ_INPUT_WINDOW_START,2,
0470      "Task B: Horizontal input window start"},
0471     {R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
0472      "Task B: Horizontal input window length"},
0473     {R_C8_B_VERT_INPUT_WINDOW_START,2,
0474      "Task B: Vertical input window start"},
0475     {R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
0476      "Task B: Vertical input window length"},
0477     {R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
0478      "Task B: Horizontal output window length"},
0479     {R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
0480      "Task B: Vertical output window length"},
0481 
0482     /* Task B: FIR filtering and prescaling */
0483     {R_D0_B_HORIZ_PRESCALING,1,
0484      "Task B: Horizontal prescaling"},
0485     {R_D1_B_ACCUMULATION_LENGTH,1,
0486      "Task B: Accumulation length"},
0487     {R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
0488      "Task B: Prescaler DC gain and FIR prefilter"},
0489     /* 0xd3 - Reserved */
0490     {R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
0491      "Task B: Luminance brightness control"},
0492     {R_D5_B_LUMA_CONTRAST_CNTL,1,
0493      "Task B: Luminance contrast control"},
0494     {R_D6_B_CHROMA_SATURATION_CNTL,1,
0495      "Task B: Chrominance saturation control"},
0496     /* 0xd7 - Reserved */
0497 
0498     /* Task B: Horizontal phase scaling */
0499     {R_D8_B_HORIZ_LUMA_SCALING_INC,2,
0500      "Task B: Horizontal luminance scaling increment"},
0501     {R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
0502      "Task B: Horizontal luminance phase offset"},
0503     /* 0xdb - Reserved */
0504     {R_DC_B_HORIZ_CHROMA_SCALING,2,
0505      "Task B: Horizontal chrominance scaling"},
0506     {R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
0507      "Task B: Horizontal Phase Offset Chroma"},
0508     /* 0xdf - Reserved */
0509 
0510     /* Task B: Vertical scaling */
0511     {R_E0_B_VERT_LUMA_SCALING_INC,2,
0512      "Task B: Vertical luminance scaling increment"},
0513     {R_E2_B_VERT_CHROMA_SCALING_INC,2,
0514      "Task B: Vertical chrominance scaling increment"},
0515     {R_E4_B_VERT_SCALING_MODE_CNTL,1,
0516      "Task B: Vertical scaling mode control"},
0517     /* 0xe5-0xe7 - Reserved */
0518     {R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
0519      "Task B: Vertical chrominance phase offset '00'"},
0520     {R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
0521      "Task B: Vertical chrominance phase offset '01'"},
0522     {R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
0523      "Task B: Vertical chrominance phase offset '10'"},
0524     {R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
0525      "Task B: Vertical chrominance phase offset '11'"},
0526     {R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
0527      "Task B: Vertical luminance phase offset '00'"},
0528     {R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
0529      "Task B: Vertical luminance phase offset '01'"},
0530     {R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
0531      "Task B: Vertical luminance phase offset '10'"},
0532     {R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
0533      "Task B: Vertical luminance phase offset '11'"},
0534 
0535     /* second PLL (PLL2) and Pulsegenerator Programming */
0536     { R_F0_LFCO_PER_LINE, 1,
0537       "LFCO's per line"},
0538     { R_F1_P_I_PARAM_SELECT,1,
0539       "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
0540     { R_F2_NOMINAL_PLL2_DTO,1,
0541      "Nominal PLL2 DTO"},
0542     {R_F3_PLL_INCREMENT,1,
0543      "PLL2 Increment"},
0544     {R_F4_PLL2_STATUS,1,
0545      "PLL2 Status"},
0546     {R_F5_PULSGEN_LINE_LENGTH,1,
0547      "Pulsgen. line length"},
0548     {R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
0549      "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
0550     {R_F7_PULSE_A_POS_MSB,1,
0551      "Pulse A Position"},
0552     {R_F8_PULSE_B_POS,2,
0553      "Pulse B Position"},
0554     {R_FA_PULSE_C_POS,2,
0555      "Pulse C Position"},
0556     /* 0xfc to 0xfe - Reserved */
0557     {R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
0558      "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
0559 };
0560 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!