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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Samsung LSI S5C73M3 8M pixel camera driver
0004  *
0005  * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
0006  * Sylwester Nawrocki <s.nawrocki@samsung.com>
0007  * Andrzej Hajda <a.hajda@samsung.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/firmware.h>
0013 #include <linux/gpio.h>
0014 #include <linux/i2c.h>
0015 #include <linux/init.h>
0016 #include <linux/media.h>
0017 #include <linux/module.h>
0018 #include <linux/of_gpio.h>
0019 #include <linux/of_graph.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/sizes.h>
0022 #include <linux/slab.h>
0023 #include <linux/spi/spi.h>
0024 #include <linux/videodev2.h>
0025 #include <media/media-entity.h>
0026 #include <media/v4l2-ctrls.h>
0027 #include <media/v4l2-device.h>
0028 #include <media/v4l2-subdev.h>
0029 #include <media/v4l2-mediabus.h>
0030 #include <media/i2c/s5c73m3.h>
0031 #include <media/v4l2-fwnode.h>
0032 
0033 #include "s5c73m3.h"
0034 
0035 int s5c73m3_dbg;
0036 module_param_named(debug, s5c73m3_dbg, int, 0644);
0037 
0038 static int boot_from_rom = 1;
0039 module_param(boot_from_rom, int, 0644);
0040 
0041 static int update_fw;
0042 module_param(update_fw, int, 0644);
0043 
0044 #define S5C73M3_EMBEDDED_DATA_MAXLEN    SZ_4K
0045 #define S5C73M3_MIPI_DATA_LANES     4
0046 #define S5C73M3_CLK_NAME        "cis_extclk"
0047 
0048 static const char * const s5c73m3_supply_names[S5C73M3_MAX_SUPPLIES] = {
0049     "vdd-int",  /* Digital Core supply (1.2V), CAM_ISP_CORE_1.2V */
0050     "vdda",     /* Analog Core supply (1.2V), CAM_SENSOR_CORE_1.2V */
0051     "vdd-reg",  /* Regulator input supply (2.8V), CAM_SENSOR_A2.8V */
0052     "vddio-host",   /* Digital Host I/O power supply (1.8V...2.8V),
0053                CAM_ISP_SENSOR_1.8V */
0054     "vddio-cis",    /* Digital CIS I/O power (1.2V...1.8V),
0055                CAM_ISP_MIPI_1.2V */
0056     "vdd-af",   /* Lens, CAM_AF_2.8V */
0057 };
0058 
0059 static const struct s5c73m3_frame_size s5c73m3_isp_resolutions[] = {
0060     { 320,  240,    COMM_CHG_MODE_YUV_320_240 },
0061     { 352,  288,    COMM_CHG_MODE_YUV_352_288 },
0062     { 640,  480,    COMM_CHG_MODE_YUV_640_480 },
0063     { 880,  720,    COMM_CHG_MODE_YUV_880_720 },
0064     { 960,  720,    COMM_CHG_MODE_YUV_960_720 },
0065     { 1008, 672,    COMM_CHG_MODE_YUV_1008_672 },
0066     { 1184, 666,    COMM_CHG_MODE_YUV_1184_666 },
0067     { 1280, 720,    COMM_CHG_MODE_YUV_1280_720 },
0068     { 1536, 864,    COMM_CHG_MODE_YUV_1536_864 },
0069     { 1600, 1200,   COMM_CHG_MODE_YUV_1600_1200 },
0070     { 1632, 1224,   COMM_CHG_MODE_YUV_1632_1224 },
0071     { 1920, 1080,   COMM_CHG_MODE_YUV_1920_1080 },
0072     { 1920, 1440,   COMM_CHG_MODE_YUV_1920_1440 },
0073     { 2304, 1296,   COMM_CHG_MODE_YUV_2304_1296 },
0074     { 3264, 2448,   COMM_CHG_MODE_YUV_3264_2448 },
0075 };
0076 
0077 static const struct s5c73m3_frame_size s5c73m3_jpeg_resolutions[] = {
0078     { 640,  480,    COMM_CHG_MODE_JPEG_640_480 },
0079     { 800,  450,    COMM_CHG_MODE_JPEG_800_450 },
0080     { 800,  600,    COMM_CHG_MODE_JPEG_800_600 },
0081     { 1024, 768,    COMM_CHG_MODE_JPEG_1024_768 },
0082     { 1280, 720,    COMM_CHG_MODE_JPEG_1280_720 },
0083     { 1280, 960,    COMM_CHG_MODE_JPEG_1280_960 },
0084     { 1600, 900,    COMM_CHG_MODE_JPEG_1600_900 },
0085     { 1600, 1200,   COMM_CHG_MODE_JPEG_1600_1200 },
0086     { 2048, 1152,   COMM_CHG_MODE_JPEG_2048_1152 },
0087     { 2048, 1536,   COMM_CHG_MODE_JPEG_2048_1536 },
0088     { 2560, 1440,   COMM_CHG_MODE_JPEG_2560_1440 },
0089     { 2560, 1920,   COMM_CHG_MODE_JPEG_2560_1920 },
0090     { 3264, 1836,   COMM_CHG_MODE_JPEG_3264_1836 },
0091     { 3264, 2176,   COMM_CHG_MODE_JPEG_3264_2176 },
0092     { 3264, 2448,   COMM_CHG_MODE_JPEG_3264_2448 },
0093 };
0094 
0095 static const struct s5c73m3_frame_size * const s5c73m3_resolutions[] = {
0096     [RES_ISP] = s5c73m3_isp_resolutions,
0097     [RES_JPEG] = s5c73m3_jpeg_resolutions
0098 };
0099 
0100 static const int s5c73m3_resolutions_len[] = {
0101     [RES_ISP] = ARRAY_SIZE(s5c73m3_isp_resolutions),
0102     [RES_JPEG] = ARRAY_SIZE(s5c73m3_jpeg_resolutions)
0103 };
0104 
0105 static const struct s5c73m3_interval s5c73m3_intervals[] = {
0106     { COMM_FRAME_RATE_FIXED_7FPS, {142857, 1000000}, {3264, 2448} },
0107     { COMM_FRAME_RATE_FIXED_15FPS, {66667, 1000000}, {3264, 2448} },
0108     { COMM_FRAME_RATE_FIXED_20FPS, {50000, 1000000}, {2304, 1296} },
0109     { COMM_FRAME_RATE_FIXED_30FPS, {33333, 1000000}, {2304, 1296} },
0110 };
0111 
0112 #define S5C73M3_DEFAULT_FRAME_INTERVAL 3 /* 30 fps */
0113 
0114 static void s5c73m3_fill_mbus_fmt(struct v4l2_mbus_framefmt *mf,
0115                   const struct s5c73m3_frame_size *fs,
0116                   u32 code)
0117 {
0118     mf->width = fs->width;
0119     mf->height = fs->height;
0120     mf->code = code;
0121     mf->colorspace = V4L2_COLORSPACE_JPEG;
0122     mf->field = V4L2_FIELD_NONE;
0123 }
0124 
0125 static int s5c73m3_i2c_write(struct i2c_client *client, u16 addr, u16 data)
0126 {
0127     u8 buf[4] = { addr >> 8, addr & 0xff, data >> 8, data & 0xff };
0128 
0129     int ret = i2c_master_send(client, buf, sizeof(buf));
0130 
0131     v4l_dbg(4, s5c73m3_dbg, client, "%s: addr 0x%04x, data 0x%04x\n",
0132          __func__, addr, data);
0133 
0134     if (ret == 4)
0135         return 0;
0136 
0137     return ret < 0 ? ret : -EREMOTEIO;
0138 }
0139 
0140 static int s5c73m3_i2c_read(struct i2c_client *client, u16 addr, u16 *data)
0141 {
0142     int ret;
0143     u8 rbuf[2], wbuf[2] = { addr >> 8, addr & 0xff };
0144     struct i2c_msg msg[2] = {
0145         {
0146             .addr = client->addr,
0147             .flags = 0,
0148             .len = sizeof(wbuf),
0149             .buf = wbuf
0150         }, {
0151             .addr = client->addr,
0152             .flags = I2C_M_RD,
0153             .len = sizeof(rbuf),
0154             .buf = rbuf
0155         }
0156     };
0157     /*
0158      * Issue repeated START after writing 2 address bytes and
0159      * just one STOP only after reading the data bytes.
0160      */
0161     ret = i2c_transfer(client->adapter, msg, 2);
0162     if (ret == 2) {
0163         *data = be16_to_cpup((__be16 *)rbuf);
0164         v4l2_dbg(4, s5c73m3_dbg, client,
0165              "%s: addr: 0x%04x, data: 0x%04x\n",
0166              __func__, addr, *data);
0167         return 0;
0168     }
0169 
0170     v4l2_err(client, "I2C read failed: addr: %04x, (%d)\n", addr, ret);
0171 
0172     return ret >= 0 ? -EREMOTEIO : ret;
0173 }
0174 
0175 int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data)
0176 {
0177     struct i2c_client *client = state->i2c_client;
0178     int ret;
0179 
0180     if ((addr ^ state->i2c_write_address) & 0xffff0000) {
0181         ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRH, addr >> 16);
0182         if (ret < 0) {
0183             state->i2c_write_address = 0;
0184             return ret;
0185         }
0186     }
0187 
0188     if ((addr ^ state->i2c_write_address) & 0xffff) {
0189         ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRL, addr & 0xffff);
0190         if (ret < 0) {
0191             state->i2c_write_address = 0;
0192             return ret;
0193         }
0194     }
0195 
0196     state->i2c_write_address = addr;
0197 
0198     ret = s5c73m3_i2c_write(client, REG_CMDBUF_ADDR, data);
0199     if (ret < 0)
0200         return ret;
0201 
0202     state->i2c_write_address += 2;
0203 
0204     return ret;
0205 }
0206 
0207 int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data)
0208 {
0209     struct i2c_client *client = state->i2c_client;
0210     int ret;
0211 
0212     if ((addr ^ state->i2c_read_address) & 0xffff0000) {
0213         ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRH, addr >> 16);
0214         if (ret < 0) {
0215             state->i2c_read_address = 0;
0216             return ret;
0217         }
0218     }
0219 
0220     if ((addr ^ state->i2c_read_address) & 0xffff) {
0221         ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRL, addr & 0xffff);
0222         if (ret < 0) {
0223             state->i2c_read_address = 0;
0224             return ret;
0225         }
0226     }
0227 
0228     state->i2c_read_address = addr;
0229 
0230     ret = s5c73m3_i2c_read(client, REG_CMDBUF_ADDR, data);
0231     if (ret < 0)
0232         return ret;
0233 
0234     state->i2c_read_address += 2;
0235 
0236     return ret;
0237 }
0238 
0239 static int s5c73m3_check_status(struct s5c73m3 *state, unsigned int value)
0240 {
0241     unsigned long start = jiffies;
0242     unsigned long end = start + msecs_to_jiffies(2000);
0243     int ret;
0244     u16 status;
0245     int count = 0;
0246 
0247     do {
0248         ret = s5c73m3_read(state, REG_STATUS, &status);
0249         if (ret < 0 || status == value)
0250             break;
0251         usleep_range(500, 1000);
0252         ++count;
0253     } while (time_is_after_jiffies(end));
0254 
0255     if (count > 0)
0256         v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
0257              "status check took %dms\n",
0258              jiffies_to_msecs(jiffies - start));
0259 
0260     if (ret == 0 && status != value) {
0261         u16 i2c_status = 0;
0262         u16 i2c_seq_status = 0;
0263 
0264         s5c73m3_read(state, REG_I2C_STATUS, &i2c_status);
0265         s5c73m3_read(state, REG_I2C_SEQ_STATUS, &i2c_seq_status);
0266 
0267         v4l2_err(&state->sensor_sd,
0268              "wrong status %#x, expected: %#x, i2c_status: %#x/%#x\n",
0269              status, value, i2c_status, i2c_seq_status);
0270 
0271         return -ETIMEDOUT;
0272     }
0273 
0274     return ret;
0275 }
0276 
0277 int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data)
0278 {
0279     int ret;
0280 
0281     ret = s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
0282     if (ret < 0)
0283         return ret;
0284 
0285     ret = s5c73m3_write(state, 0x00095000, command);
0286     if (ret < 0)
0287         return ret;
0288 
0289     ret = s5c73m3_write(state, 0x00095002, data);
0290     if (ret < 0)
0291         return ret;
0292 
0293     return s5c73m3_write(state, REG_STATUS, 0x0001);
0294 }
0295 
0296 static int s5c73m3_isp_comm_result(struct s5c73m3 *state, u16 command,
0297                    u16 *data)
0298 {
0299     return s5c73m3_read(state, COMM_RESULT_OFFSET + command, data);
0300 }
0301 
0302 static int s5c73m3_set_af_softlanding(struct s5c73m3 *state)
0303 {
0304     unsigned long start = jiffies;
0305     u16 af_softlanding;
0306     int count = 0;
0307     int ret;
0308     const char *msg;
0309 
0310     ret = s5c73m3_isp_command(state, COMM_AF_SOFTLANDING,
0311                     COMM_AF_SOFTLANDING_ON);
0312     if (ret < 0) {
0313         v4l2_info(&state->sensor_sd, "AF soft-landing failed\n");
0314         return ret;
0315     }
0316 
0317     for (;;) {
0318         ret = s5c73m3_isp_comm_result(state, COMM_AF_SOFTLANDING,
0319                             &af_softlanding);
0320         if (ret < 0) {
0321             msg = "failed";
0322             break;
0323         }
0324         if (af_softlanding == COMM_AF_SOFTLANDING_RES_COMPLETE) {
0325             msg = "succeeded";
0326             break;
0327         }
0328         if (++count > 100) {
0329             ret = -ETIME;
0330             msg = "timed out";
0331             break;
0332         }
0333         msleep(25);
0334     }
0335 
0336     v4l2_info(&state->sensor_sd, "AF soft-landing %s after %dms\n",
0337           msg, jiffies_to_msecs(jiffies - start));
0338 
0339     return ret;
0340 }
0341 
0342 static int s5c73m3_load_fw(struct v4l2_subdev *sd)
0343 {
0344     struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
0345     struct i2c_client *client = state->i2c_client;
0346     const struct firmware *fw;
0347     int ret;
0348     char fw_name[20];
0349 
0350     snprintf(fw_name, sizeof(fw_name), "SlimISP_%.2s.bin",
0351                             state->fw_file_version);
0352     ret = request_firmware(&fw, fw_name, &client->dev);
0353     if (ret < 0) {
0354         v4l2_err(sd, "Firmware request failed (%s)\n", fw_name);
0355         return -EINVAL;
0356     }
0357 
0358     v4l2_info(sd, "Loading firmware (%s, %zu B)\n", fw_name, fw->size);
0359 
0360     ret = s5c73m3_spi_write(state, fw->data, fw->size, 64);
0361 
0362     if (ret >= 0)
0363         state->isp_ready = 1;
0364     else
0365         v4l2_err(sd, "SPI write failed\n");
0366 
0367     release_firmware(fw);
0368 
0369     return ret;
0370 }
0371 
0372 static int s5c73m3_set_frame_size(struct s5c73m3 *state)
0373 {
0374     const struct s5c73m3_frame_size *prev_size =
0375                     state->sensor_pix_size[RES_ISP];
0376     const struct s5c73m3_frame_size *cap_size =
0377                     state->sensor_pix_size[RES_JPEG];
0378     unsigned int chg_mode;
0379 
0380     v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
0381          "Preview size: %dx%d, reg_val: 0x%x\n",
0382          prev_size->width, prev_size->height, prev_size->reg_val);
0383 
0384     chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW;
0385 
0386     if (state->mbus_code == S5C73M3_JPEG_FMT) {
0387         v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
0388              "Capture size: %dx%d, reg_val: 0x%x\n",
0389              cap_size->width, cap_size->height, cap_size->reg_val);
0390         chg_mode |= cap_size->reg_val;
0391     }
0392 
0393     return s5c73m3_isp_command(state, COMM_CHG_MODE, chg_mode);
0394 }
0395 
0396 static int s5c73m3_set_frame_rate(struct s5c73m3 *state)
0397 {
0398     int ret;
0399 
0400     if (state->ctrls.stabilization->val)
0401         return 0;
0402 
0403     if (WARN_ON(state->fiv == NULL))
0404         return -EINVAL;
0405 
0406     ret = s5c73m3_isp_command(state, COMM_FRAME_RATE, state->fiv->fps_reg);
0407     if (!ret)
0408         state->apply_fiv = 0;
0409 
0410     return ret;
0411 }
0412 
0413 static int __s5c73m3_s_stream(struct s5c73m3 *state, struct v4l2_subdev *sd,
0414                                 int on)
0415 {
0416     u16 mode;
0417     int ret;
0418 
0419     if (on && state->apply_fmt) {
0420         if (state->mbus_code == S5C73M3_JPEG_FMT)
0421             mode = COMM_IMG_OUTPUT_INTERLEAVED;
0422         else
0423             mode = COMM_IMG_OUTPUT_YUV;
0424 
0425         ret = s5c73m3_isp_command(state, COMM_IMG_OUTPUT, mode);
0426         if (!ret)
0427             ret = s5c73m3_set_frame_size(state);
0428         if (ret)
0429             return ret;
0430         state->apply_fmt = 0;
0431     }
0432 
0433     ret = s5c73m3_isp_command(state, COMM_SENSOR_STREAMING, !!on);
0434     if (ret)
0435         return ret;
0436 
0437     state->streaming = !!on;
0438 
0439     if (!on)
0440         return ret;
0441 
0442     if (state->apply_fiv) {
0443         ret = s5c73m3_set_frame_rate(state);
0444         if (ret < 0)
0445             v4l2_err(sd, "Error setting frame rate(%d)\n", ret);
0446     }
0447 
0448     return s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
0449 }
0450 
0451 static int s5c73m3_oif_s_stream(struct v4l2_subdev *sd, int on)
0452 {
0453     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
0454     int ret;
0455 
0456     mutex_lock(&state->lock);
0457     ret = __s5c73m3_s_stream(state, sd, on);
0458     mutex_unlock(&state->lock);
0459 
0460     return ret;
0461 }
0462 
0463 static int s5c73m3_system_status_wait(struct s5c73m3 *state, u32 value,
0464                       unsigned int delay, unsigned int steps)
0465 {
0466     u16 reg = 0;
0467 
0468     while (steps-- > 0) {
0469         int ret = s5c73m3_read(state, 0x30100010, &reg);
0470         if (ret < 0)
0471             return ret;
0472         if (reg == value)
0473             return 0;
0474         usleep_range(delay, delay + 25);
0475     }
0476     return -ETIMEDOUT;
0477 }
0478 
0479 static int s5c73m3_read_fw_version(struct s5c73m3 *state)
0480 {
0481     struct v4l2_subdev *sd = &state->sensor_sd;
0482     int i, ret;
0483     u16 data[2];
0484     int offset;
0485 
0486     offset = state->isp_ready ? 0x60 : 0;
0487 
0488     for (i = 0; i < S5C73M3_SENSOR_FW_LEN / 2; i++) {
0489         ret = s5c73m3_read(state, offset + i * 2, data);
0490         if (ret < 0)
0491             return ret;
0492         state->sensor_fw[i * 2] = (char)(*data & 0xff);
0493         state->sensor_fw[i * 2 + 1] = (char)(*data >> 8);
0494     }
0495     state->sensor_fw[S5C73M3_SENSOR_FW_LEN] = '\0';
0496 
0497 
0498     for (i = 0; i < S5C73M3_SENSOR_TYPE_LEN / 2; i++) {
0499         ret = s5c73m3_read(state, offset + 6 + i * 2, data);
0500         if (ret < 0)
0501             return ret;
0502         state->sensor_type[i * 2] = (char)(*data & 0xff);
0503         state->sensor_type[i * 2 + 1] = (char)(*data >> 8);
0504     }
0505     state->sensor_type[S5C73M3_SENSOR_TYPE_LEN] = '\0';
0506 
0507     ret = s5c73m3_read(state, offset + 0x14, data);
0508     if (ret >= 0) {
0509         ret = s5c73m3_read(state, offset + 0x16, data + 1);
0510         if (ret >= 0)
0511             state->fw_size = data[0] + (data[1] << 16);
0512     }
0513 
0514     v4l2_info(sd, "Sensor type: %s, FW version: %s\n",
0515           state->sensor_type, state->sensor_fw);
0516     return ret;
0517 }
0518 
0519 static int s5c73m3_fw_update_from(struct s5c73m3 *state)
0520 {
0521     struct v4l2_subdev *sd = &state->sensor_sd;
0522     u16 status = COMM_FW_UPDATE_NOT_READY;
0523     int ret;
0524     int count = 0;
0525 
0526     v4l2_warn(sd, "Updating F-ROM firmware.\n");
0527     do {
0528         if (status == COMM_FW_UPDATE_NOT_READY) {
0529             ret = s5c73m3_isp_command(state, COMM_FW_UPDATE, 0);
0530             if (ret < 0)
0531                 return ret;
0532         }
0533 
0534         ret = s5c73m3_read(state, 0x00095906, &status);
0535         if (ret < 0)
0536             return ret;
0537         switch (status) {
0538         case COMM_FW_UPDATE_FAIL:
0539             v4l2_warn(sd, "Updating F-ROM firmware failed.\n");
0540             return -EIO;
0541         case COMM_FW_UPDATE_SUCCESS:
0542             v4l2_warn(sd, "Updating F-ROM firmware finished.\n");
0543             return 0;
0544         }
0545         ++count;
0546         msleep(20);
0547     } while (count < 500);
0548 
0549     v4l2_warn(sd, "Updating F-ROM firmware timed-out.\n");
0550     return -ETIMEDOUT;
0551 }
0552 
0553 static int s5c73m3_spi_boot(struct s5c73m3 *state, bool load_fw)
0554 {
0555     struct v4l2_subdev *sd = &state->sensor_sd;
0556     int ret;
0557 
0558     /* Run ARM MCU */
0559     ret = s5c73m3_write(state, 0x30000004, 0xffff);
0560     if (ret < 0)
0561         return ret;
0562 
0563     usleep_range(400, 500);
0564 
0565     /* Check booting status */
0566     ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
0567     if (ret < 0) {
0568         v4l2_err(sd, "booting failed: %d\n", ret);
0569         return ret;
0570     }
0571 
0572     /* P,M,S and Boot Mode */
0573     ret = s5c73m3_write(state, 0x30100014, 0x2146);
0574     if (ret < 0)
0575         return ret;
0576 
0577     ret = s5c73m3_write(state, 0x30100010, 0x210c);
0578     if (ret < 0)
0579         return ret;
0580 
0581     usleep_range(200, 250);
0582 
0583     /* Check SPI status */
0584     ret = s5c73m3_system_status_wait(state, 0x210d, 100, 300);
0585     if (ret < 0)
0586         v4l2_err(sd, "SPI not ready: %d\n", ret);
0587 
0588     /* Firmware download over SPI */
0589     if (load_fw)
0590         s5c73m3_load_fw(sd);
0591 
0592     /* MCU reset */
0593     ret = s5c73m3_write(state, 0x30000004, 0xfffd);
0594     if (ret < 0)
0595         return ret;
0596 
0597     /* Remap */
0598     ret = s5c73m3_write(state, 0x301000a4, 0x0183);
0599     if (ret < 0)
0600         return ret;
0601 
0602     /* MCU restart */
0603     ret = s5c73m3_write(state, 0x30000004, 0xffff);
0604     if (ret < 0 || !load_fw)
0605         return ret;
0606 
0607     ret = s5c73m3_read_fw_version(state);
0608     if (ret < 0)
0609         return ret;
0610 
0611     if (load_fw && update_fw) {
0612         ret = s5c73m3_fw_update_from(state);
0613         update_fw = 0;
0614     }
0615 
0616     return ret;
0617 }
0618 
0619 static int s5c73m3_set_timing_register_for_vdd(struct s5c73m3 *state)
0620 {
0621     static const u32 regs[][2] = {
0622         { 0x30100018, 0x0618 },
0623         { 0x3010001c, 0x10c1 },
0624         { 0x30100020, 0x249e }
0625     };
0626     int ret;
0627     int i;
0628 
0629     for (i = 0; i < ARRAY_SIZE(regs); i++) {
0630         ret = s5c73m3_write(state, regs[i][0], regs[i][1]);
0631         if (ret < 0)
0632             return ret;
0633     }
0634 
0635     return 0;
0636 }
0637 
0638 static void s5c73m3_set_fw_file_version(struct s5c73m3 *state)
0639 {
0640     switch (state->sensor_fw[0]) {
0641     case 'G':
0642     case 'O':
0643         state->fw_file_version[0] = 'G';
0644         break;
0645     case 'S':
0646     case 'Z':
0647         state->fw_file_version[0] = 'Z';
0648         break;
0649     }
0650 
0651     switch (state->sensor_fw[1]) {
0652     case 'C'...'F':
0653         state->fw_file_version[1] = state->sensor_fw[1];
0654         break;
0655     }
0656 }
0657 
0658 static int s5c73m3_get_fw_version(struct s5c73m3 *state)
0659 {
0660     struct v4l2_subdev *sd = &state->sensor_sd;
0661     int ret;
0662 
0663     /* Run ARM MCU */
0664     ret = s5c73m3_write(state, 0x30000004, 0xffff);
0665     if (ret < 0)
0666         return ret;
0667     usleep_range(400, 500);
0668 
0669     /* Check booting status */
0670     ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
0671     if (ret < 0) {
0672 
0673         v4l2_err(sd, "%s: booting failed: %d\n", __func__, ret);
0674         return ret;
0675     }
0676 
0677     /* Change I/O Driver Current in order to read from F-ROM */
0678     ret = s5c73m3_write(state, 0x30100120, 0x0820);
0679     ret = s5c73m3_write(state, 0x30100124, 0x0820);
0680 
0681     /* Offset Setting */
0682     ret = s5c73m3_write(state, 0x00010418, 0x0008);
0683 
0684     /* P,M,S and Boot Mode */
0685     ret = s5c73m3_write(state, 0x30100014, 0x2146);
0686     if (ret < 0)
0687         return ret;
0688     ret = s5c73m3_write(state, 0x30100010, 0x230c);
0689     if (ret < 0)
0690         return ret;
0691 
0692     usleep_range(200, 250);
0693 
0694     /* Check SPI status */
0695     ret = s5c73m3_system_status_wait(state, 0x230e, 100, 300);
0696     if (ret < 0)
0697         v4l2_err(sd, "SPI not ready: %d\n", ret);
0698 
0699     /* ARM reset */
0700     ret = s5c73m3_write(state, 0x30000004, 0xfffd);
0701     if (ret < 0)
0702         return ret;
0703 
0704     /* Remap */
0705     ret = s5c73m3_write(state, 0x301000a4, 0x0183);
0706     if (ret < 0)
0707         return ret;
0708 
0709     s5c73m3_set_timing_register_for_vdd(state);
0710 
0711     ret = s5c73m3_read_fw_version(state);
0712 
0713     s5c73m3_set_fw_file_version(state);
0714 
0715     return ret;
0716 }
0717 
0718 static int s5c73m3_rom_boot(struct s5c73m3 *state, bool load_fw)
0719 {
0720     static const u32 boot_regs[][2] = {
0721         { 0x3100010c, 0x0044 },
0722         { 0x31000108, 0x000d },
0723         { 0x31000304, 0x0001 },
0724         { 0x00010000, 0x5800 },
0725         { 0x00010002, 0x0002 },
0726         { 0x31000000, 0x0001 },
0727         { 0x30100014, 0x1b85 },
0728         { 0x30100010, 0x230c }
0729     };
0730     struct v4l2_subdev *sd = &state->sensor_sd;
0731     int i, ret;
0732 
0733     /* Run ARM MCU */
0734     ret = s5c73m3_write(state, 0x30000004, 0xffff);
0735     if (ret < 0)
0736         return ret;
0737     usleep_range(400, 450);
0738 
0739     /* Check booting status */
0740     ret = s5c73m3_system_status_wait(state, 0x0c, 100, 4);
0741     if (ret < 0) {
0742         v4l2_err(sd, "Booting failed: %d\n", ret);
0743         return ret;
0744     }
0745 
0746     for (i = 0; i < ARRAY_SIZE(boot_regs); i++) {
0747         ret = s5c73m3_write(state, boot_regs[i][0], boot_regs[i][1]);
0748         if (ret < 0)
0749             return ret;
0750     }
0751     msleep(200);
0752 
0753     /* Check the binary read status */
0754     ret = s5c73m3_system_status_wait(state, 0x230e, 1000, 150);
0755     if (ret < 0) {
0756         v4l2_err(sd, "Binary read failed: %d\n", ret);
0757         return ret;
0758     }
0759 
0760     /* ARM reset */
0761     ret = s5c73m3_write(state, 0x30000004, 0xfffd);
0762     if (ret < 0)
0763         return ret;
0764     /* Remap */
0765     ret = s5c73m3_write(state, 0x301000a4, 0x0183);
0766     if (ret < 0)
0767         return ret;
0768     /* MCU re-start */
0769     ret = s5c73m3_write(state, 0x30000004, 0xffff);
0770     if (ret < 0)
0771         return ret;
0772 
0773     state->isp_ready = 1;
0774 
0775     return s5c73m3_read_fw_version(state);
0776 }
0777 
0778 static int s5c73m3_isp_init(struct s5c73m3 *state)
0779 {
0780     int ret;
0781 
0782     state->i2c_read_address = 0;
0783     state->i2c_write_address = 0;
0784 
0785     ret = s5c73m3_i2c_write(state->i2c_client, AHB_MSB_ADDR_PTR, 0x3310);
0786     if (ret < 0)
0787         return ret;
0788 
0789     if (boot_from_rom)
0790         return s5c73m3_rom_boot(state, true);
0791     else
0792         return s5c73m3_spi_boot(state, true);
0793 }
0794 
0795 static const struct s5c73m3_frame_size *s5c73m3_find_frame_size(
0796                     struct v4l2_mbus_framefmt *fmt,
0797                     enum s5c73m3_resolution_types idx)
0798 {
0799     const struct s5c73m3_frame_size *fs;
0800     const struct s5c73m3_frame_size *best_fs;
0801     int best_dist = INT_MAX;
0802     int i;
0803 
0804     fs = s5c73m3_resolutions[idx];
0805     best_fs = NULL;
0806     for (i = 0; i < s5c73m3_resolutions_len[idx]; ++i) {
0807         int dist = abs(fs->width - fmt->width) +
0808                         abs(fs->height - fmt->height);
0809         if (dist < best_dist) {
0810             best_dist = dist;
0811             best_fs = fs;
0812         }
0813         ++fs;
0814     }
0815 
0816     return best_fs;
0817 }
0818 
0819 static void s5c73m3_oif_try_format(struct s5c73m3 *state,
0820                    struct v4l2_subdev_state *sd_state,
0821                    struct v4l2_subdev_format *fmt,
0822                    const struct s5c73m3_frame_size **fs)
0823 {
0824     struct v4l2_subdev *sd = &state->sensor_sd;
0825     u32 code;
0826 
0827     switch (fmt->pad) {
0828     case OIF_ISP_PAD:
0829         *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
0830         code = S5C73M3_ISP_FMT;
0831         break;
0832     case OIF_JPEG_PAD:
0833         *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
0834         code = S5C73M3_JPEG_FMT;
0835         break;
0836     case OIF_SOURCE_PAD:
0837     default:
0838         if (fmt->format.code == S5C73M3_JPEG_FMT)
0839             code = S5C73M3_JPEG_FMT;
0840         else
0841             code = S5C73M3_ISP_FMT;
0842 
0843         if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
0844             *fs = state->oif_pix_size[RES_ISP];
0845         else
0846             *fs = s5c73m3_find_frame_size(
0847                         v4l2_subdev_get_try_format(sd, sd_state,
0848                                        OIF_ISP_PAD),
0849                         RES_ISP);
0850         break;
0851     }
0852 
0853     s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
0854 }
0855 
0856 static void s5c73m3_try_format(struct s5c73m3 *state,
0857                   struct v4l2_subdev_state *sd_state,
0858                   struct v4l2_subdev_format *fmt,
0859                   const struct s5c73m3_frame_size **fs)
0860 {
0861     u32 code;
0862 
0863     if (fmt->pad == S5C73M3_ISP_PAD) {
0864         *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
0865         code = S5C73M3_ISP_FMT;
0866     } else {
0867         *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
0868         code = S5C73M3_JPEG_FMT;
0869     }
0870 
0871     s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
0872 }
0873 
0874 static int s5c73m3_oif_g_frame_interval(struct v4l2_subdev *sd,
0875                    struct v4l2_subdev_frame_interval *fi)
0876 {
0877     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
0878 
0879     if (fi->pad != OIF_SOURCE_PAD)
0880         return -EINVAL;
0881 
0882     mutex_lock(&state->lock);
0883     fi->interval = state->fiv->interval;
0884     mutex_unlock(&state->lock);
0885 
0886     return 0;
0887 }
0888 
0889 static int __s5c73m3_set_frame_interval(struct s5c73m3 *state,
0890                     struct v4l2_subdev_frame_interval *fi)
0891 {
0892     const struct s5c73m3_frame_size *prev_size =
0893                         state->sensor_pix_size[RES_ISP];
0894     const struct s5c73m3_interval *fiv = &s5c73m3_intervals[0];
0895     unsigned int ret, min_err = UINT_MAX;
0896     unsigned int i, fr_time;
0897 
0898     if (fi->interval.denominator == 0)
0899         return -EINVAL;
0900 
0901     fr_time = fi->interval.numerator * 1000 / fi->interval.denominator;
0902 
0903     for (i = 0; i < ARRAY_SIZE(s5c73m3_intervals); i++) {
0904         const struct s5c73m3_interval *iv = &s5c73m3_intervals[i];
0905 
0906         if (prev_size->width > iv->size.width ||
0907             prev_size->height > iv->size.height)
0908             continue;
0909 
0910         ret = abs(iv->interval.numerator / 1000 - fr_time);
0911         if (ret < min_err) {
0912             fiv = iv;
0913             min_err = ret;
0914         }
0915     }
0916     state->fiv = fiv;
0917 
0918     v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
0919          "Changed frame interval to %u us\n", fiv->interval.numerator);
0920     return 0;
0921 }
0922 
0923 static int s5c73m3_oif_s_frame_interval(struct v4l2_subdev *sd,
0924                    struct v4l2_subdev_frame_interval *fi)
0925 {
0926     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
0927     int ret;
0928 
0929     if (fi->pad != OIF_SOURCE_PAD)
0930         return -EINVAL;
0931 
0932     v4l2_dbg(1, s5c73m3_dbg, sd, "Setting %d/%d frame interval\n",
0933          fi->interval.numerator, fi->interval.denominator);
0934 
0935     mutex_lock(&state->lock);
0936 
0937     ret = __s5c73m3_set_frame_interval(state, fi);
0938     if (!ret) {
0939         if (state->streaming)
0940             ret = s5c73m3_set_frame_rate(state);
0941         else
0942             state->apply_fiv = 1;
0943     }
0944     mutex_unlock(&state->lock);
0945     return ret;
0946 }
0947 
0948 static int s5c73m3_oif_enum_frame_interval(struct v4l2_subdev *sd,
0949                   struct v4l2_subdev_state *sd_state,
0950                   struct v4l2_subdev_frame_interval_enum *fie)
0951 {
0952     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
0953     const struct s5c73m3_interval *fi;
0954     int ret = 0;
0955 
0956     if (fie->pad != OIF_SOURCE_PAD)
0957         return -EINVAL;
0958     if (fie->index >= ARRAY_SIZE(s5c73m3_intervals))
0959         return -EINVAL;
0960 
0961     mutex_lock(&state->lock);
0962     fi = &s5c73m3_intervals[fie->index];
0963     if (fie->width > fi->size.width || fie->height > fi->size.height)
0964         ret = -EINVAL;
0965     else
0966         fie->interval = fi->interval;
0967     mutex_unlock(&state->lock);
0968 
0969     return ret;
0970 }
0971 
0972 static int s5c73m3_oif_get_pad_code(int pad, int index)
0973 {
0974     if (pad == OIF_SOURCE_PAD) {
0975         if (index > 1)
0976             return -EINVAL;
0977         return (index == 0) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
0978     }
0979 
0980     if (index > 0)
0981         return -EINVAL;
0982 
0983     return (pad == OIF_ISP_PAD) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
0984 }
0985 
0986 static int s5c73m3_get_fmt(struct v4l2_subdev *sd,
0987                struct v4l2_subdev_state *sd_state,
0988                struct v4l2_subdev_format *fmt)
0989 {
0990     struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
0991     const struct s5c73m3_frame_size *fs;
0992     u32 code;
0993 
0994     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0995         fmt->format = *v4l2_subdev_get_try_format(sd, sd_state,
0996                               fmt->pad);
0997         return 0;
0998     }
0999 
1000     mutex_lock(&state->lock);
1001 
1002     switch (fmt->pad) {
1003     case S5C73M3_ISP_PAD:
1004         code = S5C73M3_ISP_FMT;
1005         fs = state->sensor_pix_size[RES_ISP];
1006         break;
1007     case S5C73M3_JPEG_PAD:
1008         code = S5C73M3_JPEG_FMT;
1009         fs = state->sensor_pix_size[RES_JPEG];
1010         break;
1011     default:
1012         mutex_unlock(&state->lock);
1013         return -EINVAL;
1014     }
1015     s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
1016 
1017     mutex_unlock(&state->lock);
1018     return 0;
1019 }
1020 
1021 static int s5c73m3_oif_get_fmt(struct v4l2_subdev *sd,
1022                struct v4l2_subdev_state *sd_state,
1023                struct v4l2_subdev_format *fmt)
1024 {
1025     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1026     const struct s5c73m3_frame_size *fs;
1027     u32 code;
1028 
1029     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1030         fmt->format = *v4l2_subdev_get_try_format(sd, sd_state,
1031                               fmt->pad);
1032         return 0;
1033     }
1034 
1035     mutex_lock(&state->lock);
1036 
1037     switch (fmt->pad) {
1038     case OIF_ISP_PAD:
1039         code = S5C73M3_ISP_FMT;
1040         fs = state->oif_pix_size[RES_ISP];
1041         break;
1042     case OIF_JPEG_PAD:
1043         code = S5C73M3_JPEG_FMT;
1044         fs = state->oif_pix_size[RES_JPEG];
1045         break;
1046     case OIF_SOURCE_PAD:
1047         code = state->mbus_code;
1048         fs = state->oif_pix_size[RES_ISP];
1049         break;
1050     default:
1051         mutex_unlock(&state->lock);
1052         return -EINVAL;
1053     }
1054     s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
1055 
1056     mutex_unlock(&state->lock);
1057     return 0;
1058 }
1059 
1060 static int s5c73m3_set_fmt(struct v4l2_subdev *sd,
1061                struct v4l2_subdev_state *sd_state,
1062                struct v4l2_subdev_format *fmt)
1063 {
1064     const struct s5c73m3_frame_size *frame_size = NULL;
1065     struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
1066     struct v4l2_mbus_framefmt *mf;
1067     int ret = 0;
1068 
1069     mutex_lock(&state->lock);
1070 
1071     s5c73m3_try_format(state, sd_state, fmt, &frame_size);
1072 
1073     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1074         mf = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1075         *mf = fmt->format;
1076     } else {
1077         switch (fmt->pad) {
1078         case S5C73M3_ISP_PAD:
1079             state->sensor_pix_size[RES_ISP] = frame_size;
1080             break;
1081         case S5C73M3_JPEG_PAD:
1082             state->sensor_pix_size[RES_JPEG] = frame_size;
1083             break;
1084         default:
1085             ret = -EBUSY;
1086         }
1087 
1088         if (state->streaming)
1089             ret = -EBUSY;
1090         else
1091             state->apply_fmt = 1;
1092     }
1093 
1094     mutex_unlock(&state->lock);
1095 
1096     return ret;
1097 }
1098 
1099 static int s5c73m3_oif_set_fmt(struct v4l2_subdev *sd,
1100              struct v4l2_subdev_state *sd_state,
1101              struct v4l2_subdev_format *fmt)
1102 {
1103     const struct s5c73m3_frame_size *frame_size = NULL;
1104     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1105     struct v4l2_mbus_framefmt *mf;
1106     int ret = 0;
1107 
1108     mutex_lock(&state->lock);
1109 
1110     s5c73m3_oif_try_format(state, sd_state, fmt, &frame_size);
1111 
1112     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1113         mf = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1114         *mf = fmt->format;
1115         if (fmt->pad == OIF_ISP_PAD) {
1116             mf = v4l2_subdev_get_try_format(sd, sd_state,
1117                             OIF_SOURCE_PAD);
1118             mf->width = fmt->format.width;
1119             mf->height = fmt->format.height;
1120         }
1121     } else {
1122         switch (fmt->pad) {
1123         case OIF_ISP_PAD:
1124             state->oif_pix_size[RES_ISP] = frame_size;
1125             break;
1126         case OIF_JPEG_PAD:
1127             state->oif_pix_size[RES_JPEG] = frame_size;
1128             break;
1129         case OIF_SOURCE_PAD:
1130             state->mbus_code = fmt->format.code;
1131             break;
1132         default:
1133             ret = -EBUSY;
1134         }
1135 
1136         if (state->streaming)
1137             ret = -EBUSY;
1138         else
1139             state->apply_fmt = 1;
1140     }
1141 
1142     mutex_unlock(&state->lock);
1143 
1144     return ret;
1145 }
1146 
1147 static int s5c73m3_oif_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1148                   struct v4l2_mbus_frame_desc *fd)
1149 {
1150     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1151     int i;
1152 
1153     if (pad != OIF_SOURCE_PAD || fd == NULL)
1154         return -EINVAL;
1155 
1156     mutex_lock(&state->lock);
1157     fd->num_entries = 2;
1158     for (i = 0; i < fd->num_entries; i++)
1159         fd->entry[i] = state->frame_desc.entry[i];
1160     mutex_unlock(&state->lock);
1161 
1162     return 0;
1163 }
1164 
1165 static int s5c73m3_oif_set_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1166                       struct v4l2_mbus_frame_desc *fd)
1167 {
1168     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1169     struct v4l2_mbus_frame_desc *frame_desc = &state->frame_desc;
1170     int i;
1171 
1172     if (pad != OIF_SOURCE_PAD || fd == NULL)
1173         return -EINVAL;
1174 
1175     fd->entry[0].length = 10 * SZ_1M;
1176     fd->entry[1].length = max_t(u32, fd->entry[1].length,
1177                     S5C73M3_EMBEDDED_DATA_MAXLEN);
1178     fd->num_entries = 2;
1179 
1180     mutex_lock(&state->lock);
1181     for (i = 0; i < fd->num_entries; i++)
1182         frame_desc->entry[i] = fd->entry[i];
1183     mutex_unlock(&state->lock);
1184 
1185     return 0;
1186 }
1187 
1188 static int s5c73m3_enum_mbus_code(struct v4l2_subdev *sd,
1189                   struct v4l2_subdev_state *sd_state,
1190                   struct v4l2_subdev_mbus_code_enum *code)
1191 {
1192     static const int codes[] = {
1193             [S5C73M3_ISP_PAD] = S5C73M3_ISP_FMT,
1194             [S5C73M3_JPEG_PAD] = S5C73M3_JPEG_FMT};
1195 
1196     if (code->index > 0 || code->pad >= S5C73M3_NUM_PADS)
1197         return -EINVAL;
1198 
1199     code->code = codes[code->pad];
1200 
1201     return 0;
1202 }
1203 
1204 static int s5c73m3_oif_enum_mbus_code(struct v4l2_subdev *sd,
1205                 struct v4l2_subdev_state *sd_state,
1206                 struct v4l2_subdev_mbus_code_enum *code)
1207 {
1208     int ret;
1209 
1210     ret = s5c73m3_oif_get_pad_code(code->pad, code->index);
1211     if (ret < 0)
1212         return ret;
1213 
1214     code->code = ret;
1215 
1216     return 0;
1217 }
1218 
1219 static int s5c73m3_enum_frame_size(struct v4l2_subdev *sd,
1220                    struct v4l2_subdev_state *sd_state,
1221                    struct v4l2_subdev_frame_size_enum *fse)
1222 {
1223     int idx;
1224 
1225     if (fse->pad == S5C73M3_ISP_PAD) {
1226         if (fse->code != S5C73M3_ISP_FMT)
1227             return -EINVAL;
1228         idx = RES_ISP;
1229     } else{
1230         if (fse->code != S5C73M3_JPEG_FMT)
1231             return -EINVAL;
1232         idx = RES_JPEG;
1233     }
1234 
1235     if (fse->index >= s5c73m3_resolutions_len[idx])
1236         return -EINVAL;
1237 
1238     fse->min_width  = s5c73m3_resolutions[idx][fse->index].width;
1239     fse->max_width  = fse->min_width;
1240     fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
1241     fse->min_height = fse->max_height;
1242 
1243     return 0;
1244 }
1245 
1246 static int s5c73m3_oif_enum_frame_size(struct v4l2_subdev *sd,
1247                    struct v4l2_subdev_state *sd_state,
1248                    struct v4l2_subdev_frame_size_enum *fse)
1249 {
1250     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1251     int idx;
1252 
1253     if (fse->pad == OIF_SOURCE_PAD) {
1254         if (fse->index > 0)
1255             return -EINVAL;
1256 
1257         switch (fse->code) {
1258         case S5C73M3_JPEG_FMT:
1259         case S5C73M3_ISP_FMT: {
1260             unsigned w, h;
1261 
1262             if (fse->which == V4L2_SUBDEV_FORMAT_TRY) {
1263                 struct v4l2_mbus_framefmt *mf;
1264 
1265                 mf = v4l2_subdev_get_try_format(sd, sd_state,
1266                                 OIF_ISP_PAD);
1267 
1268                 w = mf->width;
1269                 h = mf->height;
1270             } else {
1271                 const struct s5c73m3_frame_size *fs;
1272 
1273                 fs = state->oif_pix_size[RES_ISP];
1274                 w = fs->width;
1275                 h = fs->height;
1276             }
1277             fse->max_width = fse->min_width = w;
1278             fse->max_height = fse->min_height = h;
1279             return 0;
1280         }
1281         default:
1282             return -EINVAL;
1283         }
1284     }
1285 
1286     if (fse->code != s5c73m3_oif_get_pad_code(fse->pad, 0))
1287         return -EINVAL;
1288 
1289     if (fse->pad == OIF_JPEG_PAD)
1290         idx = RES_JPEG;
1291     else
1292         idx = RES_ISP;
1293 
1294     if (fse->index >= s5c73m3_resolutions_len[idx])
1295         return -EINVAL;
1296 
1297     fse->min_width  = s5c73m3_resolutions[idx][fse->index].width;
1298     fse->max_width  = fse->min_width;
1299     fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
1300     fse->min_height = fse->max_height;
1301 
1302     return 0;
1303 }
1304 
1305 static int s5c73m3_oif_log_status(struct v4l2_subdev *sd)
1306 {
1307     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1308 
1309     v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
1310 
1311     v4l2_info(sd, "power: %d, apply_fmt: %d\n", state->power,
1312                             state->apply_fmt);
1313 
1314     return 0;
1315 }
1316 
1317 static int s5c73m3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1318 {
1319     struct v4l2_mbus_framefmt *mf;
1320 
1321     mf = v4l2_subdev_get_try_format(sd, fh->state, S5C73M3_ISP_PAD);
1322     s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
1323                         S5C73M3_ISP_FMT);
1324 
1325     mf = v4l2_subdev_get_try_format(sd, fh->state, S5C73M3_JPEG_PAD);
1326     s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
1327                     S5C73M3_JPEG_FMT);
1328 
1329     return 0;
1330 }
1331 
1332 static int s5c73m3_oif_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1333 {
1334     struct v4l2_mbus_framefmt *mf;
1335 
1336     mf = v4l2_subdev_get_try_format(sd, fh->state, OIF_ISP_PAD);
1337     s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
1338                         S5C73M3_ISP_FMT);
1339 
1340     mf = v4l2_subdev_get_try_format(sd, fh->state, OIF_JPEG_PAD);
1341     s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
1342                     S5C73M3_JPEG_FMT);
1343 
1344     mf = v4l2_subdev_get_try_format(sd, fh->state, OIF_SOURCE_PAD);
1345     s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
1346                         S5C73M3_ISP_FMT);
1347     return 0;
1348 }
1349 
1350 static int s5c73m3_gpio_set_value(struct s5c73m3 *priv, int id, u32 val)
1351 {
1352     if (!gpio_is_valid(priv->gpio[id].gpio))
1353         return 0;
1354     gpio_set_value(priv->gpio[id].gpio, !!val);
1355     return 1;
1356 }
1357 
1358 static int s5c73m3_gpio_assert(struct s5c73m3 *priv, int id)
1359 {
1360     return s5c73m3_gpio_set_value(priv, id, priv->gpio[id].level);
1361 }
1362 
1363 static int s5c73m3_gpio_deassert(struct s5c73m3 *priv, int id)
1364 {
1365     return s5c73m3_gpio_set_value(priv, id, !priv->gpio[id].level);
1366 }
1367 
1368 static int __s5c73m3_power_on(struct s5c73m3 *state)
1369 {
1370     int i, ret;
1371 
1372     for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++) {
1373         ret = regulator_enable(state->supplies[i].consumer);
1374         if (ret)
1375             goto err_reg_dis;
1376     }
1377 
1378     ret = clk_set_rate(state->clock, state->mclk_frequency);
1379     if (ret < 0)
1380         goto err_reg_dis;
1381 
1382     ret = clk_prepare_enable(state->clock);
1383     if (ret < 0)
1384         goto err_reg_dis;
1385 
1386     v4l2_dbg(1, s5c73m3_dbg, &state->oif_sd, "clock frequency: %ld\n",
1387                     clk_get_rate(state->clock));
1388 
1389     s5c73m3_gpio_deassert(state, STBY);
1390     usleep_range(100, 200);
1391 
1392     s5c73m3_gpio_deassert(state, RSET);
1393     usleep_range(50, 100);
1394 
1395     return 0;
1396 
1397 err_reg_dis:
1398     for (--i; i >= 0; i--)
1399         regulator_disable(state->supplies[i].consumer);
1400     return ret;
1401 }
1402 
1403 static int __s5c73m3_power_off(struct s5c73m3 *state)
1404 {
1405     int i, ret;
1406 
1407     if (s5c73m3_gpio_assert(state, RSET))
1408         usleep_range(10, 50);
1409 
1410     if (s5c73m3_gpio_assert(state, STBY))
1411         usleep_range(100, 200);
1412 
1413     clk_disable_unprepare(state->clock);
1414 
1415     state->streaming = 0;
1416     state->isp_ready = 0;
1417 
1418     for (i = S5C73M3_MAX_SUPPLIES - 1; i >= 0; i--) {
1419         ret = regulator_disable(state->supplies[i].consumer);
1420         if (ret)
1421             goto err;
1422     }
1423 
1424     return 0;
1425 err:
1426     for (++i; i < S5C73M3_MAX_SUPPLIES; i++) {
1427         int r = regulator_enable(state->supplies[i].consumer);
1428         if (r < 0)
1429             v4l2_err(&state->oif_sd, "Failed to re-enable %s: %d\n",
1430                  state->supplies[i].supply, r);
1431     }
1432 
1433     clk_prepare_enable(state->clock);
1434     return ret;
1435 }
1436 
1437 static int s5c73m3_oif_set_power(struct v4l2_subdev *sd, int on)
1438 {
1439     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1440     int ret = 0;
1441 
1442     mutex_lock(&state->lock);
1443 
1444     if (on && !state->power) {
1445         ret = __s5c73m3_power_on(state);
1446         if (!ret)
1447             ret = s5c73m3_isp_init(state);
1448         if (!ret) {
1449             state->apply_fiv = 1;
1450             state->apply_fmt = 1;
1451         }
1452     } else if (state->power == !on) {
1453         ret = s5c73m3_set_af_softlanding(state);
1454         if (!ret)
1455             ret = __s5c73m3_power_off(state);
1456         else
1457             v4l2_err(sd, "Soft landing lens failed\n");
1458     }
1459     if (!ret)
1460         state->power += on ? 1 : -1;
1461 
1462     v4l2_dbg(1, s5c73m3_dbg, sd, "%s: power: %d\n",
1463          __func__, state->power);
1464 
1465     mutex_unlock(&state->lock);
1466     return ret;
1467 }
1468 
1469 static int s5c73m3_oif_registered(struct v4l2_subdev *sd)
1470 {
1471     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1472     int ret;
1473 
1474     ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->sensor_sd);
1475     if (ret) {
1476         v4l2_err(sd->v4l2_dev, "Failed to register %s\n",
1477                             state->oif_sd.name);
1478         return ret;
1479     }
1480 
1481     ret = media_create_pad_link(&state->sensor_sd.entity,
1482             S5C73M3_ISP_PAD, &state->oif_sd.entity, OIF_ISP_PAD,
1483             MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1484 
1485     ret = media_create_pad_link(&state->sensor_sd.entity,
1486             S5C73M3_JPEG_PAD, &state->oif_sd.entity, OIF_JPEG_PAD,
1487             MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1488 
1489     return ret;
1490 }
1491 
1492 static void s5c73m3_oif_unregistered(struct v4l2_subdev *sd)
1493 {
1494     struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1495     v4l2_device_unregister_subdev(&state->sensor_sd);
1496 }
1497 
1498 static const struct v4l2_subdev_internal_ops s5c73m3_internal_ops = {
1499     .open       = s5c73m3_open,
1500 };
1501 
1502 static const struct v4l2_subdev_pad_ops s5c73m3_pad_ops = {
1503     .enum_mbus_code     = s5c73m3_enum_mbus_code,
1504     .enum_frame_size    = s5c73m3_enum_frame_size,
1505     .get_fmt        = s5c73m3_get_fmt,
1506     .set_fmt        = s5c73m3_set_fmt,
1507 };
1508 
1509 static const struct v4l2_subdev_ops s5c73m3_subdev_ops = {
1510     .pad    = &s5c73m3_pad_ops,
1511 };
1512 
1513 static const struct v4l2_subdev_internal_ops oif_internal_ops = {
1514     .registered = s5c73m3_oif_registered,
1515     .unregistered   = s5c73m3_oif_unregistered,
1516     .open       = s5c73m3_oif_open,
1517 };
1518 
1519 static const struct v4l2_subdev_pad_ops s5c73m3_oif_pad_ops = {
1520     .enum_mbus_code     = s5c73m3_oif_enum_mbus_code,
1521     .enum_frame_size    = s5c73m3_oif_enum_frame_size,
1522     .enum_frame_interval    = s5c73m3_oif_enum_frame_interval,
1523     .get_fmt        = s5c73m3_oif_get_fmt,
1524     .set_fmt        = s5c73m3_oif_set_fmt,
1525     .get_frame_desc     = s5c73m3_oif_get_frame_desc,
1526     .set_frame_desc     = s5c73m3_oif_set_frame_desc,
1527 };
1528 
1529 static const struct v4l2_subdev_core_ops s5c73m3_oif_core_ops = {
1530     .s_power    = s5c73m3_oif_set_power,
1531     .log_status = s5c73m3_oif_log_status,
1532 };
1533 
1534 static const struct v4l2_subdev_video_ops s5c73m3_oif_video_ops = {
1535     .s_stream       = s5c73m3_oif_s_stream,
1536     .g_frame_interval   = s5c73m3_oif_g_frame_interval,
1537     .s_frame_interval   = s5c73m3_oif_s_frame_interval,
1538 };
1539 
1540 static const struct v4l2_subdev_ops oif_subdev_ops = {
1541     .core   = &s5c73m3_oif_core_ops,
1542     .pad    = &s5c73m3_oif_pad_ops,
1543     .video  = &s5c73m3_oif_video_ops,
1544 };
1545 
1546 static int s5c73m3_configure_gpios(struct s5c73m3 *state)
1547 {
1548     static const char * const gpio_names[] = {
1549         "S5C73M3_STBY", "S5C73M3_RST"
1550     };
1551     struct i2c_client *c = state->i2c_client;
1552     struct s5c73m3_gpio *g = state->gpio;
1553     int ret, i;
1554 
1555     for (i = 0; i < GPIO_NUM; ++i) {
1556         unsigned int flags = GPIOF_DIR_OUT;
1557         if (g[i].level)
1558             flags |= GPIOF_INIT_HIGH;
1559         ret = devm_gpio_request_one(&c->dev, g[i].gpio, flags,
1560                         gpio_names[i]);
1561         if (ret) {
1562             v4l2_err(c, "failed to request gpio %s\n",
1563                  gpio_names[i]);
1564             return ret;
1565         }
1566     }
1567     return 0;
1568 }
1569 
1570 static int s5c73m3_parse_gpios(struct s5c73m3 *state)
1571 {
1572     static const char * const prop_names[] = {
1573         "standby-gpios", "xshutdown-gpios",
1574     };
1575     struct device *dev = &state->i2c_client->dev;
1576     struct device_node *node = dev->of_node;
1577     int ret, i;
1578 
1579     for (i = 0; i < GPIO_NUM; ++i) {
1580         enum of_gpio_flags of_flags;
1581 
1582         ret = of_get_named_gpio_flags(node, prop_names[i],
1583                           0, &of_flags);
1584         if (ret < 0) {
1585             dev_err(dev, "failed to parse %s DT property\n",
1586                 prop_names[i]);
1587             return -EINVAL;
1588         }
1589         state->gpio[i].gpio = ret;
1590         state->gpio[i].level = !(of_flags & OF_GPIO_ACTIVE_LOW);
1591     }
1592     return 0;
1593 }
1594 
1595 static int s5c73m3_get_platform_data(struct s5c73m3 *state)
1596 {
1597     struct device *dev = &state->i2c_client->dev;
1598     const struct s5c73m3_platform_data *pdata = dev->platform_data;
1599     struct device_node *node = dev->of_node;
1600     struct device_node *node_ep;
1601     struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
1602     int ret;
1603 
1604     if (!node) {
1605         if (!pdata) {
1606             dev_err(dev, "Platform data not specified\n");
1607             return -EINVAL;
1608         }
1609 
1610         state->mclk_frequency = pdata->mclk_frequency;
1611         state->gpio[STBY] = pdata->gpio_stby;
1612         state->gpio[RSET] = pdata->gpio_reset;
1613         return 0;
1614     }
1615 
1616     state->clock = devm_clk_get(dev, S5C73M3_CLK_NAME);
1617     if (IS_ERR(state->clock))
1618         return PTR_ERR(state->clock);
1619 
1620     if (of_property_read_u32(node, "clock-frequency",
1621                  &state->mclk_frequency)) {
1622         state->mclk_frequency = S5C73M3_DEFAULT_MCLK_FREQ;
1623         dev_info(dev, "using default %u Hz clock frequency\n",
1624                     state->mclk_frequency);
1625     }
1626 
1627     ret = s5c73m3_parse_gpios(state);
1628     if (ret < 0)
1629         return -EINVAL;
1630 
1631     node_ep = of_graph_get_next_endpoint(node, NULL);
1632     if (!node_ep) {
1633         dev_warn(dev, "no endpoint defined for node: %pOF\n", node);
1634         return 0;
1635     }
1636 
1637     ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node_ep), &ep);
1638     of_node_put(node_ep);
1639     if (ret)
1640         return ret;
1641 
1642     if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1643         dev_err(dev, "unsupported bus type\n");
1644         return -EINVAL;
1645     }
1646     /*
1647      * Number of MIPI CSI-2 data lanes is currently not configurable,
1648      * always a default value of 4 lanes is used.
1649      */
1650     if (ep.bus.mipi_csi2.num_data_lanes != S5C73M3_MIPI_DATA_LANES)
1651         dev_info(dev, "falling back to 4 MIPI CSI-2 data lanes\n");
1652 
1653     return 0;
1654 }
1655 
1656 static int s5c73m3_probe(struct i2c_client *client)
1657 {
1658     struct device *dev = &client->dev;
1659     struct v4l2_subdev *sd;
1660     struct v4l2_subdev *oif_sd;
1661     struct s5c73m3 *state;
1662     int ret, i;
1663 
1664     state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1665     if (!state)
1666         return -ENOMEM;
1667 
1668     state->i2c_client = client;
1669     ret = s5c73m3_get_platform_data(state);
1670     if (ret < 0)
1671         return ret;
1672 
1673     mutex_init(&state->lock);
1674     sd = &state->sensor_sd;
1675     oif_sd = &state->oif_sd;
1676 
1677     v4l2_subdev_init(sd, &s5c73m3_subdev_ops);
1678     sd->owner = client->dev.driver->owner;
1679     v4l2_set_subdevdata(sd, state);
1680     strscpy(sd->name, "S5C73M3", sizeof(sd->name));
1681 
1682     sd->internal_ops = &s5c73m3_internal_ops;
1683     sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1684 
1685     state->sensor_pads[S5C73M3_JPEG_PAD].flags = MEDIA_PAD_FL_SOURCE;
1686     state->sensor_pads[S5C73M3_ISP_PAD].flags = MEDIA_PAD_FL_SOURCE;
1687     sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1688 
1689     ret = media_entity_pads_init(&sd->entity, S5C73M3_NUM_PADS,
1690                             state->sensor_pads);
1691     if (ret < 0)
1692         return ret;
1693 
1694     v4l2_i2c_subdev_init(oif_sd, client, &oif_subdev_ops);
1695     /* Static name; NEVER use in new drivers! */
1696     strscpy(oif_sd->name, "S5C73M3-OIF", sizeof(oif_sd->name));
1697 
1698     oif_sd->internal_ops = &oif_internal_ops;
1699     oif_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1700 
1701     state->oif_pads[OIF_ISP_PAD].flags = MEDIA_PAD_FL_SINK;
1702     state->oif_pads[OIF_JPEG_PAD].flags = MEDIA_PAD_FL_SINK;
1703     state->oif_pads[OIF_SOURCE_PAD].flags = MEDIA_PAD_FL_SOURCE;
1704     oif_sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
1705 
1706     ret = media_entity_pads_init(&oif_sd->entity, OIF_NUM_PADS,
1707                             state->oif_pads);
1708     if (ret < 0)
1709         return ret;
1710 
1711     ret = s5c73m3_configure_gpios(state);
1712     if (ret)
1713         goto out_err;
1714 
1715     for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++)
1716         state->supplies[i].supply = s5c73m3_supply_names[i];
1717 
1718     ret = devm_regulator_bulk_get(dev, S5C73M3_MAX_SUPPLIES,
1719                    state->supplies);
1720     if (ret) {
1721         dev_err(dev, "failed to get regulators\n");
1722         goto out_err;
1723     }
1724 
1725     ret = s5c73m3_init_controls(state);
1726     if (ret)
1727         goto out_err;
1728 
1729     state->sensor_pix_size[RES_ISP] = &s5c73m3_isp_resolutions[1];
1730     state->sensor_pix_size[RES_JPEG] = &s5c73m3_jpeg_resolutions[1];
1731     state->oif_pix_size[RES_ISP] = state->sensor_pix_size[RES_ISP];
1732     state->oif_pix_size[RES_JPEG] = state->sensor_pix_size[RES_JPEG];
1733 
1734     state->mbus_code = S5C73M3_ISP_FMT;
1735 
1736     state->fiv = &s5c73m3_intervals[S5C73M3_DEFAULT_FRAME_INTERVAL];
1737 
1738     state->fw_file_version[0] = 'G';
1739     state->fw_file_version[1] = 'C';
1740 
1741     ret = s5c73m3_register_spi_driver(state);
1742     if (ret < 0)
1743         goto out_err;
1744 
1745     oif_sd->dev = dev;
1746 
1747     ret = __s5c73m3_power_on(state);
1748     if (ret < 0)
1749         goto out_err1;
1750 
1751     ret = s5c73m3_get_fw_version(state);
1752     __s5c73m3_power_off(state);
1753 
1754     if (ret < 0) {
1755         dev_err(dev, "Device detection failed: %d\n", ret);
1756         goto out_err1;
1757     }
1758 
1759     ret = v4l2_async_register_subdev(oif_sd);
1760     if (ret < 0)
1761         goto out_err1;
1762 
1763     v4l2_info(sd, "%s: completed successfully\n", __func__);
1764     return 0;
1765 
1766 out_err1:
1767     s5c73m3_unregister_spi_driver(state);
1768 out_err:
1769     media_entity_cleanup(&sd->entity);
1770     return ret;
1771 }
1772 
1773 static int s5c73m3_remove(struct i2c_client *client)
1774 {
1775     struct v4l2_subdev *oif_sd = i2c_get_clientdata(client);
1776     struct s5c73m3 *state = oif_sd_to_s5c73m3(oif_sd);
1777     struct v4l2_subdev *sensor_sd = &state->sensor_sd;
1778 
1779     v4l2_async_unregister_subdev(oif_sd);
1780 
1781     v4l2_ctrl_handler_free(oif_sd->ctrl_handler);
1782     media_entity_cleanup(&oif_sd->entity);
1783 
1784     v4l2_device_unregister_subdev(sensor_sd);
1785     media_entity_cleanup(&sensor_sd->entity);
1786 
1787     s5c73m3_unregister_spi_driver(state);
1788 
1789     return 0;
1790 }
1791 
1792 static const struct i2c_device_id s5c73m3_id[] = {
1793     { DRIVER_NAME, 0 },
1794     { }
1795 };
1796 MODULE_DEVICE_TABLE(i2c, s5c73m3_id);
1797 
1798 #ifdef CONFIG_OF
1799 static const struct of_device_id s5c73m3_of_match[] = {
1800     { .compatible = "samsung,s5c73m3" },
1801     { }
1802 };
1803 MODULE_DEVICE_TABLE(of, s5c73m3_of_match);
1804 #endif
1805 
1806 static struct i2c_driver s5c73m3_i2c_driver = {
1807     .driver = {
1808         .of_match_table = of_match_ptr(s5c73m3_of_match),
1809         .name   = DRIVER_NAME,
1810     },
1811     .probe_new  = s5c73m3_probe,
1812     .remove     = s5c73m3_remove,
1813     .id_table   = s5c73m3_id,
1814 };
1815 
1816 module_i2c_driver(s5c73m3_i2c_driver);
1817 
1818 MODULE_DESCRIPTION("Samsung S5C73M3 camera driver");
1819 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1820 MODULE_LICENSE("GPL");
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