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0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/i2c.h>
0014 #include <linux/module.h>
0015 #include <linux/slab.h>
0016 #include <linux/v4l2-mediabus.h>
0017 #include <linux/videodev2.h>
0018
0019 #include <media/i2c/rj54n1cb0c.h>
0020 #include <media/v4l2-device.h>
0021 #include <media/v4l2-ctrls.h>
0022 #include <media/v4l2-subdev.h>
0023
0024 #define RJ54N1_DEV_CODE 0x0400
0025 #define RJ54N1_DEV_CODE2 0x0401
0026 #define RJ54N1_OUT_SEL 0x0403
0027 #define RJ54N1_XY_OUTPUT_SIZE_S_H 0x0404
0028 #define RJ54N1_X_OUTPUT_SIZE_S_L 0x0405
0029 #define RJ54N1_Y_OUTPUT_SIZE_S_L 0x0406
0030 #define RJ54N1_XY_OUTPUT_SIZE_P_H 0x0407
0031 #define RJ54N1_X_OUTPUT_SIZE_P_L 0x0408
0032 #define RJ54N1_Y_OUTPUT_SIZE_P_L 0x0409
0033 #define RJ54N1_LINE_LENGTH_PCK_S_H 0x040a
0034 #define RJ54N1_LINE_LENGTH_PCK_S_L 0x040b
0035 #define RJ54N1_LINE_LENGTH_PCK_P_H 0x040c
0036 #define RJ54N1_LINE_LENGTH_PCK_P_L 0x040d
0037 #define RJ54N1_RESIZE_N 0x040e
0038 #define RJ54N1_RESIZE_N_STEP 0x040f
0039 #define RJ54N1_RESIZE_STEP 0x0410
0040 #define RJ54N1_RESIZE_HOLD_H 0x0411
0041 #define RJ54N1_RESIZE_HOLD_L 0x0412
0042 #define RJ54N1_H_OBEN_OFS 0x0413
0043 #define RJ54N1_V_OBEN_OFS 0x0414
0044 #define RJ54N1_RESIZE_CONTROL 0x0415
0045 #define RJ54N1_STILL_CONTROL 0x0417
0046 #define RJ54N1_INC_USE_SEL_H 0x0425
0047 #define RJ54N1_INC_USE_SEL_L 0x0426
0048 #define RJ54N1_MIRROR_STILL_MODE 0x0427
0049 #define RJ54N1_INIT_START 0x0428
0050 #define RJ54N1_SCALE_1_2_LEV 0x0429
0051 #define RJ54N1_SCALE_4_LEV 0x042a
0052 #define RJ54N1_Y_GAIN 0x04d8
0053 #define RJ54N1_APT_GAIN_UP 0x04fa
0054 #define RJ54N1_RA_SEL_UL 0x0530
0055 #define RJ54N1_BYTE_SWAP 0x0531
0056 #define RJ54N1_OUT_SIGPO 0x053b
0057 #define RJ54N1_WB_SEL_WEIGHT_I 0x054e
0058 #define RJ54N1_BIT8_WB 0x0569
0059 #define RJ54N1_HCAPS_WB 0x056a
0060 #define RJ54N1_VCAPS_WB 0x056b
0061 #define RJ54N1_HCAPE_WB 0x056c
0062 #define RJ54N1_VCAPE_WB 0x056d
0063 #define RJ54N1_EXPOSURE_CONTROL 0x058c
0064 #define RJ54N1_FRAME_LENGTH_S_H 0x0595
0065 #define RJ54N1_FRAME_LENGTH_S_L 0x0596
0066 #define RJ54N1_FRAME_LENGTH_P_H 0x0597
0067 #define RJ54N1_FRAME_LENGTH_P_L 0x0598
0068 #define RJ54N1_PEAK_H 0x05b7
0069 #define RJ54N1_PEAK_50 0x05b8
0070 #define RJ54N1_PEAK_60 0x05b9
0071 #define RJ54N1_PEAK_DIFF 0x05ba
0072 #define RJ54N1_IOC 0x05ef
0073 #define RJ54N1_TG_BYPASS 0x0700
0074 #define RJ54N1_PLL_L 0x0701
0075 #define RJ54N1_PLL_N 0x0702
0076 #define RJ54N1_PLL_EN 0x0704
0077 #define RJ54N1_RATIO_TG 0x0706
0078 #define RJ54N1_RATIO_T 0x0707
0079 #define RJ54N1_RATIO_R 0x0708
0080 #define RJ54N1_RAMP_TGCLK_EN 0x0709
0081 #define RJ54N1_OCLK_DSP 0x0710
0082 #define RJ54N1_RATIO_OP 0x0711
0083 #define RJ54N1_RATIO_O 0x0712
0084 #define RJ54N1_OCLK_SEL_EN 0x0713
0085 #define RJ54N1_CLK_RST 0x0717
0086 #define RJ54N1_RESET_STANDBY 0x0718
0087 #define RJ54N1_FWFLG 0x07fe
0088
0089 #define E_EXCLK (1 << 7)
0090 #define SOFT_STDBY (1 << 4)
0091 #define SEN_RSTX (1 << 2)
0092 #define TG_RSTX (1 << 1)
0093 #define DSP_RSTX (1 << 0)
0094
0095 #define RESIZE_HOLD_SEL (1 << 2)
0096 #define RESIZE_GO (1 << 1)
0097
0098
0099
0100
0101
0102 #define RJ54N1_COLUMN_SKIP 0
0103 #define RJ54N1_ROW_SKIP 0
0104 #define RJ54N1_MAX_WIDTH 1600
0105 #define RJ54N1_MAX_HEIGHT 1200
0106
0107 #define PLL_L 2
0108 #define PLL_N 0x31
0109
0110
0111
0112
0113 struct rj54n1_datafmt {
0114 u32 code;
0115 enum v4l2_colorspace colorspace;
0116 };
0117
0118
0119 static const struct rj54n1_datafmt *rj54n1_find_datafmt(
0120 u32 code, const struct rj54n1_datafmt *fmt,
0121 int n)
0122 {
0123 int i;
0124 for (i = 0; i < n; i++)
0125 if (fmt[i].code == code)
0126 return fmt + i;
0127
0128 return NULL;
0129 }
0130
0131 static const struct rj54n1_datafmt rj54n1_colour_fmts[] = {
0132 {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
0133 {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
0134 {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
0135 {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
0136 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
0137 {MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE, V4L2_COLORSPACE_SRGB},
0138 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
0139 {MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE, V4L2_COLORSPACE_SRGB},
0140 {MEDIA_BUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
0141 };
0142
0143 struct rj54n1_clock_div {
0144 u8 ratio_tg;
0145 u8 ratio_t;
0146 u8 ratio_r;
0147 u8 ratio_op;
0148 u8 ratio_o;
0149 };
0150
0151 struct rj54n1 {
0152 struct v4l2_subdev subdev;
0153 struct v4l2_ctrl_handler hdl;
0154 struct clk *clk;
0155 struct gpio_desc *pwup_gpio;
0156 struct gpio_desc *enable_gpio;
0157 struct rj54n1_clock_div clk_div;
0158 const struct rj54n1_datafmt *fmt;
0159 struct v4l2_rect rect;
0160 unsigned int tgclk_mhz;
0161 bool auto_wb;
0162 unsigned short width;
0163 unsigned short height;
0164 unsigned short resize;
0165 unsigned short scale;
0166 u8 bank;
0167 };
0168
0169 struct rj54n1_reg_val {
0170 u16 reg;
0171 u8 val;
0172 };
0173
0174 static const struct rj54n1_reg_val bank_4[] = {
0175 {0x417, 0},
0176 {0x42c, 0},
0177 {0x42d, 0xf0},
0178 {0x42e, 0},
0179 {0x42f, 0x50},
0180 {0x430, 0xf5},
0181 {0x431, 0x16},
0182 {0x432, 0x20},
0183 {0x433, 0},
0184 {0x434, 0xc8},
0185 {0x43c, 8},
0186 {0x43e, 0x90},
0187 {0x445, 0x83},
0188 {0x4ba, 0x58},
0189 {0x4bb, 4},
0190 {0x4bc, 0x20},
0191 {0x4db, 4},
0192 {0x4fe, 2},
0193 };
0194
0195 static const struct rj54n1_reg_val bank_5[] = {
0196 {0x514, 0},
0197 {0x516, 0},
0198 {0x518, 0},
0199 {0x51a, 0},
0200 {0x51d, 0xff},
0201 {0x56f, 0x28},
0202 {0x575, 0x40},
0203 {0x5bc, 0x48},
0204 {0x5c1, 6},
0205 {0x5e5, 0x11},
0206 {0x5e6, 0x43},
0207 {0x5e7, 0x33},
0208 {0x5e8, 0x21},
0209 {0x5e9, 0x30},
0210 {0x5ea, 0x0},
0211 {0x5eb, 0xa5},
0212 {0x5ec, 0xff},
0213 {0x5fe, 2},
0214 };
0215
0216 static const struct rj54n1_reg_val bank_7[] = {
0217 {0x70a, 0},
0218 {0x714, 0xff},
0219 {0x715, 0xff},
0220 {0x716, 0x1f},
0221 {0x7FE, 2},
0222 };
0223
0224 static const struct rj54n1_reg_val bank_8[] = {
0225 {0x800, 0x00},
0226 {0x801, 0x01},
0227 {0x802, 0x61},
0228 {0x805, 0x00},
0229 {0x806, 0x00},
0230 {0x807, 0x00},
0231 {0x808, 0x00},
0232 {0x809, 0x01},
0233 {0x80A, 0x61},
0234 {0x80B, 0x00},
0235 {0x80C, 0x01},
0236 {0x80D, 0x00},
0237 {0x80E, 0x00},
0238 {0x80F, 0x00},
0239 {0x810, 0x00},
0240 {0x811, 0x01},
0241 {0x812, 0x61},
0242 {0x813, 0x00},
0243 {0x814, 0x11},
0244 {0x815, 0x00},
0245 {0x816, 0x41},
0246 {0x817, 0x00},
0247 {0x818, 0x51},
0248 {0x819, 0x01},
0249 {0x81A, 0x1F},
0250 {0x81B, 0x00},
0251 {0x81C, 0x01},
0252 {0x81D, 0x00},
0253 {0x81E, 0x11},
0254 {0x81F, 0x00},
0255 {0x820, 0x41},
0256 {0x821, 0x00},
0257 {0x822, 0x51},
0258 {0x823, 0x00},
0259 {0x824, 0x00},
0260 {0x825, 0x00},
0261 {0x826, 0x47},
0262 {0x827, 0x01},
0263 {0x828, 0x4F},
0264 {0x829, 0x00},
0265 {0x82A, 0x00},
0266 {0x82B, 0x00},
0267 {0x82C, 0x30},
0268 {0x82D, 0x00},
0269 {0x82E, 0x40},
0270 {0x82F, 0x00},
0271 {0x830, 0xB3},
0272 {0x831, 0x00},
0273 {0x832, 0xE3},
0274 {0x833, 0x00},
0275 {0x834, 0x00},
0276 {0x835, 0x00},
0277 {0x836, 0x00},
0278 {0x837, 0x00},
0279 {0x838, 0x00},
0280 {0x839, 0x01},
0281 {0x83A, 0x61},
0282 {0x83B, 0x00},
0283 {0x83C, 0x01},
0284 {0x83D, 0x00},
0285 {0x83E, 0x00},
0286 {0x83F, 0x00},
0287 {0x840, 0x00},
0288 {0x841, 0x01},
0289 {0x842, 0x61},
0290 {0x843, 0x00},
0291 {0x844, 0x1D},
0292 {0x845, 0x00},
0293 {0x846, 0x00},
0294 {0x847, 0x00},
0295 {0x848, 0x00},
0296 {0x849, 0x01},
0297 {0x84A, 0x1F},
0298 {0x84B, 0x00},
0299 {0x84C, 0x05},
0300 {0x84D, 0x00},
0301 {0x84E, 0x19},
0302 {0x84F, 0x01},
0303 {0x850, 0x21},
0304 {0x851, 0x01},
0305 {0x852, 0x5D},
0306 {0x853, 0x00},
0307 {0x854, 0x00},
0308 {0x855, 0x00},
0309 {0x856, 0x19},
0310 {0x857, 0x01},
0311 {0x858, 0x21},
0312 {0x859, 0x00},
0313 {0x85A, 0x00},
0314 {0x85B, 0x00},
0315 {0x85C, 0x00},
0316 {0x85D, 0x00},
0317 {0x85E, 0x00},
0318 {0x85F, 0x00},
0319 {0x860, 0xB3},
0320 {0x861, 0x00},
0321 {0x862, 0xE3},
0322 {0x863, 0x00},
0323 {0x864, 0x00},
0324 {0x865, 0x00},
0325 {0x866, 0x00},
0326 {0x867, 0x00},
0327 {0x868, 0x00},
0328 {0x869, 0xE2},
0329 {0x86A, 0x00},
0330 {0x86B, 0x01},
0331 {0x86C, 0x06},
0332 {0x86D, 0x00},
0333 {0x86E, 0x00},
0334 {0x86F, 0x00},
0335 {0x870, 0x60},
0336 {0x871, 0x8C},
0337 {0x872, 0x10},
0338 {0x873, 0x00},
0339 {0x874, 0xE0},
0340 {0x875, 0x00},
0341 {0x876, 0x27},
0342 {0x877, 0x01},
0343 {0x878, 0x00},
0344 {0x879, 0x00},
0345 {0x87A, 0x00},
0346 {0x87B, 0x03},
0347 {0x87C, 0x00},
0348 {0x87D, 0x00},
0349 {0x87E, 0x00},
0350 {0x87F, 0x00},
0351 {0x880, 0x00},
0352 {0x881, 0x00},
0353 {0x882, 0x00},
0354 {0x883, 0x00},
0355 {0x884, 0x00},
0356 {0x885, 0x00},
0357 {0x886, 0xF8},
0358 {0x887, 0x00},
0359 {0x888, 0x03},
0360 {0x889, 0x00},
0361 {0x88A, 0x64},
0362 {0x88B, 0x00},
0363 {0x88C, 0x03},
0364 {0x88D, 0x00},
0365 {0x88E, 0xB1},
0366 {0x88F, 0x00},
0367 {0x890, 0x03},
0368 {0x891, 0x01},
0369 {0x892, 0x1D},
0370 {0x893, 0x00},
0371 {0x894, 0x03},
0372 {0x895, 0x01},
0373 {0x896, 0x4B},
0374 {0x897, 0x00},
0375 {0x898, 0xE5},
0376 {0x899, 0x00},
0377 {0x89A, 0x01},
0378 {0x89B, 0x00},
0379 {0x89C, 0x01},
0380 {0x89D, 0x04},
0381 {0x89E, 0xC8},
0382 {0x89F, 0x00},
0383 {0x8A0, 0x01},
0384 {0x8A1, 0x01},
0385 {0x8A2, 0x61},
0386 {0x8A3, 0x00},
0387 {0x8A4, 0x01},
0388 {0x8A5, 0x00},
0389 {0x8A6, 0x00},
0390 {0x8A7, 0x00},
0391 {0x8A8, 0x00},
0392 {0x8A9, 0x00},
0393 {0x8AA, 0x7F},
0394 {0x8AB, 0x03},
0395 {0x8AC, 0x00},
0396 {0x8AD, 0x00},
0397 {0x8AE, 0x00},
0398 {0x8AF, 0x00},
0399 {0x8B0, 0x00},
0400 {0x8B1, 0x00},
0401 {0x8B6, 0x00},
0402 {0x8B7, 0x01},
0403 {0x8B8, 0x00},
0404 {0x8B9, 0x00},
0405 {0x8BA, 0x02},
0406 {0x8BB, 0x00},
0407 {0x8BC, 0xFF},
0408 {0x8BD, 0x00},
0409 {0x8FE, 2},
0410 };
0411
0412 static const struct rj54n1_reg_val bank_10[] = {
0413 {0x10bf, 0x69}
0414 };
0415
0416
0417 static const struct rj54n1_clock_div clk_div = {
0418 .ratio_tg = 3 ,
0419 .ratio_t = 4 ,
0420 .ratio_r = 4 ,
0421 .ratio_op = 1 ,
0422 .ratio_o = 9 ,
0423 };
0424
0425 static struct rj54n1 *to_rj54n1(const struct i2c_client *client)
0426 {
0427 return container_of(i2c_get_clientdata(client), struct rj54n1, subdev);
0428 }
0429
0430 static int reg_read(struct i2c_client *client, const u16 reg)
0431 {
0432 struct rj54n1 *rj54n1 = to_rj54n1(client);
0433 int ret;
0434
0435
0436 if (rj54n1->bank != reg >> 8) {
0437 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
0438 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
0439 if (ret < 0)
0440 return ret;
0441 rj54n1->bank = reg >> 8;
0442 }
0443 return i2c_smbus_read_byte_data(client, reg & 0xff);
0444 }
0445
0446 static int reg_write(struct i2c_client *client, const u16 reg,
0447 const u8 data)
0448 {
0449 struct rj54n1 *rj54n1 = to_rj54n1(client);
0450 int ret;
0451
0452
0453 if (rj54n1->bank != reg >> 8) {
0454 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
0455 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
0456 if (ret < 0)
0457 return ret;
0458 rj54n1->bank = reg >> 8;
0459 }
0460 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", reg & 0xff, data);
0461 return i2c_smbus_write_byte_data(client, reg & 0xff, data);
0462 }
0463
0464 static int reg_set(struct i2c_client *client, const u16 reg,
0465 const u8 data, const u8 mask)
0466 {
0467 int ret;
0468
0469 ret = reg_read(client, reg);
0470 if (ret < 0)
0471 return ret;
0472 return reg_write(client, reg, (ret & ~mask) | (data & mask));
0473 }
0474
0475 static int reg_write_multiple(struct i2c_client *client,
0476 const struct rj54n1_reg_val *rv, const int n)
0477 {
0478 int i, ret;
0479
0480 for (i = 0; i < n; i++) {
0481 ret = reg_write(client, rv->reg, rv->val);
0482 if (ret < 0)
0483 return ret;
0484 rv++;
0485 }
0486
0487 return 0;
0488 }
0489
0490 static int rj54n1_enum_mbus_code(struct v4l2_subdev *sd,
0491 struct v4l2_subdev_state *sd_state,
0492 struct v4l2_subdev_mbus_code_enum *code)
0493 {
0494 if (code->pad || code->index >= ARRAY_SIZE(rj54n1_colour_fmts))
0495 return -EINVAL;
0496
0497 code->code = rj54n1_colour_fmts[code->index].code;
0498 return 0;
0499 }
0500
0501 static int rj54n1_s_stream(struct v4l2_subdev *sd, int enable)
0502 {
0503 struct i2c_client *client = v4l2_get_subdevdata(sd);
0504
0505
0506 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80);
0507 }
0508
0509 static int rj54n1_set_rect(struct i2c_client *client,
0510 u16 reg_x, u16 reg_y, u16 reg_xy,
0511 u32 width, u32 height)
0512 {
0513 int ret;
0514
0515 ret = reg_write(client, reg_xy,
0516 ((width >> 4) & 0x70) |
0517 ((height >> 8) & 7));
0518
0519 if (!ret)
0520 ret = reg_write(client, reg_x, width & 0xff);
0521 if (!ret)
0522 ret = reg_write(client, reg_y, height & 0xff);
0523
0524 return ret;
0525 }
0526
0527
0528
0529
0530
0531 static int rj54n1_commit(struct i2c_client *client)
0532 {
0533 int ret = reg_write(client, RJ54N1_INIT_START, 1);
0534 msleep(10);
0535 if (!ret)
0536 ret = reg_write(client, RJ54N1_INIT_START, 0);
0537 return ret;
0538 }
0539
0540 static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
0541 s32 *out_w, s32 *out_h);
0542
0543 static int rj54n1_set_selection(struct v4l2_subdev *sd,
0544 struct v4l2_subdev_state *sd_state,
0545 struct v4l2_subdev_selection *sel)
0546 {
0547 struct i2c_client *client = v4l2_get_subdevdata(sd);
0548 struct rj54n1 *rj54n1 = to_rj54n1(client);
0549 const struct v4l2_rect *rect = &sel->r;
0550 int output_w, output_h, input_w = rect->width, input_h = rect->height;
0551 int ret;
0552
0553 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
0554 sel->target != V4L2_SEL_TGT_CROP)
0555 return -EINVAL;
0556
0557
0558 v4l_bound_align_image(&input_w, 8, RJ54N1_MAX_WIDTH, 0,
0559 &input_h, 8, RJ54N1_MAX_HEIGHT, 0, 0);
0560
0561 output_w = (input_w * 1024 + rj54n1->resize / 2) / rj54n1->resize;
0562 output_h = (input_h * 1024 + rj54n1->resize / 2) / rj54n1->resize;
0563
0564 dev_dbg(&client->dev, "Scaling for %dx%d : %u = %dx%d\n",
0565 input_w, input_h, rj54n1->resize, output_w, output_h);
0566
0567 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
0568 if (ret < 0)
0569 return ret;
0570
0571 rj54n1->width = output_w;
0572 rj54n1->height = output_h;
0573 rj54n1->resize = ret;
0574 rj54n1->rect.width = input_w;
0575 rj54n1->rect.height = input_h;
0576
0577 return 0;
0578 }
0579
0580 static int rj54n1_get_selection(struct v4l2_subdev *sd,
0581 struct v4l2_subdev_state *sd_state,
0582 struct v4l2_subdev_selection *sel)
0583 {
0584 struct i2c_client *client = v4l2_get_subdevdata(sd);
0585 struct rj54n1 *rj54n1 = to_rj54n1(client);
0586
0587 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
0588 return -EINVAL;
0589
0590 switch (sel->target) {
0591 case V4L2_SEL_TGT_CROP_BOUNDS:
0592 sel->r.left = RJ54N1_COLUMN_SKIP;
0593 sel->r.top = RJ54N1_ROW_SKIP;
0594 sel->r.width = RJ54N1_MAX_WIDTH;
0595 sel->r.height = RJ54N1_MAX_HEIGHT;
0596 return 0;
0597 case V4L2_SEL_TGT_CROP:
0598 sel->r = rj54n1->rect;
0599 return 0;
0600 default:
0601 return -EINVAL;
0602 }
0603 }
0604
0605 static int rj54n1_get_fmt(struct v4l2_subdev *sd,
0606 struct v4l2_subdev_state *sd_state,
0607 struct v4l2_subdev_format *format)
0608 {
0609 struct v4l2_mbus_framefmt *mf = &format->format;
0610 struct i2c_client *client = v4l2_get_subdevdata(sd);
0611 struct rj54n1 *rj54n1 = to_rj54n1(client);
0612
0613 if (format->pad)
0614 return -EINVAL;
0615
0616 mf->code = rj54n1->fmt->code;
0617 mf->colorspace = rj54n1->fmt->colorspace;
0618 mf->ycbcr_enc = V4L2_YCBCR_ENC_601;
0619 mf->xfer_func = V4L2_XFER_FUNC_SRGB;
0620 mf->quantization = V4L2_QUANTIZATION_DEFAULT;
0621 mf->field = V4L2_FIELD_NONE;
0622 mf->width = rj54n1->width;
0623 mf->height = rj54n1->height;
0624
0625 return 0;
0626 }
0627
0628
0629
0630
0631
0632
0633 static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
0634 s32 *out_w, s32 *out_h)
0635 {
0636 struct i2c_client *client = v4l2_get_subdevdata(sd);
0637 struct rj54n1 *rj54n1 = to_rj54n1(client);
0638 unsigned int skip, resize, input_w = *in_w, input_h = *in_h,
0639 output_w = *out_w, output_h = *out_h;
0640 u16 inc_sel, wb_bit8, wb_left, wb_right, wb_top, wb_bottom;
0641 unsigned int peak, peak_50, peak_60;
0642 int ret;
0643
0644
0645
0646
0647
0648
0649
0650 if (output_w > max(512U, input_w / 2)) {
0651 if (2 * output_w > RJ54N1_MAX_WIDTH) {
0652 input_w = RJ54N1_MAX_WIDTH;
0653 output_w = RJ54N1_MAX_WIDTH / 2;
0654 } else {
0655 input_w = output_w * 2;
0656 }
0657
0658 dev_dbg(&client->dev, "Adjusted output width: in %u, out %u\n",
0659 input_w, output_w);
0660 }
0661
0662 if (output_h > max(384U, input_h / 2)) {
0663 if (2 * output_h > RJ54N1_MAX_HEIGHT) {
0664 input_h = RJ54N1_MAX_HEIGHT;
0665 output_h = RJ54N1_MAX_HEIGHT / 2;
0666 } else {
0667 input_h = output_h * 2;
0668 }
0669
0670 dev_dbg(&client->dev, "Adjusted output height: in %u, out %u\n",
0671 input_h, output_h);
0672 }
0673
0674
0675 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_S_L,
0676 RJ54N1_Y_OUTPUT_SIZE_S_L,
0677 RJ54N1_XY_OUTPUT_SIZE_S_H, output_w, output_h);
0678 if (!ret)
0679 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_P_L,
0680 RJ54N1_Y_OUTPUT_SIZE_P_L,
0681 RJ54N1_XY_OUTPUT_SIZE_P_H, output_w, output_h);
0682
0683 if (ret < 0)
0684 return ret;
0685
0686 if (output_w > input_w && output_h > input_h) {
0687 input_w = output_w;
0688 input_h = output_h;
0689
0690 resize = 1024;
0691 } else {
0692 unsigned int resize_x, resize_y;
0693 resize_x = (input_w * 1024 + output_w / 2) / output_w;
0694 resize_y = (input_h * 1024 + output_h / 2) / output_h;
0695
0696
0697 if (resize_x > resize_y &&
0698 (output_h * resize_x + 512) / 1024 > RJ54N1_MAX_HEIGHT)
0699 resize = (RJ54N1_MAX_HEIGHT * 1024 + output_h / 2) /
0700 output_h;
0701 else if (resize_y > resize_x &&
0702 (output_w * resize_y + 512) / 1024 > RJ54N1_MAX_WIDTH)
0703 resize = (RJ54N1_MAX_WIDTH * 1024 + output_w / 2) /
0704 output_w;
0705 else
0706 resize = max(resize_x, resize_y);
0707
0708
0709 switch (resize) {
0710 case 2040 ... 2047:
0711 resize = 2039;
0712 break;
0713 case 4080 ... 4095:
0714 resize = 4079;
0715 break;
0716 case 8160 ... 8191:
0717 resize = 8159;
0718 break;
0719 case 16320 ... 16384:
0720 resize = 16319;
0721 }
0722 }
0723
0724
0725 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff);
0726 if (!ret)
0727 ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8);
0728
0729 if (ret < 0)
0730 return ret;
0731
0732
0733
0734
0735
0736
0737
0738
0739
0740
0741
0742
0743
0744 skip = min(resize / 1024, 15U);
0745
0746 inc_sel = 1 << skip;
0747
0748 if (inc_sel <= 2)
0749 inc_sel = 0xc;
0750 else if (resize & 1023 && skip < 15)
0751 inc_sel |= 1 << (skip + 1);
0752
0753 ret = reg_write(client, RJ54N1_INC_USE_SEL_L, inc_sel & 0xfc);
0754 if (!ret)
0755 ret = reg_write(client, RJ54N1_INC_USE_SEL_H, inc_sel >> 8);
0756
0757 if (!rj54n1->auto_wb) {
0758
0759 wb_left = output_w / 16;
0760 wb_right = (3 * output_w / 4 - 3) / 4;
0761 wb_top = output_h / 16;
0762 wb_bottom = (3 * output_h / 4 - 3) / 4;
0763 wb_bit8 = ((wb_left >> 2) & 0x40) | ((wb_top >> 4) & 0x10) |
0764 ((wb_right >> 6) & 4) | ((wb_bottom >> 8) & 1);
0765
0766 if (!ret)
0767 ret = reg_write(client, RJ54N1_BIT8_WB, wb_bit8);
0768 if (!ret)
0769 ret = reg_write(client, RJ54N1_HCAPS_WB, wb_left);
0770 if (!ret)
0771 ret = reg_write(client, RJ54N1_VCAPS_WB, wb_top);
0772 if (!ret)
0773 ret = reg_write(client, RJ54N1_HCAPE_WB, wb_right);
0774 if (!ret)
0775 ret = reg_write(client, RJ54N1_VCAPE_WB, wb_bottom);
0776 }
0777
0778
0779 peak = 12 * RJ54N1_MAX_WIDTH * (1 << 14) * resize / rj54n1->tgclk_mhz /
0780 10000;
0781 peak_50 = peak / 6;
0782 peak_60 = peak / 5;
0783
0784 if (!ret)
0785 ret = reg_write(client, RJ54N1_PEAK_H,
0786 ((peak_50 >> 4) & 0xf0) | (peak_60 >> 8));
0787 if (!ret)
0788 ret = reg_write(client, RJ54N1_PEAK_50, peak_50);
0789 if (!ret)
0790 ret = reg_write(client, RJ54N1_PEAK_60, peak_60);
0791 if (!ret)
0792 ret = reg_write(client, RJ54N1_PEAK_DIFF, peak / 150);
0793
0794
0795 if (!ret)
0796 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
0797 RESIZE_HOLD_SEL | RESIZE_GO | 1);
0798
0799 if (ret < 0)
0800 return ret;
0801
0802
0803 msleep(230);
0804
0805 ret = reg_write(client, RJ54N1_RESIZE_CONTROL, RESIZE_HOLD_SEL | 1);
0806 if (ret < 0)
0807 return ret;
0808
0809 *in_w = (output_w * resize + 512) / 1024;
0810 *in_h = (output_h * resize + 512) / 1024;
0811 *out_w = output_w;
0812 *out_h = output_h;
0813
0814 dev_dbg(&client->dev, "Scaled for %dx%d : %u = %ux%u, skip %u\n",
0815 *in_w, *in_h, resize, output_w, output_h, skip);
0816
0817 return resize;
0818 }
0819
0820 static int rj54n1_set_clock(struct i2c_client *client)
0821 {
0822 struct rj54n1 *rj54n1 = to_rj54n1(client);
0823 int ret;
0824
0825
0826 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK | SOFT_STDBY);
0827
0828 if (!ret)
0829 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK);
0830
0831 if (!ret)
0832 ret = reg_write(client, RJ54N1_PLL_L, PLL_L);
0833 if (!ret)
0834 ret = reg_write(client, RJ54N1_PLL_N, PLL_N);
0835
0836
0837 if (!ret)
0838 ret = reg_write(client, RJ54N1_RATIO_TG,
0839 rj54n1->clk_div.ratio_tg);
0840 if (!ret)
0841 ret = reg_write(client, RJ54N1_RATIO_T,
0842 rj54n1->clk_div.ratio_t);
0843 if (!ret)
0844 ret = reg_write(client, RJ54N1_RATIO_R,
0845 rj54n1->clk_div.ratio_r);
0846
0847
0848 if (!ret)
0849 ret = reg_write(client, RJ54N1_RAMP_TGCLK_EN, 3);
0850
0851
0852 if (!ret)
0853 ret = reg_write(client, RJ54N1_OCLK_DSP, 0);
0854
0855
0856 if (!ret)
0857 ret = reg_write(client, RJ54N1_RATIO_OP,
0858 rj54n1->clk_div.ratio_op);
0859 if (!ret)
0860 ret = reg_write(client, RJ54N1_RATIO_O,
0861 rj54n1->clk_div.ratio_o);
0862
0863
0864 if (!ret)
0865 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
0866
0867
0868 if (!ret)
0869 ret = reg_write(client, RJ54N1_TG_BYPASS, 2);
0870
0871
0872 if (!ret)
0873 ret = reg_write(client, RJ54N1_RESET_STANDBY,
0874 E_EXCLK | SEN_RSTX);
0875
0876 if (!ret)
0877 ret = reg_write(client, RJ54N1_PLL_EN, 1);
0878
0879
0880 msleep(10);
0881
0882
0883 if (!ret)
0884 ret = reg_write(client, RJ54N1_CLK_RST, 1);
0885
0886 if (!ret)
0887 ret = reg_read(client, RJ54N1_CLK_RST);
0888 if (ret != 1) {
0889 dev_err(&client->dev,
0890 "Resetting RJ54N1CB0C clock failed: %d!\n", ret);
0891 return -EIO;
0892 }
0893
0894
0895 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1);
0896
0897
0898 if (!ret)
0899 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
0900
0901 return ret;
0902 }
0903
0904 static int rj54n1_reg_init(struct i2c_client *client)
0905 {
0906 struct rj54n1 *rj54n1 = to_rj54n1(client);
0907 int ret = rj54n1_set_clock(client);
0908
0909 if (!ret)
0910 ret = reg_write_multiple(client, bank_7, ARRAY_SIZE(bank_7));
0911 if (!ret)
0912 ret = reg_write_multiple(client, bank_10, ARRAY_SIZE(bank_10));
0913
0914
0915 if (!ret)
0916 ret = reg_write(client, RJ54N1_SCALE_1_2_LEV, 3 | (7 << 4));
0917 if (!ret)
0918 ret = reg_write(client, RJ54N1_SCALE_4_LEV, 0xf);
0919
0920
0921 if (!ret)
0922 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
0923 RESIZE_HOLD_SEL | 1);
0924
0925
0926 if (!ret)
0927 ret = reg_write(client, RJ54N1_Y_GAIN, 0x84);
0928
0929
0930
0931
0932
0933 if (!ret)
0934 ret = reg_write(client, RJ54N1_MIRROR_STILL_MODE, 0x27);
0935
0936 if (!ret)
0937 ret = reg_write_multiple(client, bank_4, ARRAY_SIZE(bank_4));
0938
0939
0940 if (!ret)
0941 ret = reg_write(client, RJ54N1_EXPOSURE_CONTROL, 0x80);
0942
0943 if (!ret)
0944 ret = reg_read(client, RJ54N1_WB_SEL_WEIGHT_I);
0945 if (ret >= 0) {
0946 rj54n1->auto_wb = ret & 0x80;
0947 ret = reg_write_multiple(client, bank_5, ARRAY_SIZE(bank_5));
0948 }
0949 if (!ret)
0950 ret = reg_write_multiple(client, bank_8, ARRAY_SIZE(bank_8));
0951
0952 if (!ret)
0953 ret = reg_write(client, RJ54N1_RESET_STANDBY,
0954 E_EXCLK | DSP_RSTX | SEN_RSTX);
0955
0956
0957 if (!ret)
0958 ret = rj54n1_commit(client);
0959
0960
0961 if (!ret)
0962 ret = reg_write(client, RJ54N1_RESET_STANDBY,
0963 E_EXCLK | DSP_RSTX | TG_RSTX | SEN_RSTX);
0964
0965
0966 if (!ret)
0967 ret = reg_write(client, RJ54N1_FWFLG, 2);
0968
0969
0970 msleep(700);
0971
0972 return ret;
0973 }
0974
0975 static int rj54n1_set_fmt(struct v4l2_subdev *sd,
0976 struct v4l2_subdev_state *sd_state,
0977 struct v4l2_subdev_format *format)
0978 {
0979 struct v4l2_mbus_framefmt *mf = &format->format;
0980 struct i2c_client *client = v4l2_get_subdevdata(sd);
0981 struct rj54n1 *rj54n1 = to_rj54n1(client);
0982 const struct rj54n1_datafmt *fmt;
0983 int output_w, output_h, max_w, max_h,
0984 input_w = rj54n1->rect.width, input_h = rj54n1->rect.height;
0985 int align = mf->code == MEDIA_BUS_FMT_SBGGR10_1X10 ||
0986 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE ||
0987 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE ||
0988 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE ||
0989 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE;
0990 int ret;
0991
0992 if (format->pad)
0993 return -EINVAL;
0994
0995 dev_dbg(&client->dev, "%s: code = %d, width = %u, height = %u\n",
0996 __func__, mf->code, mf->width, mf->height);
0997
0998 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
0999 ARRAY_SIZE(rj54n1_colour_fmts));
1000 if (!fmt) {
1001 fmt = rj54n1->fmt;
1002 mf->code = fmt->code;
1003 }
1004
1005 mf->field = V4L2_FIELD_NONE;
1006 mf->colorspace = fmt->colorspace;
1007
1008 v4l_bound_align_image(&mf->width, 112, RJ54N1_MAX_WIDTH, align,
1009 &mf->height, 84, RJ54N1_MAX_HEIGHT, align, 0);
1010
1011 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1012 sd_state->pads->try_fmt = *mf;
1013 return 0;
1014 }
1015
1016
1017
1018
1019
1020 ret = reg_read(client, RJ54N1_RESET_STANDBY);
1021 if (ret < 0)
1022 return ret;
1023
1024 if (!(ret & E_EXCLK)) {
1025 ret = rj54n1_reg_init(client);
1026 if (ret < 0)
1027 return ret;
1028 }
1029
1030
1031 switch (mf->code) {
1032 case MEDIA_BUS_FMT_YUYV8_2X8:
1033 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1034 if (!ret)
1035 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1036 break;
1037 case MEDIA_BUS_FMT_YVYU8_2X8:
1038 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1039 if (!ret)
1040 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1041 break;
1042 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1043 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1044 if (!ret)
1045 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1046 break;
1047 case MEDIA_BUS_FMT_RGB565_2X8_BE:
1048 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1049 if (!ret)
1050 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1051 break;
1052 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
1053 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1054 if (!ret)
1055 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1056 if (!ret)
1057 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1058 break;
1059 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
1060 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1061 if (!ret)
1062 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1063 if (!ret)
1064 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1065 break;
1066 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
1067 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1068 if (!ret)
1069 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1070 if (!ret)
1071 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1072 break;
1073 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
1074 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1075 if (!ret)
1076 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1077 if (!ret)
1078 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1079 break;
1080 case MEDIA_BUS_FMT_SBGGR10_1X10:
1081 ret = reg_write(client, RJ54N1_OUT_SEL, 5);
1082 break;
1083 default:
1084 ret = -EINVAL;
1085 }
1086
1087
1088 if (!ret)
1089 ret = reg_set(client, RJ54N1_OCLK_SEL_EN,
1090 (mf->code == MEDIA_BUS_FMT_SBGGR10_1X10) << 1, 2);
1091
1092 if (ret < 0)
1093 return ret;
1094
1095
1096 max_w = mf->width * (16 * 1024 - 1) / 1024;
1097 if (input_w > max_w)
1098 input_w = max_w;
1099 max_h = mf->height * (16 * 1024 - 1) / 1024;
1100 if (input_h > max_h)
1101 input_h = max_h;
1102
1103 output_w = mf->width;
1104 output_h = mf->height;
1105
1106 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
1107 if (ret < 0)
1108 return ret;
1109
1110 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
1111 ARRAY_SIZE(rj54n1_colour_fmts));
1112
1113 rj54n1->fmt = fmt;
1114 rj54n1->resize = ret;
1115 rj54n1->rect.width = input_w;
1116 rj54n1->rect.height = input_h;
1117 rj54n1->width = output_w;
1118 rj54n1->height = output_h;
1119
1120 mf->width = output_w;
1121 mf->height = output_h;
1122 mf->field = V4L2_FIELD_NONE;
1123 mf->colorspace = fmt->colorspace;
1124
1125 return 0;
1126 }
1127
1128 #ifdef CONFIG_VIDEO_ADV_DEBUG
1129 static int rj54n1_g_register(struct v4l2_subdev *sd,
1130 struct v4l2_dbg_register *reg)
1131 {
1132 struct i2c_client *client = v4l2_get_subdevdata(sd);
1133
1134 if (reg->reg < 0x400 || reg->reg > 0x1fff)
1135
1136 return -EINVAL;
1137
1138 reg->size = 1;
1139 reg->val = reg_read(client, reg->reg);
1140
1141 if (reg->val > 0xff)
1142 return -EIO;
1143
1144 return 0;
1145 }
1146
1147 static int rj54n1_s_register(struct v4l2_subdev *sd,
1148 const struct v4l2_dbg_register *reg)
1149 {
1150 struct i2c_client *client = v4l2_get_subdevdata(sd);
1151
1152 if (reg->reg < 0x400 || reg->reg > 0x1fff)
1153
1154 return -EINVAL;
1155
1156 if (reg_write(client, reg->reg, reg->val) < 0)
1157 return -EIO;
1158
1159 return 0;
1160 }
1161 #endif
1162
1163 static int rj54n1_s_power(struct v4l2_subdev *sd, int on)
1164 {
1165 struct i2c_client *client = v4l2_get_subdevdata(sd);
1166 struct rj54n1 *rj54n1 = to_rj54n1(client);
1167
1168 if (on) {
1169 if (rj54n1->pwup_gpio)
1170 gpiod_set_value(rj54n1->pwup_gpio, 1);
1171 if (rj54n1->enable_gpio)
1172 gpiod_set_value(rj54n1->enable_gpio, 1);
1173
1174 msleep(1);
1175
1176 return clk_prepare_enable(rj54n1->clk);
1177 }
1178
1179 clk_disable_unprepare(rj54n1->clk);
1180
1181 if (rj54n1->enable_gpio)
1182 gpiod_set_value(rj54n1->enable_gpio, 0);
1183 if (rj54n1->pwup_gpio)
1184 gpiod_set_value(rj54n1->pwup_gpio, 0);
1185
1186 return 0;
1187 }
1188
1189 static int rj54n1_s_ctrl(struct v4l2_ctrl *ctrl)
1190 {
1191 struct rj54n1 *rj54n1 = container_of(ctrl->handler, struct rj54n1, hdl);
1192 struct v4l2_subdev *sd = &rj54n1->subdev;
1193 struct i2c_client *client = v4l2_get_subdevdata(sd);
1194 int data;
1195
1196 switch (ctrl->id) {
1197 case V4L2_CID_VFLIP:
1198 if (ctrl->val)
1199 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 1);
1200 else
1201 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 1, 1);
1202 if (data < 0)
1203 return -EIO;
1204 return 0;
1205 case V4L2_CID_HFLIP:
1206 if (ctrl->val)
1207 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 2);
1208 else
1209 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 2, 2);
1210 if (data < 0)
1211 return -EIO;
1212 return 0;
1213 case V4L2_CID_GAIN:
1214 if (reg_write(client, RJ54N1_Y_GAIN, ctrl->val * 2) < 0)
1215 return -EIO;
1216 return 0;
1217 case V4L2_CID_AUTO_WHITE_BALANCE:
1218
1219 if (reg_set(client, RJ54N1_WB_SEL_WEIGHT_I, ctrl->val << 7,
1220 0x80) < 0)
1221 return -EIO;
1222 rj54n1->auto_wb = ctrl->val;
1223 return 0;
1224 }
1225
1226 return -EINVAL;
1227 }
1228
1229 static const struct v4l2_ctrl_ops rj54n1_ctrl_ops = {
1230 .s_ctrl = rj54n1_s_ctrl,
1231 };
1232
1233 static const struct v4l2_subdev_core_ops rj54n1_subdev_core_ops = {
1234 #ifdef CONFIG_VIDEO_ADV_DEBUG
1235 .g_register = rj54n1_g_register,
1236 .s_register = rj54n1_s_register,
1237 #endif
1238 .s_power = rj54n1_s_power,
1239 };
1240
1241 static const struct v4l2_subdev_video_ops rj54n1_subdev_video_ops = {
1242 .s_stream = rj54n1_s_stream,
1243 };
1244
1245 static const struct v4l2_subdev_pad_ops rj54n1_subdev_pad_ops = {
1246 .enum_mbus_code = rj54n1_enum_mbus_code,
1247 .get_selection = rj54n1_get_selection,
1248 .set_selection = rj54n1_set_selection,
1249 .get_fmt = rj54n1_get_fmt,
1250 .set_fmt = rj54n1_set_fmt,
1251 };
1252
1253 static const struct v4l2_subdev_ops rj54n1_subdev_ops = {
1254 .core = &rj54n1_subdev_core_ops,
1255 .video = &rj54n1_subdev_video_ops,
1256 .pad = &rj54n1_subdev_pad_ops,
1257 };
1258
1259
1260
1261
1262
1263 static int rj54n1_video_probe(struct i2c_client *client,
1264 struct rj54n1_pdata *priv)
1265 {
1266 struct rj54n1 *rj54n1 = to_rj54n1(client);
1267 int data1, data2;
1268 int ret;
1269
1270 ret = rj54n1_s_power(&rj54n1->subdev, 1);
1271 if (ret < 0)
1272 return ret;
1273
1274
1275 data1 = reg_read(client, RJ54N1_DEV_CODE);
1276 data2 = reg_read(client, RJ54N1_DEV_CODE2);
1277
1278 if (data1 != 0x51 || data2 != 0x10) {
1279 ret = -ENODEV;
1280 dev_info(&client->dev, "No RJ54N1CB0C found, read 0x%x:0x%x\n",
1281 data1, data2);
1282 goto done;
1283 }
1284
1285
1286 ret = reg_write(client, RJ54N1_IOC, priv->ioctl_high << 7);
1287 if (ret < 0)
1288 goto done;
1289
1290 dev_info(&client->dev, "Detected a RJ54N1CB0C chip ID 0x%x:0x%x\n",
1291 data1, data2);
1292
1293 ret = v4l2_ctrl_handler_setup(&rj54n1->hdl);
1294
1295 done:
1296 rj54n1_s_power(&rj54n1->subdev, 0);
1297 return ret;
1298 }
1299
1300 static int rj54n1_probe(struct i2c_client *client,
1301 const struct i2c_device_id *did)
1302 {
1303 struct rj54n1 *rj54n1;
1304 struct i2c_adapter *adapter = client->adapter;
1305 struct rj54n1_pdata *rj54n1_priv;
1306 int ret;
1307
1308 if (!client->dev.platform_data) {
1309 dev_err(&client->dev, "RJ54N1CB0C: missing platform data!\n");
1310 return -EINVAL;
1311 }
1312
1313 rj54n1_priv = client->dev.platform_data;
1314
1315 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1316 dev_warn(&adapter->dev,
1317 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
1318 return -EIO;
1319 }
1320
1321 rj54n1 = devm_kzalloc(&client->dev, sizeof(struct rj54n1), GFP_KERNEL);
1322 if (!rj54n1)
1323 return -ENOMEM;
1324
1325 v4l2_i2c_subdev_init(&rj54n1->subdev, client, &rj54n1_subdev_ops);
1326 v4l2_ctrl_handler_init(&rj54n1->hdl, 4);
1327 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1328 V4L2_CID_VFLIP, 0, 1, 1, 0);
1329 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1330 V4L2_CID_HFLIP, 0, 1, 1, 0);
1331 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1332 V4L2_CID_GAIN, 0, 127, 1, 66);
1333 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1334 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1335 rj54n1->subdev.ctrl_handler = &rj54n1->hdl;
1336 if (rj54n1->hdl.error)
1337 return rj54n1->hdl.error;
1338
1339 rj54n1->clk_div = clk_div;
1340 rj54n1->rect.left = RJ54N1_COLUMN_SKIP;
1341 rj54n1->rect.top = RJ54N1_ROW_SKIP;
1342 rj54n1->rect.width = RJ54N1_MAX_WIDTH;
1343 rj54n1->rect.height = RJ54N1_MAX_HEIGHT;
1344 rj54n1->width = RJ54N1_MAX_WIDTH;
1345 rj54n1->height = RJ54N1_MAX_HEIGHT;
1346 rj54n1->fmt = &rj54n1_colour_fmts[0];
1347 rj54n1->resize = 1024;
1348 rj54n1->tgclk_mhz = (rj54n1_priv->mclk_freq / PLL_L * PLL_N) /
1349 (clk_div.ratio_tg + 1) / (clk_div.ratio_t + 1);
1350
1351 rj54n1->clk = clk_get(&client->dev, NULL);
1352 if (IS_ERR(rj54n1->clk)) {
1353 ret = PTR_ERR(rj54n1->clk);
1354 goto err_free_ctrl;
1355 }
1356
1357 rj54n1->pwup_gpio = gpiod_get_optional(&client->dev, "powerup",
1358 GPIOD_OUT_LOW);
1359 if (IS_ERR(rj54n1->pwup_gpio)) {
1360 dev_info(&client->dev, "Unable to get GPIO \"powerup\": %ld\n",
1361 PTR_ERR(rj54n1->pwup_gpio));
1362 ret = PTR_ERR(rj54n1->pwup_gpio);
1363 goto err_clk_put;
1364 }
1365
1366 rj54n1->enable_gpio = gpiod_get_optional(&client->dev, "enable",
1367 GPIOD_OUT_LOW);
1368 if (IS_ERR(rj54n1->enable_gpio)) {
1369 dev_info(&client->dev, "Unable to get GPIO \"enable\": %ld\n",
1370 PTR_ERR(rj54n1->enable_gpio));
1371 ret = PTR_ERR(rj54n1->enable_gpio);
1372 goto err_gpio_put;
1373 }
1374
1375 ret = rj54n1_video_probe(client, rj54n1_priv);
1376 if (ret < 0)
1377 goto err_gpio_put;
1378
1379 ret = v4l2_async_register_subdev(&rj54n1->subdev);
1380 if (ret)
1381 goto err_gpio_put;
1382
1383 return 0;
1384
1385 err_gpio_put:
1386 if (rj54n1->enable_gpio)
1387 gpiod_put(rj54n1->enable_gpio);
1388
1389 if (rj54n1->pwup_gpio)
1390 gpiod_put(rj54n1->pwup_gpio);
1391
1392 err_clk_put:
1393 clk_put(rj54n1->clk);
1394
1395 err_free_ctrl:
1396 v4l2_ctrl_handler_free(&rj54n1->hdl);
1397
1398 return ret;
1399 }
1400
1401 static int rj54n1_remove(struct i2c_client *client)
1402 {
1403 struct rj54n1 *rj54n1 = to_rj54n1(client);
1404
1405 if (rj54n1->enable_gpio)
1406 gpiod_put(rj54n1->enable_gpio);
1407 if (rj54n1->pwup_gpio)
1408 gpiod_put(rj54n1->pwup_gpio);
1409
1410 clk_put(rj54n1->clk);
1411 v4l2_ctrl_handler_free(&rj54n1->hdl);
1412 v4l2_async_unregister_subdev(&rj54n1->subdev);
1413
1414 return 0;
1415 }
1416
1417 static const struct i2c_device_id rj54n1_id[] = {
1418 { "rj54n1cb0c", 0 },
1419 { }
1420 };
1421 MODULE_DEVICE_TABLE(i2c, rj54n1_id);
1422
1423 static struct i2c_driver rj54n1_i2c_driver = {
1424 .driver = {
1425 .name = "rj54n1cb0c",
1426 },
1427 .probe = rj54n1_probe,
1428 .remove = rj54n1_remove,
1429 .id_table = rj54n1_id,
1430 };
1431
1432 module_i2c_driver(rj54n1_i2c_driver);
1433
1434 MODULE_DESCRIPTION("Sharp RJ54N1CB0C Camera driver");
1435 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1436 MODULE_LICENSE("GPL v2");