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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * IMI RDACM21 GMSL Camera Driver
0004  *
0005  * Copyright (C) 2017-2020 Jacopo Mondi
0006  * Copyright (C) 2017-2019 Kieran Bingham
0007  * Copyright (C) 2017-2019 Laurent Pinchart
0008  * Copyright (C) 2017-2019 Niklas Söderlund
0009  * Copyright (C) 2016 Renesas Electronics Corporation
0010  * Copyright (C) 2015 Cogent Embedded, Inc.
0011  */
0012 
0013 #include <linux/delay.h>
0014 #include <linux/fwnode.h>
0015 #include <linux/init.h>
0016 #include <linux/i2c.h>
0017 #include <linux/module.h>
0018 #include <linux/slab.h>
0019 #include <linux/videodev2.h>
0020 
0021 #include <media/v4l2-async.h>
0022 #include <media/v4l2-ctrls.h>
0023 #include <media/v4l2-subdev.h>
0024 #include "max9271.h"
0025 
0026 #define MAX9271_RESET_CYCLES        10
0027 
0028 #define OV490_I2C_ADDRESS       0x24
0029 
0030 #define OV490_PAGE_HIGH_REG     0xfffd
0031 #define OV490_PAGE_LOW_REG      0xfffe
0032 
0033 /*
0034  * The SCCB slave handling is undocumented; the registers naming scheme is
0035  * totally arbitrary.
0036  */
0037 #define OV490_SCCB_SLAVE_WRITE      0x00
0038 #define OV490_SCCB_SLAVE_READ       0x01
0039 #define OV490_SCCB_SLAVE0_DIR       0x80195000
0040 #define OV490_SCCB_SLAVE0_ADDR_HIGH 0x80195001
0041 #define OV490_SCCB_SLAVE0_ADDR_LOW  0x80195002
0042 
0043 #define OV490_DVP_CTRL3         0x80286009
0044 
0045 #define OV490_ODS_CTRL_FRAME_OUTPUT_EN  0x0c
0046 #define OV490_ODS_CTRL          0x8029d000
0047 
0048 #define OV490_HOST_CMD          0x808000c0
0049 #define OV490_HOST_CMD_TRIGGER      0xc1
0050 
0051 #define OV490_ID_VAL            0x0490
0052 #define OV490_ID(_p, _v)        ((((_p) & 0xff) << 8) | ((_v) & 0xff))
0053 #define OV490_PID           0x8080300a
0054 #define OV490_VER           0x8080300b
0055 #define OV490_PID_TIMEOUT       20
0056 #define OV490_OUTPUT_EN_TIMEOUT     300
0057 
0058 #define OV490_GPIO0         BIT(0)
0059 #define OV490_SPWDN0            BIT(0)
0060 #define OV490_GPIO_SEL0         0x80800050
0061 #define OV490_GPIO_SEL1         0x80800051
0062 #define OV490_GPIO_DIRECTION0       0x80800054
0063 #define OV490_GPIO_DIRECTION1       0x80800055
0064 #define OV490_GPIO_OUTPUT_VALUE0    0x80800058
0065 #define OV490_GPIO_OUTPUT_VALUE1    0x80800059
0066 
0067 #define OV490_ISP_HSIZE_LOW     0x80820060
0068 #define OV490_ISP_HSIZE_HIGH        0x80820061
0069 #define OV490_ISP_VSIZE_LOW     0x80820062
0070 #define OV490_ISP_VSIZE_HIGH        0x80820063
0071 
0072 #define OV10640_PID_TIMEOUT     20
0073 #define OV10640_ID_HIGH         0xa6
0074 #define OV10640_CHIP_ID         0x300a
0075 #define OV10640_PIXEL_RATE      55000000
0076 
0077 struct rdacm21_device {
0078     struct device           *dev;
0079     struct max9271_device       serializer;
0080     struct i2c_client       *isp;
0081     struct v4l2_subdev      sd;
0082     struct media_pad        pad;
0083     struct v4l2_mbus_framefmt   fmt;
0084     struct v4l2_ctrl_handler    ctrls;
0085     u32             addrs[2];
0086     u16             last_page;
0087 };
0088 
0089 static inline struct rdacm21_device *sd_to_rdacm21(struct v4l2_subdev *sd)
0090 {
0091     return container_of(sd, struct rdacm21_device, sd);
0092 }
0093 
0094 static const struct ov490_reg {
0095     u16 reg;
0096     u8 val;
0097 } ov490_regs_wizard[] = {
0098     {0xfffd, 0x80},
0099     {0xfffe, 0x82},
0100     {0x0071, 0x11},
0101     {0x0075, 0x11},
0102     {0xfffe, 0x29},
0103     {0x6010, 0x01},
0104     /*
0105      * OV490 EMB line disable in YUV and RAW data,
0106      * NOTE: EMB line is still used in ISP and sensor
0107      */
0108     {0xe000, 0x14},
0109     {0xfffe, 0x28},
0110     {0x6000, 0x04},
0111     {0x6004, 0x00},
0112     /*
0113      * PCLK polarity - useless due to silicon bug.
0114      * Use 0x808000bb register instead.
0115      */
0116     {0x6008, 0x00},
0117     {0xfffe, 0x80},
0118     {0x0091, 0x00},
0119     /* bit[3]=0 - PCLK polarity workaround. */
0120     {0x00bb, 0x1d},
0121     /* Ov490 FSIN: app_fsin_from_fsync */
0122     {0xfffe, 0x85},
0123     {0x0008, 0x00},
0124     {0x0009, 0x01},
0125     /* FSIN0 source. */
0126     {0x000A, 0x05},
0127     {0x000B, 0x00},
0128     /* FSIN0 delay. */
0129     {0x0030, 0x02},
0130     {0x0031, 0x00},
0131     {0x0032, 0x00},
0132     {0x0033, 0x00},
0133     /* FSIN1 delay. */
0134     {0x0038, 0x02},
0135     {0x0039, 0x00},
0136     {0x003A, 0x00},
0137     {0x003B, 0x00},
0138     /* FSIN0 length. */
0139     {0x0070, 0x2C},
0140     {0x0071, 0x01},
0141     {0x0072, 0x00},
0142     {0x0073, 0x00},
0143     /* FSIN1 length. */
0144     {0x0074, 0x64},
0145     {0x0075, 0x00},
0146     {0x0076, 0x00},
0147     {0x0077, 0x00},
0148     {0x0000, 0x14},
0149     {0x0001, 0x00},
0150     {0x0002, 0x00},
0151     {0x0003, 0x00},
0152     /*
0153      * Load fsin0,load fsin1,load other,
0154      * It will be cleared automatically.
0155      */
0156     {0x0004, 0x32},
0157     {0x0005, 0x00},
0158     {0x0006, 0x00},
0159     {0x0007, 0x00},
0160     {0xfffe, 0x80},
0161     /* Sensor FSIN. */
0162     {0x0081, 0x00},
0163     /* ov10640 FSIN enable */
0164     {0xfffe, 0x19},
0165     {0x5000, 0x00},
0166     {0x5001, 0x30},
0167     {0x5002, 0x8c},
0168     {0x5003, 0xb2},
0169     {0xfffe, 0x80},
0170     {0x00c0, 0xc1},
0171     /* ov10640 HFLIP=1 by default */
0172     {0xfffe, 0x19},
0173     {0x5000, 0x01},
0174     {0x5001, 0x00},
0175     {0xfffe, 0x80},
0176     {0x00c0, 0xdc},
0177 };
0178 
0179 static int ov490_read(struct rdacm21_device *dev, u16 reg, u8 *val)
0180 {
0181     u8 buf[2] = { reg >> 8, reg };
0182     int ret;
0183 
0184     ret = i2c_master_send(dev->isp, buf, 2);
0185     if (ret == 2)
0186         ret = i2c_master_recv(dev->isp, val, 1);
0187 
0188     if (ret < 0) {
0189         dev_dbg(dev->dev, "%s: register 0x%04x read failed (%d)\n",
0190             __func__, reg, ret);
0191         return ret;
0192     }
0193 
0194     return 0;
0195 }
0196 
0197 static int ov490_write(struct rdacm21_device *dev, u16 reg, u8 val)
0198 {
0199     u8 buf[3] = { reg >> 8, reg, val };
0200     int ret;
0201 
0202     ret = i2c_master_send(dev->isp, buf, 3);
0203     if (ret < 0) {
0204         dev_err(dev->dev, "%s: register 0x%04x write failed (%d)\n",
0205             __func__, reg, ret);
0206         return ret;
0207     }
0208 
0209     return 0;
0210 }
0211 
0212 static int ov490_set_page(struct rdacm21_device *dev, u16 page)
0213 {
0214     u8 page_high = page >> 8;
0215     u8 page_low = page;
0216     int ret;
0217 
0218     if (page == dev->last_page)
0219         return 0;
0220 
0221     if (page_high != (dev->last_page >> 8)) {
0222         ret = ov490_write(dev, OV490_PAGE_HIGH_REG, page_high);
0223         if (ret)
0224             return ret;
0225     }
0226 
0227     if (page_low != (u8)dev->last_page) {
0228         ret = ov490_write(dev, OV490_PAGE_LOW_REG, page_low);
0229         if (ret)
0230             return ret;
0231     }
0232 
0233     dev->last_page = page;
0234     usleep_range(100, 150);
0235 
0236     return 0;
0237 }
0238 
0239 static int ov490_read_reg(struct rdacm21_device *dev, u32 reg, u8 *val)
0240 {
0241     int ret;
0242 
0243     ret = ov490_set_page(dev, reg >> 16);
0244     if (ret)
0245         return ret;
0246 
0247     ret = ov490_read(dev, (u16)reg, val);
0248     if (ret)
0249         return ret;
0250 
0251     dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, *val);
0252 
0253     return 0;
0254 }
0255 
0256 static int ov490_write_reg(struct rdacm21_device *dev, u32 reg, u8 val)
0257 {
0258     int ret;
0259 
0260     ret = ov490_set_page(dev, reg >> 16);
0261     if (ret)
0262         return ret;
0263 
0264     ret = ov490_write(dev, (u16)reg, val);
0265     if (ret)
0266         return ret;
0267 
0268     dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, val);
0269 
0270     return 0;
0271 }
0272 
0273 static int rdacm21_s_stream(struct v4l2_subdev *sd, int enable)
0274 {
0275     struct rdacm21_device *dev = sd_to_rdacm21(sd);
0276 
0277     /*
0278      * Enable serial link now that the ISP provides a valid pixel clock
0279      * to start serializing video data on the GMSL link.
0280      */
0281     return max9271_set_serial_link(&dev->serializer, enable);
0282 }
0283 
0284 static int rdacm21_enum_mbus_code(struct v4l2_subdev *sd,
0285                   struct v4l2_subdev_state *sd_state,
0286                   struct v4l2_subdev_mbus_code_enum *code)
0287 {
0288     if (code->pad || code->index > 0)
0289         return -EINVAL;
0290 
0291     code->code = MEDIA_BUS_FMT_YUYV8_1X16;
0292 
0293     return 0;
0294 }
0295 
0296 static int rdacm21_get_fmt(struct v4l2_subdev *sd,
0297                struct v4l2_subdev_state *sd_state,
0298                struct v4l2_subdev_format *format)
0299 {
0300     struct v4l2_mbus_framefmt *mf = &format->format;
0301     struct rdacm21_device *dev = sd_to_rdacm21(sd);
0302 
0303     if (format->pad)
0304         return -EINVAL;
0305 
0306     mf->width       = dev->fmt.width;
0307     mf->height      = dev->fmt.height;
0308     mf->code        = MEDIA_BUS_FMT_YUYV8_1X16;
0309     mf->colorspace      = V4L2_COLORSPACE_SRGB;
0310     mf->field       = V4L2_FIELD_NONE;
0311     mf->ycbcr_enc       = V4L2_YCBCR_ENC_601;
0312     mf->quantization    = V4L2_QUANTIZATION_FULL_RANGE;
0313     mf->xfer_func       = V4L2_XFER_FUNC_NONE;
0314 
0315     return 0;
0316 }
0317 
0318 static const struct v4l2_subdev_video_ops rdacm21_video_ops = {
0319     .s_stream   = rdacm21_s_stream,
0320 };
0321 
0322 static const struct v4l2_subdev_pad_ops rdacm21_subdev_pad_ops = {
0323     .enum_mbus_code = rdacm21_enum_mbus_code,
0324     .get_fmt    = rdacm21_get_fmt,
0325     .set_fmt    = rdacm21_get_fmt,
0326 };
0327 
0328 static const struct v4l2_subdev_ops rdacm21_subdev_ops = {
0329     .video      = &rdacm21_video_ops,
0330     .pad        = &rdacm21_subdev_pad_ops,
0331 };
0332 
0333 static void ov10640_power_up(struct rdacm21_device *dev)
0334 {
0335     /* Enable GPIO0#0 (reset) and GPIO1#0 (pwdn) as output lines. */
0336     ov490_write_reg(dev, OV490_GPIO_SEL0, OV490_GPIO0);
0337     ov490_write_reg(dev, OV490_GPIO_SEL1, OV490_SPWDN0);
0338     ov490_write_reg(dev, OV490_GPIO_DIRECTION0, OV490_GPIO0);
0339     ov490_write_reg(dev, OV490_GPIO_DIRECTION1, OV490_SPWDN0);
0340 
0341     /* Power up OV10640 and then reset it. */
0342     ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE1, OV490_SPWDN0);
0343     usleep_range(1500, 3000);
0344 
0345     ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, 0x00);
0346     usleep_range(1500, 3000);
0347     ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_GPIO0);
0348     usleep_range(3000, 5000);
0349 }
0350 
0351 static int ov10640_check_id(struct rdacm21_device *dev)
0352 {
0353     unsigned int i;
0354     u8 val;
0355 
0356     /* Read OV10640 ID to test communications. */
0357     for (i = 0; i < OV10640_PID_TIMEOUT; ++i) {
0358         ov490_write_reg(dev, OV490_SCCB_SLAVE0_DIR,
0359                 OV490_SCCB_SLAVE_READ);
0360         ov490_write_reg(dev, OV490_SCCB_SLAVE0_ADDR_HIGH,
0361                 OV10640_CHIP_ID >> 8);
0362         ov490_write_reg(dev, OV490_SCCB_SLAVE0_ADDR_LOW,
0363                 OV10640_CHIP_ID & 0xff);
0364 
0365         /*
0366          * Trigger SCCB slave transaction and give it some time
0367          * to complete.
0368          */
0369         ov490_write_reg(dev, OV490_HOST_CMD, OV490_HOST_CMD_TRIGGER);
0370         usleep_range(1000, 1500);
0371 
0372         ov490_read_reg(dev, OV490_SCCB_SLAVE0_DIR, &val);
0373         if (val == OV10640_ID_HIGH)
0374             break;
0375         usleep_range(1000, 1500);
0376     }
0377     if (i == OV10640_PID_TIMEOUT) {
0378         dev_err(dev->dev, "OV10640 ID mismatch: (0x%02x)\n", val);
0379         return -ENODEV;
0380     }
0381 
0382     dev_dbg(dev->dev, "OV10640 ID = 0x%2x\n", val);
0383 
0384     return 0;
0385 }
0386 
0387 static int ov490_initialize(struct rdacm21_device *dev)
0388 {
0389     u8 pid, ver, val;
0390     unsigned int i;
0391     int ret;
0392 
0393     ov10640_power_up(dev);
0394 
0395     /*
0396      * Read OV490 Id to test communications. Give it up to 40msec to
0397      * exit from reset.
0398      */
0399     for (i = 0; i < OV490_PID_TIMEOUT; ++i) {
0400         ret = ov490_read_reg(dev, OV490_PID, &pid);
0401         if (ret == 0)
0402             break;
0403         usleep_range(1000, 2000);
0404     }
0405     if (i == OV490_PID_TIMEOUT) {
0406         dev_err(dev->dev, "OV490 PID read failed (%d)\n", ret);
0407         return ret;
0408     }
0409 
0410     ret = ov490_read_reg(dev, OV490_VER, &ver);
0411     if (ret < 0)
0412         return ret;
0413 
0414     if (OV490_ID(pid, ver) != OV490_ID_VAL) {
0415         dev_err(dev->dev, "OV490 ID mismatch (0x%04x)\n",
0416             OV490_ID(pid, ver));
0417         return -ENODEV;
0418     }
0419 
0420     /* Wait for firmware boot by reading streamon status. */
0421     for (i = 0; i < OV490_OUTPUT_EN_TIMEOUT; ++i) {
0422         ov490_read_reg(dev, OV490_ODS_CTRL, &val);
0423         if (val == OV490_ODS_CTRL_FRAME_OUTPUT_EN)
0424             break;
0425         usleep_range(1000, 2000);
0426     }
0427     if (i == OV490_OUTPUT_EN_TIMEOUT) {
0428         dev_err(dev->dev, "Timeout waiting for firmware boot\n");
0429         return -ENODEV;
0430     }
0431 
0432     ret = ov10640_check_id(dev);
0433     if (ret)
0434         return ret;
0435 
0436     /* Program OV490 with register-value table. */
0437     for (i = 0; i < ARRAY_SIZE(ov490_regs_wizard); ++i) {
0438         ret = ov490_write(dev, ov490_regs_wizard[i].reg,
0439                   ov490_regs_wizard[i].val);
0440         if (ret < 0) {
0441             dev_err(dev->dev,
0442                 "%s: register %u (0x%04x) write failed (%d)\n",
0443                 __func__, i, ov490_regs_wizard[i].reg, ret);
0444 
0445             return -EIO;
0446         }
0447 
0448         usleep_range(100, 150);
0449     }
0450 
0451     /*
0452      * The ISP is programmed with the content of a serial flash memory.
0453      * Read the firmware configuration to reflect it through the V4L2 APIs.
0454      */
0455     ov490_read_reg(dev, OV490_ISP_HSIZE_HIGH, &val);
0456     dev->fmt.width = (val & 0xf) << 8;
0457     ov490_read_reg(dev, OV490_ISP_HSIZE_LOW, &val);
0458     dev->fmt.width |= (val & 0xff);
0459 
0460     ov490_read_reg(dev, OV490_ISP_VSIZE_HIGH, &val);
0461     dev->fmt.height = (val & 0xf) << 8;
0462     ov490_read_reg(dev, OV490_ISP_VSIZE_LOW, &val);
0463     dev->fmt.height |= val & 0xff;
0464 
0465     /* Set bus width to 12 bits with [0:11] ordering. */
0466     ov490_write_reg(dev, OV490_DVP_CTRL3, 0x10);
0467 
0468     dev_info(dev->dev, "Identified RDACM21 camera module\n");
0469 
0470     return 0;
0471 }
0472 
0473 static int rdacm21_initialize(struct rdacm21_device *dev)
0474 {
0475     int ret;
0476 
0477     max9271_wake_up(&dev->serializer);
0478 
0479     /* Enable reverse channel and disable the serial link. */
0480     ret = max9271_set_serial_link(&dev->serializer, false);
0481     if (ret)
0482         return ret;
0483 
0484     /* Configure I2C bus at 105Kbps speed and configure GMSL. */
0485     ret = max9271_configure_i2c(&dev->serializer,
0486                     MAX9271_I2CSLVSH_469NS_234NS |
0487                     MAX9271_I2CSLVTO_1024US |
0488                     MAX9271_I2CMSTBT_105KBPS);
0489     if (ret)
0490         return ret;
0491 
0492     ret = max9271_verify_id(&dev->serializer);
0493     if (ret)
0494         return ret;
0495 
0496     /*
0497      * Enable GPIO1 and hold OV490 in reset during max9271 configuration.
0498      * The reset signal has to be asserted for at least 250 useconds.
0499      */
0500     ret = max9271_enable_gpios(&dev->serializer, MAX9271_GPIO1OUT);
0501     if (ret)
0502         return ret;
0503 
0504     ret = max9271_clear_gpios(&dev->serializer, MAX9271_GPIO1OUT);
0505     if (ret)
0506         return ret;
0507     usleep_range(250, 500);
0508 
0509     ret = max9271_configure_gmsl_link(&dev->serializer);
0510     if (ret)
0511         return ret;
0512 
0513     ret = max9271_set_address(&dev->serializer, dev->addrs[0]);
0514     if (ret)
0515         return ret;
0516     dev->serializer.client->addr = dev->addrs[0];
0517 
0518     ret = max9271_set_translation(&dev->serializer, dev->addrs[1],
0519                       OV490_I2C_ADDRESS);
0520     if (ret)
0521         return ret;
0522     dev->isp->addr = dev->addrs[1];
0523 
0524     /* Release OV490 from reset and initialize it. */
0525     ret = max9271_set_gpios(&dev->serializer, MAX9271_GPIO1OUT);
0526     if (ret)
0527         return ret;
0528     usleep_range(3000, 5000);
0529 
0530     ret = ov490_initialize(dev);
0531     if (ret)
0532         return ret;
0533 
0534     /*
0535      * Set reverse channel high threshold to increase noise immunity.
0536      *
0537      * This should be compensated by increasing the reverse channel
0538      * amplitude on the remote deserializer side.
0539      */
0540     return max9271_set_high_threshold(&dev->serializer, true);
0541 }
0542 
0543 static int rdacm21_probe(struct i2c_client *client)
0544 {
0545     struct rdacm21_device *dev;
0546     struct fwnode_handle *ep;
0547     int ret;
0548 
0549     dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
0550     if (!dev)
0551         return -ENOMEM;
0552     dev->dev = &client->dev;
0553     dev->serializer.client = client;
0554 
0555     ret = of_property_read_u32_array(client->dev.of_node, "reg",
0556                      dev->addrs, 2);
0557     if (ret < 0) {
0558         dev_err(dev->dev, "Invalid DT reg property: %d\n", ret);
0559         return -EINVAL;
0560     }
0561 
0562     /* Create the dummy I2C client for the sensor. */
0563     dev->isp = i2c_new_dummy_device(client->adapter, OV490_I2C_ADDRESS);
0564     if (IS_ERR(dev->isp))
0565         return PTR_ERR(dev->isp);
0566 
0567     ret = rdacm21_initialize(dev);
0568     if (ret < 0)
0569         goto error;
0570 
0571     /* Initialize and register the subdevice. */
0572     v4l2_i2c_subdev_init(&dev->sd, client, &rdacm21_subdev_ops);
0573     dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
0574 
0575     v4l2_ctrl_handler_init(&dev->ctrls, 1);
0576     v4l2_ctrl_new_std(&dev->ctrls, NULL, V4L2_CID_PIXEL_RATE,
0577               OV10640_PIXEL_RATE, OV10640_PIXEL_RATE, 1,
0578               OV10640_PIXEL_RATE);
0579     dev->sd.ctrl_handler = &dev->ctrls;
0580 
0581     ret = dev->ctrls.error;
0582     if (ret)
0583         goto error_free_ctrls;
0584 
0585     dev->pad.flags = MEDIA_PAD_FL_SOURCE;
0586     dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
0587     ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad);
0588     if (ret < 0)
0589         goto error_free_ctrls;
0590 
0591     ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
0592     if (!ep) {
0593         dev_err(&client->dev,
0594             "Unable to get endpoint in node %pOF\n",
0595             client->dev.of_node);
0596         ret = -ENOENT;
0597         goto error_free_ctrls;
0598     }
0599     dev->sd.fwnode = ep;
0600 
0601     ret = v4l2_async_register_subdev(&dev->sd);
0602     if (ret)
0603         goto error_put_node;
0604 
0605     return 0;
0606 
0607 error_put_node:
0608     fwnode_handle_put(dev->sd.fwnode);
0609 error_free_ctrls:
0610     v4l2_ctrl_handler_free(&dev->ctrls);
0611 error:
0612     i2c_unregister_device(dev->isp);
0613 
0614     return ret;
0615 }
0616 
0617 static int rdacm21_remove(struct i2c_client *client)
0618 {
0619     struct rdacm21_device *dev = sd_to_rdacm21(i2c_get_clientdata(client));
0620 
0621     v4l2_async_unregister_subdev(&dev->sd);
0622     v4l2_ctrl_handler_free(&dev->ctrls);
0623     i2c_unregister_device(dev->isp);
0624     fwnode_handle_put(dev->sd.fwnode);
0625 
0626     return 0;
0627 }
0628 
0629 static const struct of_device_id rdacm21_of_ids[] = {
0630     { .compatible = "imi,rdacm21" },
0631     { }
0632 };
0633 MODULE_DEVICE_TABLE(of, rdacm21_of_ids);
0634 
0635 static struct i2c_driver rdacm21_i2c_driver = {
0636     .driver = {
0637         .name   = "rdacm21",
0638         .of_match_table = rdacm21_of_ids,
0639     },
0640     .probe_new  = rdacm21_probe,
0641     .remove     = rdacm21_remove,
0642 };
0643 
0644 module_i2c_driver(rdacm21_i2c_driver);
0645 
0646 MODULE_DESCRIPTION("GMSL Camera driver for RDACM21");
0647 MODULE_AUTHOR("Jacopo Mondi");
0648 MODULE_LICENSE("GPL v2");
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