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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * OmniVision OV96xx Camera Driver
0004  *
0005  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
0006  *
0007  * Based on ov772x camera driver:
0008  *
0009  * Copyright (C) 2008 Renesas Solutions Corp.
0010  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
0011  *
0012  * Based on ov7670 and soc_camera_platform driver,
0013  * transition from soc_camera to pxa_camera based on mt9m111
0014  *
0015  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
0016  * Copyright (C) 2008 Magnus Damm
0017  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
0018  */
0019 
0020 #include <linux/clk.h>
0021 #include <linux/init.h>
0022 #include <linux/module.h>
0023 #include <linux/i2c.h>
0024 #include <linux/slab.h>
0025 #include <linux/delay.h>
0026 #include <linux/v4l2-mediabus.h>
0027 #include <linux/videodev2.h>
0028 
0029 #include <media/v4l2-async.h>
0030 #include <media/v4l2-common.h>
0031 #include <media/v4l2-ctrls.h>
0032 #include <media/v4l2-device.h>
0033 #include <media/v4l2-event.h>
0034 
0035 #include <linux/gpio/consumer.h>
0036 
0037 #include "ov9640.h"
0038 
0039 #define to_ov9640_sensor(sd)    container_of(sd, struct ov9640_priv, subdev)
0040 
0041 /* default register setup */
0042 static const struct ov9640_reg ov9640_regs_dflt[] = {
0043     { OV9640_COM5,  OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
0044     { OV9640_COM6,  OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
0045             OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
0046     { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
0047     { OV9640_ACOM,  OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
0048     { OV9640_TSLB,  OV9640_TSLB_YUYV_UYVY },
0049     { OV9640_COM16, OV9640_COM16_RB_AVG },
0050 
0051     /* Gamma curve P */
0052     { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
0053     { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
0054     { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
0055     { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
0056 
0057     /* Gamma curve T */
0058     { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
0059     { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
0060     { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
0061     { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
0062 };
0063 
0064 /* Configurations
0065  * NOTE: for YUV, alter the following registers:
0066  *      COM12 |= OV9640_COM12_YUV_AVG
0067  *
0068  *   for RGB, alter the following registers:
0069  *      COM7  |= OV9640_COM7_RGB
0070  *      COM13 |= OV9640_COM13_RGB_AVG
0071  *      COM15 |= proper RGB color encoding mode
0072  */
0073 static const struct ov9640_reg ov9640_regs_qqcif[] = {
0074     { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
0075     { OV9640_COM1,  OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
0076     { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
0077     { OV9640_COM7,  OV9640_COM7_QCIF },
0078     { OV9640_COM12, OV9640_COM12_RSVD },
0079     { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
0080     { OV9640_COM15, OV9640_COM15_OR_10F0 },
0081 };
0082 
0083 static const struct ov9640_reg ov9640_regs_qqvga[] = {
0084     { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
0085     { OV9640_COM1,  OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
0086     { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
0087     { OV9640_COM7,  OV9640_COM7_QVGA },
0088     { OV9640_COM12, OV9640_COM12_RSVD },
0089     { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
0090     { OV9640_COM15, OV9640_COM15_OR_10F0 },
0091 };
0092 
0093 static const struct ov9640_reg ov9640_regs_qcif[] = {
0094     { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
0095     { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
0096     { OV9640_COM7,  OV9640_COM7_QCIF },
0097     { OV9640_COM12, OV9640_COM12_RSVD },
0098     { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
0099     { OV9640_COM15, OV9640_COM15_OR_10F0 },
0100 };
0101 
0102 static const struct ov9640_reg ov9640_regs_qvga[] = {
0103     { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
0104     { OV9640_COM4,  OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
0105     { OV9640_COM7,  OV9640_COM7_QVGA },
0106     { OV9640_COM12, OV9640_COM12_RSVD },
0107     { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
0108     { OV9640_COM15, OV9640_COM15_OR_10F0 },
0109 };
0110 
0111 static const struct ov9640_reg ov9640_regs_cif[] = {
0112     { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
0113     { OV9640_COM3,  OV9640_COM3_VP },
0114     { OV9640_COM7,  OV9640_COM7_CIF },
0115     { OV9640_COM12, OV9640_COM12_RSVD },
0116     { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
0117     { OV9640_COM15, OV9640_COM15_OR_10F0 },
0118 };
0119 
0120 static const struct ov9640_reg ov9640_regs_vga[] = {
0121     { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
0122     { OV9640_COM3,  OV9640_COM3_VP },
0123     { OV9640_COM7,  OV9640_COM7_VGA },
0124     { OV9640_COM12, OV9640_COM12_RSVD },
0125     { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
0126     { OV9640_COM15, OV9640_COM15_OR_10F0 },
0127 };
0128 
0129 static const struct ov9640_reg ov9640_regs_sxga[] = {
0130     { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
0131     { OV9640_COM3,  OV9640_COM3_VP },
0132     { OV9640_COM7,  0 },
0133     { OV9640_COM12, OV9640_COM12_RSVD },
0134     { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
0135     { OV9640_COM15, OV9640_COM15_OR_10F0 },
0136 };
0137 
0138 static const struct ov9640_reg ov9640_regs_yuv[] = {
0139     { OV9640_MTX1,  0x58 },
0140     { OV9640_MTX2,  0x48 },
0141     { OV9640_MTX3,  0x10 },
0142     { OV9640_MTX4,  0x28 },
0143     { OV9640_MTX5,  0x48 },
0144     { OV9640_MTX6,  0x70 },
0145     { OV9640_MTX7,  0x40 },
0146     { OV9640_MTX8,  0x40 },
0147     { OV9640_MTX9,  0x40 },
0148     { OV9640_MTXS,  0x0f },
0149 };
0150 
0151 static const struct ov9640_reg ov9640_regs_rgb[] = {
0152     { OV9640_MTX1,  0x71 },
0153     { OV9640_MTX2,  0x3e },
0154     { OV9640_MTX3,  0x0c },
0155     { OV9640_MTX4,  0x33 },
0156     { OV9640_MTX5,  0x72 },
0157     { OV9640_MTX6,  0x00 },
0158     { OV9640_MTX7,  0x2b },
0159     { OV9640_MTX8,  0x66 },
0160     { OV9640_MTX9,  0xd2 },
0161     { OV9640_MTXS,  0x65 },
0162 };
0163 
0164 static const u32 ov9640_codes[] = {
0165     MEDIA_BUS_FMT_UYVY8_2X8,
0166     MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
0167     MEDIA_BUS_FMT_RGB565_2X8_LE,
0168 };
0169 
0170 /* read a register */
0171 static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
0172 {
0173     int ret;
0174     u8 data = reg;
0175     struct i2c_msg msg = {
0176         .addr   = client->addr,
0177         .flags  = 0,
0178         .len    = 1,
0179         .buf    = &data,
0180     };
0181 
0182     ret = i2c_transfer(client->adapter, &msg, 1);
0183     if (ret < 0)
0184         goto err;
0185 
0186     msg.flags = I2C_M_RD;
0187     ret = i2c_transfer(client->adapter, &msg, 1);
0188     if (ret < 0)
0189         goto err;
0190 
0191     *val = data;
0192     return 0;
0193 
0194 err:
0195     dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
0196     return ret;
0197 }
0198 
0199 /* write a register */
0200 static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
0201 {
0202     int ret;
0203     u8 _val;
0204     unsigned char data[2] = { reg, val };
0205     struct i2c_msg msg = {
0206         .addr   = client->addr,
0207         .flags  = 0,
0208         .len    = 2,
0209         .buf    = data,
0210     };
0211 
0212     ret = i2c_transfer(client->adapter, &msg, 1);
0213     if (ret < 0) {
0214         dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
0215         return ret;
0216     }
0217 
0218     /* we have to read the register back ... no idea why, maybe HW bug */
0219     ret = ov9640_reg_read(client, reg, &_val);
0220     if (ret)
0221         dev_err(&client->dev,
0222             "Failed reading back register 0x%02x!\n", reg);
0223 
0224     return 0;
0225 }
0226 
0227 
0228 /* Read a register, alter its bits, write it back */
0229 static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
0230 {
0231     u8 val;
0232     int ret;
0233 
0234     ret = ov9640_reg_read(client, reg, &val);
0235     if (ret) {
0236         dev_err(&client->dev,
0237             "[Read]-Modify-Write of register %02x failed!\n", reg);
0238         return ret;
0239     }
0240 
0241     val |= set;
0242     val &= ~unset;
0243 
0244     ret = ov9640_reg_write(client, reg, val);
0245     if (ret)
0246         dev_err(&client->dev,
0247             "Read-Modify-[Write] of register %02x failed!\n", reg);
0248 
0249     return ret;
0250 }
0251 
0252 /* Soft reset the camera. This has nothing to do with the RESET pin! */
0253 static int ov9640_reset(struct i2c_client *client)
0254 {
0255     int ret;
0256 
0257     ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
0258     if (ret)
0259         dev_err(&client->dev,
0260             "An error occurred while entering soft reset!\n");
0261 
0262     return ret;
0263 }
0264 
0265 /* Start/Stop streaming from the device */
0266 static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
0267 {
0268     return 0;
0269 }
0270 
0271 /* Set status of additional camera capabilities */
0272 static int ov9640_s_ctrl(struct v4l2_ctrl *ctrl)
0273 {
0274     struct ov9640_priv *priv = container_of(ctrl->handler,
0275                         struct ov9640_priv, hdl);
0276     struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
0277 
0278     switch (ctrl->id) {
0279     case V4L2_CID_VFLIP:
0280         if (ctrl->val)
0281             return ov9640_reg_rmw(client, OV9640_MVFP,
0282                           OV9640_MVFP_V, 0);
0283         return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_V);
0284     case V4L2_CID_HFLIP:
0285         if (ctrl->val)
0286             return ov9640_reg_rmw(client, OV9640_MVFP,
0287                           OV9640_MVFP_H, 0);
0288         return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_H);
0289     }
0290 
0291     return -EINVAL;
0292 }
0293 
0294 #ifdef CONFIG_VIDEO_ADV_DEBUG
0295 static int ov9640_get_register(struct v4l2_subdev *sd,
0296                 struct v4l2_dbg_register *reg)
0297 {
0298     struct i2c_client *client = v4l2_get_subdevdata(sd);
0299     int ret;
0300     u8 val;
0301 
0302     if (reg->reg & ~0xff)
0303         return -EINVAL;
0304 
0305     reg->size = 1;
0306 
0307     ret = ov9640_reg_read(client, reg->reg, &val);
0308     if (ret)
0309         return ret;
0310 
0311     reg->val = (__u64)val;
0312 
0313     return 0;
0314 }
0315 
0316 static int ov9640_set_register(struct v4l2_subdev *sd,
0317                 const struct v4l2_dbg_register *reg)
0318 {
0319     struct i2c_client *client = v4l2_get_subdevdata(sd);
0320 
0321     if (reg->reg & ~0xff || reg->val & ~0xff)
0322         return -EINVAL;
0323 
0324     return ov9640_reg_write(client, reg->reg, reg->val);
0325 }
0326 #endif
0327 
0328 static int ov9640_s_power(struct v4l2_subdev *sd, int on)
0329 {
0330     struct ov9640_priv *priv = to_ov9640_sensor(sd);
0331     int ret = 0;
0332 
0333     if (on) {
0334         gpiod_set_value(priv->gpio_power, 1);
0335         usleep_range(1000, 2000);
0336         ret = clk_prepare_enable(priv->clk);
0337         usleep_range(1000, 2000);
0338         gpiod_set_value(priv->gpio_reset, 0);
0339     } else {
0340         gpiod_set_value(priv->gpio_reset, 1);
0341         usleep_range(1000, 2000);
0342         clk_disable_unprepare(priv->clk);
0343         usleep_range(1000, 2000);
0344         gpiod_set_value(priv->gpio_power, 0);
0345     }
0346 
0347     return ret;
0348 }
0349 
0350 /* select nearest higher resolution for capture */
0351 static void ov9640_res_roundup(u32 *width, u32 *height)
0352 {
0353     unsigned int i;
0354     enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
0355     static const u32 res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
0356     static const u32 res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
0357 
0358     for (i = 0; i < ARRAY_SIZE(res_x); i++) {
0359         if (res_x[i] >= *width && res_y[i] >= *height) {
0360             *width = res_x[i];
0361             *height = res_y[i];
0362             return;
0363         }
0364     }
0365 
0366     *width = res_x[SXGA];
0367     *height = res_y[SXGA];
0368 }
0369 
0370 /* Prepare necessary register changes depending on color encoding */
0371 static void ov9640_alter_regs(u32 code,
0372                   struct ov9640_reg_alt *alt)
0373 {
0374     switch (code) {
0375     default:
0376     case MEDIA_BUS_FMT_UYVY8_2X8:
0377         alt->com12  = OV9640_COM12_YUV_AVG;
0378         alt->com13  = OV9640_COM13_Y_DELAY_EN |
0379                     OV9640_COM13_YUV_DLY(0x01);
0380         break;
0381     case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
0382         alt->com7   = OV9640_COM7_RGB;
0383         alt->com13  = OV9640_COM13_RGB_AVG;
0384         alt->com15  = OV9640_COM15_RGB_555;
0385         break;
0386     case MEDIA_BUS_FMT_RGB565_2X8_LE:
0387         alt->com7   = OV9640_COM7_RGB;
0388         alt->com13  = OV9640_COM13_RGB_AVG;
0389         alt->com15  = OV9640_COM15_RGB_565;
0390         break;
0391     }
0392 }
0393 
0394 /* Setup registers according to resolution and color encoding */
0395 static int ov9640_write_regs(struct i2c_client *client, u32 width,
0396         u32 code, struct ov9640_reg_alt *alts)
0397 {
0398     const struct ov9640_reg *ov9640_regs, *matrix_regs;
0399     unsigned int        ov9640_regs_len, matrix_regs_len;
0400     unsigned int        i;
0401     int         ret;
0402     u8          val;
0403 
0404     /* select register configuration for given resolution */
0405     switch (width) {
0406     case W_QQCIF:
0407         ov9640_regs = ov9640_regs_qqcif;
0408         ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
0409         break;
0410     case W_QQVGA:
0411         ov9640_regs = ov9640_regs_qqvga;
0412         ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
0413         break;
0414     case W_QCIF:
0415         ov9640_regs = ov9640_regs_qcif;
0416         ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
0417         break;
0418     case W_QVGA:
0419         ov9640_regs = ov9640_regs_qvga;
0420         ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
0421         break;
0422     case W_CIF:
0423         ov9640_regs = ov9640_regs_cif;
0424         ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
0425         break;
0426     case W_VGA:
0427         ov9640_regs = ov9640_regs_vga;
0428         ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
0429         break;
0430     case W_SXGA:
0431         ov9640_regs = ov9640_regs_sxga;
0432         ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
0433         break;
0434     default:
0435         dev_err(&client->dev, "Failed to select resolution!\n");
0436         return -EINVAL;
0437     }
0438 
0439     /* select color matrix configuration for given color encoding */
0440     if (code == MEDIA_BUS_FMT_UYVY8_2X8) {
0441         matrix_regs = ov9640_regs_yuv;
0442         matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
0443     } else {
0444         matrix_regs = ov9640_regs_rgb;
0445         matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
0446     }
0447 
0448     /* write register settings into the module */
0449     for (i = 0; i < ov9640_regs_len; i++) {
0450         val = ov9640_regs[i].val;
0451 
0452         switch (ov9640_regs[i].reg) {
0453         case OV9640_COM7:
0454             val |= alts->com7;
0455             break;
0456         case OV9640_COM12:
0457             val |= alts->com12;
0458             break;
0459         case OV9640_COM13:
0460             val |= alts->com13;
0461             break;
0462         case OV9640_COM15:
0463             val |= alts->com15;
0464             break;
0465         }
0466 
0467         ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
0468         if (ret)
0469             return ret;
0470     }
0471 
0472     /* write color matrix configuration into the module */
0473     for (i = 0; i < matrix_regs_len; i++) {
0474         ret = ov9640_reg_write(client, matrix_regs[i].reg,
0475                        matrix_regs[i].val);
0476         if (ret)
0477             return ret;
0478     }
0479 
0480     return 0;
0481 }
0482 
0483 /* program default register values */
0484 static int ov9640_prog_dflt(struct i2c_client *client)
0485 {
0486     unsigned int i;
0487     int ret;
0488 
0489     for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
0490         ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
0491                        ov9640_regs_dflt[i].val);
0492         if (ret)
0493             return ret;
0494     }
0495 
0496     /* wait for the changes to actually happen, 140ms are not enough yet */
0497     msleep(150);
0498 
0499     return 0;
0500 }
0501 
0502 /* set the format we will capture in */
0503 static int ov9640_s_fmt(struct v4l2_subdev *sd,
0504             struct v4l2_mbus_framefmt *mf)
0505 {
0506     struct i2c_client *client = v4l2_get_subdevdata(sd);
0507     struct ov9640_reg_alt alts = {0};
0508     int ret;
0509 
0510     ov9640_alter_regs(mf->code, &alts);
0511 
0512     ov9640_reset(client);
0513 
0514     ret = ov9640_prog_dflt(client);
0515     if (ret)
0516         return ret;
0517 
0518     return ov9640_write_regs(client, mf->width, mf->code, &alts);
0519 }
0520 
0521 static int ov9640_set_fmt(struct v4l2_subdev *sd,
0522         struct v4l2_subdev_state *sd_state,
0523         struct v4l2_subdev_format *format)
0524 {
0525     struct v4l2_mbus_framefmt *mf = &format->format;
0526 
0527     if (format->pad)
0528         return -EINVAL;
0529 
0530     ov9640_res_roundup(&mf->width, &mf->height);
0531 
0532     mf->field = V4L2_FIELD_NONE;
0533 
0534     switch (mf->code) {
0535     case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
0536     case MEDIA_BUS_FMT_RGB565_2X8_LE:
0537         mf->colorspace = V4L2_COLORSPACE_SRGB;
0538         break;
0539     default:
0540         mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
0541         fallthrough;
0542     case MEDIA_BUS_FMT_UYVY8_2X8:
0543         mf->colorspace = V4L2_COLORSPACE_JPEG;
0544         break;
0545     }
0546 
0547     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
0548         return ov9640_s_fmt(sd, mf);
0549 
0550     sd_state->pads->try_fmt = *mf;
0551 
0552     return 0;
0553 }
0554 
0555 static int ov9640_enum_mbus_code(struct v4l2_subdev *sd,
0556         struct v4l2_subdev_state *sd_state,
0557         struct v4l2_subdev_mbus_code_enum *code)
0558 {
0559     if (code->pad || code->index >= ARRAY_SIZE(ov9640_codes))
0560         return -EINVAL;
0561 
0562     code->code = ov9640_codes[code->index];
0563 
0564     return 0;
0565 }
0566 
0567 static int ov9640_get_selection(struct v4l2_subdev *sd,
0568         struct v4l2_subdev_state *sd_state,
0569         struct v4l2_subdev_selection *sel)
0570 {
0571     if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
0572         return -EINVAL;
0573 
0574     sel->r.left = 0;
0575     sel->r.top = 0;
0576     switch (sel->target) {
0577     case V4L2_SEL_TGT_CROP_BOUNDS:
0578     case V4L2_SEL_TGT_CROP:
0579         sel->r.width = W_SXGA;
0580         sel->r.height = H_SXGA;
0581         return 0;
0582     default:
0583         return -EINVAL;
0584     }
0585 }
0586 
0587 static int ov9640_video_probe(struct i2c_client *client)
0588 {
0589     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0590     struct ov9640_priv *priv = to_ov9640_sensor(sd);
0591     u8      pid, ver, midh, midl;
0592     const char  *devname;
0593     int     ret;
0594 
0595     ret = ov9640_s_power(&priv->subdev, 1);
0596     if (ret < 0)
0597         return ret;
0598 
0599     /*
0600      * check and show product ID and manufacturer ID
0601      */
0602 
0603     ret = ov9640_reg_read(client, OV9640_PID, &pid);
0604     if (!ret)
0605         ret = ov9640_reg_read(client, OV9640_VER, &ver);
0606     if (!ret)
0607         ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
0608     if (!ret)
0609         ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
0610     if (ret)
0611         goto done;
0612 
0613     switch (VERSION(pid, ver)) {
0614     case OV9640_V2:
0615         devname     = "ov9640";
0616         priv->revision  = 2;
0617         break;
0618     case OV9640_V3:
0619         devname     = "ov9640";
0620         priv->revision  = 3;
0621         break;
0622     default:
0623         dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
0624         ret = -ENODEV;
0625         goto done;
0626     }
0627 
0628     dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
0629          devname, pid, ver, midh, midl);
0630 
0631     ret = v4l2_ctrl_handler_setup(&priv->hdl);
0632 
0633 done:
0634     ov9640_s_power(&priv->subdev, 0);
0635     return ret;
0636 }
0637 
0638 static const struct v4l2_ctrl_ops ov9640_ctrl_ops = {
0639     .s_ctrl = ov9640_s_ctrl,
0640 };
0641 
0642 static const struct v4l2_subdev_core_ops ov9640_core_ops = {
0643 #ifdef CONFIG_VIDEO_ADV_DEBUG
0644     .g_register     = ov9640_get_register,
0645     .s_register     = ov9640_set_register,
0646 #endif
0647     .s_power        = ov9640_s_power,
0648 };
0649 
0650 /* Request bus settings on camera side */
0651 static int ov9640_get_mbus_config(struct v4l2_subdev *sd,
0652                   unsigned int pad,
0653                   struct v4l2_mbus_config *cfg)
0654 {
0655     cfg->type = V4L2_MBUS_PARALLEL;
0656     cfg->bus.parallel.flags = V4L2_MBUS_PCLK_SAMPLE_RISING |
0657                   V4L2_MBUS_MASTER |
0658                   V4L2_MBUS_VSYNC_ACTIVE_HIGH |
0659                   V4L2_MBUS_HSYNC_ACTIVE_HIGH |
0660                   V4L2_MBUS_DATA_ACTIVE_HIGH;
0661 
0662     return 0;
0663 }
0664 
0665 static const struct v4l2_subdev_video_ops ov9640_video_ops = {
0666     .s_stream   = ov9640_s_stream,
0667 };
0668 
0669 static const struct v4l2_subdev_pad_ops ov9640_pad_ops = {
0670     .enum_mbus_code = ov9640_enum_mbus_code,
0671     .get_selection  = ov9640_get_selection,
0672     .set_fmt    = ov9640_set_fmt,
0673     .get_mbus_config = ov9640_get_mbus_config,
0674 };
0675 
0676 static const struct v4l2_subdev_ops ov9640_subdev_ops = {
0677     .core   = &ov9640_core_ops,
0678     .video  = &ov9640_video_ops,
0679     .pad    = &ov9640_pad_ops,
0680 };
0681 
0682 /*
0683  * i2c_driver function
0684  */
0685 static int ov9640_probe(struct i2c_client *client,
0686             const struct i2c_device_id *did)
0687 {
0688     struct ov9640_priv *priv;
0689     int ret;
0690 
0691     priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
0692     if (!priv)
0693         return -ENOMEM;
0694 
0695     priv->gpio_power = devm_gpiod_get(&client->dev, "Camera power",
0696                       GPIOD_OUT_LOW);
0697     if (IS_ERR(priv->gpio_power)) {
0698         ret = PTR_ERR(priv->gpio_power);
0699         return ret;
0700     }
0701 
0702     priv->gpio_reset = devm_gpiod_get(&client->dev, "Camera reset",
0703                       GPIOD_OUT_HIGH);
0704     if (IS_ERR(priv->gpio_reset)) {
0705         ret = PTR_ERR(priv->gpio_reset);
0706         return ret;
0707     }
0708 
0709     v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
0710 
0711     v4l2_ctrl_handler_init(&priv->hdl, 2);
0712     v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
0713               V4L2_CID_VFLIP, 0, 1, 1, 0);
0714     v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
0715               V4L2_CID_HFLIP, 0, 1, 1, 0);
0716 
0717     if (priv->hdl.error) {
0718         ret = priv->hdl.error;
0719         goto ectrlinit;
0720     }
0721 
0722     priv->subdev.ctrl_handler = &priv->hdl;
0723 
0724     priv->clk = devm_clk_get(&client->dev, "mclk");
0725     if (IS_ERR(priv->clk)) {
0726         ret = PTR_ERR(priv->clk);
0727         goto ectrlinit;
0728     }
0729 
0730     ret = ov9640_video_probe(client);
0731     if (ret)
0732         goto ectrlinit;
0733 
0734     priv->subdev.dev = &client->dev;
0735     ret = v4l2_async_register_subdev(&priv->subdev);
0736     if (ret)
0737         goto ectrlinit;
0738 
0739     return 0;
0740 
0741 ectrlinit:
0742     v4l2_ctrl_handler_free(&priv->hdl);
0743 
0744     return ret;
0745 }
0746 
0747 static int ov9640_remove(struct i2c_client *client)
0748 {
0749     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0750     struct ov9640_priv *priv = to_ov9640_sensor(sd);
0751 
0752     v4l2_async_unregister_subdev(&priv->subdev);
0753     v4l2_ctrl_handler_free(&priv->hdl);
0754 
0755     return 0;
0756 }
0757 
0758 static const struct i2c_device_id ov9640_id[] = {
0759     { "ov9640", 0 },
0760     { }
0761 };
0762 MODULE_DEVICE_TABLE(i2c, ov9640_id);
0763 
0764 static struct i2c_driver ov9640_i2c_driver = {
0765     .driver = {
0766         .name = "ov9640",
0767     },
0768     .probe    = ov9640_probe,
0769     .remove   = ov9640_remove,
0770     .id_table = ov9640_id,
0771 };
0772 
0773 module_i2c_driver(ov9640_i2c_driver);
0774 
0775 MODULE_DESCRIPTION("OmniVision OV96xx CMOS Image Sensor driver");
0776 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
0777 MODULE_LICENSE("GPL v2");
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