0001
0002
0003
0004
0005
0006
0007 #include <asm/unaligned.h>
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/i2c.h>
0012 #include <linux/module.h>
0013 #include <linux/pm_runtime.h>
0014
0015 #include <media/v4l2-ctrls.h>
0016 #include <media/v4l2-fwnode.h>
0017 #include <media/v4l2-subdev.h>
0018
0019
0020 #define OV9282_REG_MODE_SELECT 0x0100
0021 #define OV9282_MODE_STANDBY 0x00
0022 #define OV9282_MODE_STREAMING 0x01
0023
0024
0025 #define OV9282_REG_LPFR 0x380e
0026
0027
0028 #define OV9282_REG_ID 0x300a
0029 #define OV9282_ID 0x9281
0030
0031
0032 #define OV9282_REG_EXPOSURE 0x3500
0033 #define OV9282_EXPOSURE_MIN 1
0034 #define OV9282_EXPOSURE_OFFSET 12
0035 #define OV9282_EXPOSURE_STEP 1
0036 #define OV9282_EXPOSURE_DEFAULT 0x0282
0037
0038
0039 #define OV9282_REG_AGAIN 0x3509
0040 #define OV9282_AGAIN_MIN 0x10
0041 #define OV9282_AGAIN_MAX 0xff
0042 #define OV9282_AGAIN_STEP 1
0043 #define OV9282_AGAIN_DEFAULT 0x10
0044
0045
0046 #define OV9282_REG_HOLD 0x3308
0047
0048
0049 #define OV9282_INCLK_RATE 24000000
0050
0051
0052 #define OV9282_LINK_FREQ 400000000
0053 #define OV9282_NUM_DATA_LANES 2
0054
0055 #define OV9282_REG_MIN 0x00
0056 #define OV9282_REG_MAX 0xfffff
0057
0058
0059
0060
0061
0062
0063 struct ov9282_reg {
0064 u16 address;
0065 u8 val;
0066 };
0067
0068
0069
0070
0071
0072
0073 struct ov9282_reg_list {
0074 u32 num_of_regs;
0075 const struct ov9282_reg *regs;
0076 };
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091 struct ov9282_mode {
0092 u32 width;
0093 u32 height;
0094 u32 code;
0095 u32 hblank;
0096 u32 vblank;
0097 u32 vblank_min;
0098 u32 vblank_max;
0099 u64 pclk;
0100 u32 link_freq_idx;
0101 struct ov9282_reg_list reg_list;
0102 };
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124 struct ov9282 {
0125 struct device *dev;
0126 struct i2c_client *client;
0127 struct v4l2_subdev sd;
0128 struct media_pad pad;
0129 struct gpio_desc *reset_gpio;
0130 struct clk *inclk;
0131 struct v4l2_ctrl_handler ctrl_handler;
0132 struct v4l2_ctrl *link_freq_ctrl;
0133 struct v4l2_ctrl *pclk_ctrl;
0134 struct v4l2_ctrl *hblank_ctrl;
0135 struct v4l2_ctrl *vblank_ctrl;
0136 struct {
0137 struct v4l2_ctrl *exp_ctrl;
0138 struct v4l2_ctrl *again_ctrl;
0139 };
0140 u32 vblank;
0141 const struct ov9282_mode *cur_mode;
0142 struct mutex mutex;
0143 bool streaming;
0144 };
0145
0146 static const s64 link_freq[] = {
0147 OV9282_LINK_FREQ,
0148 };
0149
0150
0151 static const struct ov9282_reg mode_1280x720_regs[] = {
0152 {0x0302, 0x32},
0153 {0x030d, 0x50},
0154 {0x030e, 0x02},
0155 {0x3001, 0x00},
0156 {0x3004, 0x00},
0157 {0x3005, 0x00},
0158 {0x3006, 0x04},
0159 {0x3011, 0x0a},
0160 {0x3013, 0x18},
0161 {0x301c, 0xf0},
0162 {0x3022, 0x01},
0163 {0x3030, 0x10},
0164 {0x3039, 0x32},
0165 {0x303a, 0x00},
0166 {0x3500, 0x00},
0167 {0x3501, 0x5f},
0168 {0x3502, 0x1e},
0169 {0x3503, 0x08},
0170 {0x3505, 0x8c},
0171 {0x3507, 0x03},
0172 {0x3508, 0x00},
0173 {0x3509, 0x10},
0174 {0x3610, 0x80},
0175 {0x3611, 0xa0},
0176 {0x3620, 0x6e},
0177 {0x3632, 0x56},
0178 {0x3633, 0x78},
0179 {0x3666, 0x00},
0180 {0x366f, 0x5a},
0181 {0x3680, 0x84},
0182 {0x3712, 0x80},
0183 {0x372d, 0x22},
0184 {0x3731, 0x80},
0185 {0x3732, 0x30},
0186 {0x3778, 0x00},
0187 {0x377d, 0x22},
0188 {0x3788, 0x02},
0189 {0x3789, 0xa4},
0190 {0x378a, 0x00},
0191 {0x378b, 0x4a},
0192 {0x3799, 0x20},
0193 {0x3800, 0x00},
0194 {0x3801, 0x00},
0195 {0x3802, 0x00},
0196 {0x3803, 0x00},
0197 {0x3804, 0x05},
0198 {0x3805, 0x0f},
0199 {0x3806, 0x02},
0200 {0x3807, 0xdf},
0201 {0x3808, 0x05},
0202 {0x3809, 0x00},
0203 {0x380a, 0x02},
0204 {0x380b, 0xd0},
0205 {0x380c, 0x05},
0206 {0x380d, 0xfa},
0207 {0x380e, 0x06},
0208 {0x380f, 0xce},
0209 {0x3810, 0x00},
0210 {0x3811, 0x08},
0211 {0x3812, 0x00},
0212 {0x3813, 0x08},
0213 {0x3814, 0x11},
0214 {0x3815, 0x11},
0215 {0x3820, 0x3c},
0216 {0x3821, 0x84},
0217 {0x3881, 0x42},
0218 {0x38a8, 0x02},
0219 {0x38a9, 0x80},
0220 {0x38b1, 0x00},
0221 {0x38c4, 0x00},
0222 {0x38c5, 0xc0},
0223 {0x38c6, 0x04},
0224 {0x38c7, 0x80},
0225 {0x3920, 0xff},
0226 {0x4003, 0x40},
0227 {0x4008, 0x02},
0228 {0x4009, 0x05},
0229 {0x400c, 0x00},
0230 {0x400d, 0x03},
0231 {0x4010, 0x40},
0232 {0x4043, 0x40},
0233 {0x4307, 0x30},
0234 {0x4317, 0x00},
0235 {0x4501, 0x00},
0236 {0x4507, 0x00},
0237 {0x4509, 0x80},
0238 {0x450a, 0x08},
0239 {0x4601, 0x04},
0240 {0x470f, 0x00},
0241 {0x4f07, 0x00},
0242 {0x4800, 0x20},
0243 {0x5000, 0x9f},
0244 {0x5001, 0x00},
0245 {0x5e00, 0x00},
0246 {0x5d00, 0x07},
0247 {0x5d01, 0x00},
0248 {0x0101, 0x01},
0249 {0x1000, 0x03},
0250 {0x5a08, 0x84},
0251 };
0252
0253
0254 static const struct ov9282_mode supported_mode = {
0255 .width = 1280,
0256 .height = 720,
0257 .hblank = 250,
0258 .vblank = 1022,
0259 .vblank_min = 151,
0260 .vblank_max = 51540,
0261 .pclk = 160000000,
0262 .link_freq_idx = 0,
0263 .code = MEDIA_BUS_FMT_Y10_1X10,
0264 .reg_list = {
0265 .num_of_regs = ARRAY_SIZE(mode_1280x720_regs),
0266 .regs = mode_1280x720_regs,
0267 },
0268 };
0269
0270
0271
0272
0273
0274
0275
0276 static inline struct ov9282 *to_ov9282(struct v4l2_subdev *subdev)
0277 {
0278 return container_of(subdev, struct ov9282, sd);
0279 }
0280
0281
0282
0283
0284
0285
0286
0287
0288
0289
0290 static int ov9282_read_reg(struct ov9282 *ov9282, u16 reg, u32 len, u32 *val)
0291 {
0292 struct i2c_client *client = v4l2_get_subdevdata(&ov9282->sd);
0293 struct i2c_msg msgs[2] = {0};
0294 u8 addr_buf[2] = {0};
0295 u8 data_buf[4] = {0};
0296 int ret;
0297
0298 if (WARN_ON(len > 4))
0299 return -EINVAL;
0300
0301 put_unaligned_be16(reg, addr_buf);
0302
0303
0304 msgs[0].addr = client->addr;
0305 msgs[0].flags = 0;
0306 msgs[0].len = ARRAY_SIZE(addr_buf);
0307 msgs[0].buf = addr_buf;
0308
0309
0310 msgs[1].addr = client->addr;
0311 msgs[1].flags = I2C_M_RD;
0312 msgs[1].len = len;
0313 msgs[1].buf = &data_buf[4 - len];
0314
0315 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0316 if (ret != ARRAY_SIZE(msgs))
0317 return -EIO;
0318
0319 *val = get_unaligned_be32(data_buf);
0320
0321 return 0;
0322 }
0323
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333 static int ov9282_write_reg(struct ov9282 *ov9282, u16 reg, u32 len, u32 val)
0334 {
0335 struct i2c_client *client = v4l2_get_subdevdata(&ov9282->sd);
0336 u8 buf[6] = {0};
0337
0338 if (WARN_ON(len > 4))
0339 return -EINVAL;
0340
0341 put_unaligned_be16(reg, buf);
0342 put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
0343 if (i2c_master_send(client, buf, len + 2) != len + 2)
0344 return -EIO;
0345
0346 return 0;
0347 }
0348
0349
0350
0351
0352
0353
0354
0355
0356
0357 static int ov9282_write_regs(struct ov9282 *ov9282,
0358 const struct ov9282_reg *regs, u32 len)
0359 {
0360 unsigned int i;
0361 int ret;
0362
0363 for (i = 0; i < len; i++) {
0364 ret = ov9282_write_reg(ov9282, regs[i].address, 1, regs[i].val);
0365 if (ret)
0366 return ret;
0367 }
0368
0369 return 0;
0370 }
0371
0372
0373
0374
0375
0376
0377
0378
0379 static int ov9282_update_controls(struct ov9282 *ov9282,
0380 const struct ov9282_mode *mode)
0381 {
0382 int ret;
0383
0384 ret = __v4l2_ctrl_s_ctrl(ov9282->link_freq_ctrl, mode->link_freq_idx);
0385 if (ret)
0386 return ret;
0387
0388 ret = __v4l2_ctrl_s_ctrl(ov9282->hblank_ctrl, mode->hblank);
0389 if (ret)
0390 return ret;
0391
0392 return __v4l2_ctrl_modify_range(ov9282->vblank_ctrl, mode->vblank_min,
0393 mode->vblank_max, 1, mode->vblank);
0394 }
0395
0396
0397
0398
0399
0400
0401
0402
0403
0404 static int ov9282_update_exp_gain(struct ov9282 *ov9282, u32 exposure, u32 gain)
0405 {
0406 u32 lpfr;
0407 int ret;
0408
0409 lpfr = ov9282->vblank + ov9282->cur_mode->height;
0410
0411 dev_dbg(ov9282->dev, "Set exp %u, analog gain %u, lpfr %u",
0412 exposure, gain, lpfr);
0413
0414 ret = ov9282_write_reg(ov9282, OV9282_REG_HOLD, 1, 1);
0415 if (ret)
0416 return ret;
0417
0418 ret = ov9282_write_reg(ov9282, OV9282_REG_LPFR, 2, lpfr);
0419 if (ret)
0420 goto error_release_group_hold;
0421
0422 ret = ov9282_write_reg(ov9282, OV9282_REG_EXPOSURE, 3, exposure << 4);
0423 if (ret)
0424 goto error_release_group_hold;
0425
0426 ret = ov9282_write_reg(ov9282, OV9282_REG_AGAIN, 1, gain);
0427
0428 error_release_group_hold:
0429 ov9282_write_reg(ov9282, OV9282_REG_HOLD, 1, 0);
0430
0431 return ret;
0432 }
0433
0434
0435
0436
0437
0438
0439
0440
0441
0442
0443
0444
0445
0446 static int ov9282_set_ctrl(struct v4l2_ctrl *ctrl)
0447 {
0448 struct ov9282 *ov9282 =
0449 container_of(ctrl->handler, struct ov9282, ctrl_handler);
0450 u32 analog_gain;
0451 u32 exposure;
0452 int ret;
0453
0454 switch (ctrl->id) {
0455 case V4L2_CID_VBLANK:
0456 ov9282->vblank = ov9282->vblank_ctrl->val;
0457
0458 dev_dbg(ov9282->dev, "Received vblank %u, new lpfr %u",
0459 ov9282->vblank,
0460 ov9282->vblank + ov9282->cur_mode->height);
0461
0462 ret = __v4l2_ctrl_modify_range(ov9282->exp_ctrl,
0463 OV9282_EXPOSURE_MIN,
0464 ov9282->vblank +
0465 ov9282->cur_mode->height -
0466 OV9282_EXPOSURE_OFFSET,
0467 1, OV9282_EXPOSURE_DEFAULT);
0468 break;
0469 case V4L2_CID_EXPOSURE:
0470
0471 if (!pm_runtime_get_if_in_use(ov9282->dev))
0472 return 0;
0473
0474 exposure = ctrl->val;
0475 analog_gain = ov9282->again_ctrl->val;
0476
0477 dev_dbg(ov9282->dev, "Received exp %u, analog gain %u",
0478 exposure, analog_gain);
0479
0480 ret = ov9282_update_exp_gain(ov9282, exposure, analog_gain);
0481
0482 pm_runtime_put(ov9282->dev);
0483
0484 break;
0485 default:
0486 dev_err(ov9282->dev, "Invalid control %d", ctrl->id);
0487 ret = -EINVAL;
0488 }
0489
0490 return ret;
0491 }
0492
0493
0494 static const struct v4l2_ctrl_ops ov9282_ctrl_ops = {
0495 .s_ctrl = ov9282_set_ctrl,
0496 };
0497
0498
0499
0500
0501
0502
0503
0504
0505
0506 static int ov9282_enum_mbus_code(struct v4l2_subdev *sd,
0507 struct v4l2_subdev_state *sd_state,
0508 struct v4l2_subdev_mbus_code_enum *code)
0509 {
0510 if (code->index > 0)
0511 return -EINVAL;
0512
0513 code->code = supported_mode.code;
0514
0515 return 0;
0516 }
0517
0518
0519
0520
0521
0522
0523
0524
0525
0526 static int ov9282_enum_frame_size(struct v4l2_subdev *sd,
0527 struct v4l2_subdev_state *sd_state,
0528 struct v4l2_subdev_frame_size_enum *fsize)
0529 {
0530 if (fsize->index > 0)
0531 return -EINVAL;
0532
0533 if (fsize->code != supported_mode.code)
0534 return -EINVAL;
0535
0536 fsize->min_width = supported_mode.width;
0537 fsize->max_width = fsize->min_width;
0538 fsize->min_height = supported_mode.height;
0539 fsize->max_height = fsize->min_height;
0540
0541 return 0;
0542 }
0543
0544
0545
0546
0547
0548
0549
0550
0551 static void ov9282_fill_pad_format(struct ov9282 *ov9282,
0552 const struct ov9282_mode *mode,
0553 struct v4l2_subdev_format *fmt)
0554 {
0555 fmt->format.width = mode->width;
0556 fmt->format.height = mode->height;
0557 fmt->format.code = mode->code;
0558 fmt->format.field = V4L2_FIELD_NONE;
0559 fmt->format.colorspace = V4L2_COLORSPACE_RAW;
0560 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
0561 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT;
0562 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
0563 }
0564
0565
0566
0567
0568
0569
0570
0571
0572
0573 static int ov9282_get_pad_format(struct v4l2_subdev *sd,
0574 struct v4l2_subdev_state *sd_state,
0575 struct v4l2_subdev_format *fmt)
0576 {
0577 struct ov9282 *ov9282 = to_ov9282(sd);
0578
0579 mutex_lock(&ov9282->mutex);
0580
0581 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0582 struct v4l2_mbus_framefmt *framefmt;
0583
0584 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0585 fmt->format = *framefmt;
0586 } else {
0587 ov9282_fill_pad_format(ov9282, ov9282->cur_mode, fmt);
0588 }
0589
0590 mutex_unlock(&ov9282->mutex);
0591
0592 return 0;
0593 }
0594
0595
0596
0597
0598
0599
0600
0601
0602
0603 static int ov9282_set_pad_format(struct v4l2_subdev *sd,
0604 struct v4l2_subdev_state *sd_state,
0605 struct v4l2_subdev_format *fmt)
0606 {
0607 struct ov9282 *ov9282 = to_ov9282(sd);
0608 const struct ov9282_mode *mode;
0609 int ret = 0;
0610
0611 mutex_lock(&ov9282->mutex);
0612
0613 mode = &supported_mode;
0614 ov9282_fill_pad_format(ov9282, mode, fmt);
0615
0616 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0617 struct v4l2_mbus_framefmt *framefmt;
0618
0619 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0620 *framefmt = fmt->format;
0621 } else {
0622 ret = ov9282_update_controls(ov9282, mode);
0623 if (!ret)
0624 ov9282->cur_mode = mode;
0625 }
0626
0627 mutex_unlock(&ov9282->mutex);
0628
0629 return ret;
0630 }
0631
0632
0633
0634
0635
0636
0637
0638
0639 static int ov9282_init_pad_cfg(struct v4l2_subdev *sd,
0640 struct v4l2_subdev_state *sd_state)
0641 {
0642 struct ov9282 *ov9282 = to_ov9282(sd);
0643 struct v4l2_subdev_format fmt = { 0 };
0644
0645 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
0646 ov9282_fill_pad_format(ov9282, &supported_mode, &fmt);
0647
0648 return ov9282_set_pad_format(sd, sd_state, &fmt);
0649 }
0650
0651
0652
0653
0654
0655
0656
0657 static int ov9282_start_streaming(struct ov9282 *ov9282)
0658 {
0659 const struct ov9282_reg_list *reg_list;
0660 int ret;
0661
0662
0663 reg_list = &ov9282->cur_mode->reg_list;
0664 ret = ov9282_write_regs(ov9282, reg_list->regs, reg_list->num_of_regs);
0665 if (ret) {
0666 dev_err(ov9282->dev, "fail to write initial registers");
0667 return ret;
0668 }
0669
0670
0671 ret = __v4l2_ctrl_handler_setup(ov9282->sd.ctrl_handler);
0672 if (ret) {
0673 dev_err(ov9282->dev, "fail to setup handler");
0674 return ret;
0675 }
0676
0677
0678 ret = ov9282_write_reg(ov9282, OV9282_REG_MODE_SELECT,
0679 1, OV9282_MODE_STREAMING);
0680 if (ret) {
0681 dev_err(ov9282->dev, "fail to start streaming");
0682 return ret;
0683 }
0684
0685 return 0;
0686 }
0687
0688
0689
0690
0691
0692
0693
0694 static int ov9282_stop_streaming(struct ov9282 *ov9282)
0695 {
0696 return ov9282_write_reg(ov9282, OV9282_REG_MODE_SELECT,
0697 1, OV9282_MODE_STANDBY);
0698 }
0699
0700
0701
0702
0703
0704
0705
0706
0707 static int ov9282_set_stream(struct v4l2_subdev *sd, int enable)
0708 {
0709 struct ov9282 *ov9282 = to_ov9282(sd);
0710 int ret;
0711
0712 mutex_lock(&ov9282->mutex);
0713
0714 if (ov9282->streaming == enable) {
0715 mutex_unlock(&ov9282->mutex);
0716 return 0;
0717 }
0718
0719 if (enable) {
0720 ret = pm_runtime_resume_and_get(ov9282->dev);
0721 if (ret)
0722 goto error_unlock;
0723
0724 ret = ov9282_start_streaming(ov9282);
0725 if (ret)
0726 goto error_power_off;
0727 } else {
0728 ov9282_stop_streaming(ov9282);
0729 pm_runtime_put(ov9282->dev);
0730 }
0731
0732 ov9282->streaming = enable;
0733
0734 mutex_unlock(&ov9282->mutex);
0735
0736 return 0;
0737
0738 error_power_off:
0739 pm_runtime_put(ov9282->dev);
0740 error_unlock:
0741 mutex_unlock(&ov9282->mutex);
0742
0743 return ret;
0744 }
0745
0746
0747
0748
0749
0750
0751
0752 static int ov9282_detect(struct ov9282 *ov9282)
0753 {
0754 int ret;
0755 u32 val;
0756
0757 ret = ov9282_read_reg(ov9282, OV9282_REG_ID, 2, &val);
0758 if (ret)
0759 return ret;
0760
0761 if (val != OV9282_ID) {
0762 dev_err(ov9282->dev, "chip id mismatch: %x!=%x",
0763 OV9282_ID, val);
0764 return -ENXIO;
0765 }
0766
0767 return 0;
0768 }
0769
0770
0771
0772
0773
0774
0775
0776 static int ov9282_parse_hw_config(struct ov9282 *ov9282)
0777 {
0778 struct fwnode_handle *fwnode = dev_fwnode(ov9282->dev);
0779 struct v4l2_fwnode_endpoint bus_cfg = {
0780 .bus_type = V4L2_MBUS_CSI2_DPHY
0781 };
0782 struct fwnode_handle *ep;
0783 unsigned long rate;
0784 unsigned int i;
0785 int ret;
0786
0787 if (!fwnode)
0788 return -ENXIO;
0789
0790
0791 ov9282->reset_gpio = devm_gpiod_get_optional(ov9282->dev, "reset",
0792 GPIOD_OUT_LOW);
0793 if (IS_ERR(ov9282->reset_gpio)) {
0794 dev_err(ov9282->dev, "failed to get reset gpio %ld",
0795 PTR_ERR(ov9282->reset_gpio));
0796 return PTR_ERR(ov9282->reset_gpio);
0797 }
0798
0799
0800 ov9282->inclk = devm_clk_get(ov9282->dev, NULL);
0801 if (IS_ERR(ov9282->inclk)) {
0802 dev_err(ov9282->dev, "could not get inclk");
0803 return PTR_ERR(ov9282->inclk);
0804 }
0805
0806 rate = clk_get_rate(ov9282->inclk);
0807 if (rate != OV9282_INCLK_RATE) {
0808 dev_err(ov9282->dev, "inclk frequency mismatch");
0809 return -EINVAL;
0810 }
0811
0812 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
0813 if (!ep)
0814 return -ENXIO;
0815
0816 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
0817 fwnode_handle_put(ep);
0818 if (ret)
0819 return ret;
0820
0821 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV9282_NUM_DATA_LANES) {
0822 dev_err(ov9282->dev,
0823 "number of CSI2 data lanes %d is not supported",
0824 bus_cfg.bus.mipi_csi2.num_data_lanes);
0825 ret = -EINVAL;
0826 goto done_endpoint_free;
0827 }
0828
0829 if (!bus_cfg.nr_of_link_frequencies) {
0830 dev_err(ov9282->dev, "no link frequencies defined");
0831 ret = -EINVAL;
0832 goto done_endpoint_free;
0833 }
0834
0835 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++)
0836 if (bus_cfg.link_frequencies[i] == OV9282_LINK_FREQ)
0837 goto done_endpoint_free;
0838
0839 ret = -EINVAL;
0840
0841 done_endpoint_free:
0842 v4l2_fwnode_endpoint_free(&bus_cfg);
0843
0844 return ret;
0845 }
0846
0847
0848 static const struct v4l2_subdev_video_ops ov9282_video_ops = {
0849 .s_stream = ov9282_set_stream,
0850 };
0851
0852 static const struct v4l2_subdev_pad_ops ov9282_pad_ops = {
0853 .init_cfg = ov9282_init_pad_cfg,
0854 .enum_mbus_code = ov9282_enum_mbus_code,
0855 .enum_frame_size = ov9282_enum_frame_size,
0856 .get_fmt = ov9282_get_pad_format,
0857 .set_fmt = ov9282_set_pad_format,
0858 };
0859
0860 static const struct v4l2_subdev_ops ov9282_subdev_ops = {
0861 .video = &ov9282_video_ops,
0862 .pad = &ov9282_pad_ops,
0863 };
0864
0865
0866
0867
0868
0869
0870
0871 static int ov9282_power_on(struct device *dev)
0872 {
0873 struct v4l2_subdev *sd = dev_get_drvdata(dev);
0874 struct ov9282 *ov9282 = to_ov9282(sd);
0875 int ret;
0876
0877 usleep_range(400, 600);
0878
0879 gpiod_set_value_cansleep(ov9282->reset_gpio, 1);
0880
0881 ret = clk_prepare_enable(ov9282->inclk);
0882 if (ret) {
0883 dev_err(ov9282->dev, "fail to enable inclk");
0884 goto error_reset;
0885 }
0886
0887 usleep_range(400, 600);
0888
0889 return 0;
0890
0891 error_reset:
0892 gpiod_set_value_cansleep(ov9282->reset_gpio, 0);
0893
0894 return ret;
0895 }
0896
0897
0898
0899
0900
0901
0902
0903 static int ov9282_power_off(struct device *dev)
0904 {
0905 struct v4l2_subdev *sd = dev_get_drvdata(dev);
0906 struct ov9282 *ov9282 = to_ov9282(sd);
0907
0908 gpiod_set_value_cansleep(ov9282->reset_gpio, 0);
0909
0910 clk_disable_unprepare(ov9282->inclk);
0911
0912 return 0;
0913 }
0914
0915
0916
0917
0918
0919
0920
0921 static int ov9282_init_controls(struct ov9282 *ov9282)
0922 {
0923 struct v4l2_ctrl_handler *ctrl_hdlr = &ov9282->ctrl_handler;
0924 const struct ov9282_mode *mode = ov9282->cur_mode;
0925 u32 lpfr;
0926 int ret;
0927
0928 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 6);
0929 if (ret)
0930 return ret;
0931
0932
0933 ctrl_hdlr->lock = &ov9282->mutex;
0934
0935
0936 lpfr = mode->vblank + mode->height;
0937 ov9282->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0938 &ov9282_ctrl_ops,
0939 V4L2_CID_EXPOSURE,
0940 OV9282_EXPOSURE_MIN,
0941 lpfr - OV9282_EXPOSURE_OFFSET,
0942 OV9282_EXPOSURE_STEP,
0943 OV9282_EXPOSURE_DEFAULT);
0944
0945 ov9282->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0946 &ov9282_ctrl_ops,
0947 V4L2_CID_ANALOGUE_GAIN,
0948 OV9282_AGAIN_MIN,
0949 OV9282_AGAIN_MAX,
0950 OV9282_AGAIN_STEP,
0951 OV9282_AGAIN_DEFAULT);
0952
0953 v4l2_ctrl_cluster(2, &ov9282->exp_ctrl);
0954
0955 ov9282->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0956 &ov9282_ctrl_ops,
0957 V4L2_CID_VBLANK,
0958 mode->vblank_min,
0959 mode->vblank_max,
0960 1, mode->vblank);
0961
0962
0963 ov9282->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0964 &ov9282_ctrl_ops,
0965 V4L2_CID_PIXEL_RATE,
0966 mode->pclk, mode->pclk,
0967 1, mode->pclk);
0968
0969 ov9282->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr,
0970 &ov9282_ctrl_ops,
0971 V4L2_CID_LINK_FREQ,
0972 ARRAY_SIZE(link_freq) -
0973 1,
0974 mode->link_freq_idx,
0975 link_freq);
0976 if (ov9282->link_freq_ctrl)
0977 ov9282->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0978
0979 ov9282->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0980 &ov9282_ctrl_ops,
0981 V4L2_CID_HBLANK,
0982 OV9282_REG_MIN,
0983 OV9282_REG_MAX,
0984 1, mode->hblank);
0985 if (ov9282->hblank_ctrl)
0986 ov9282->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0987
0988 if (ctrl_hdlr->error) {
0989 dev_err(ov9282->dev, "control init failed: %d",
0990 ctrl_hdlr->error);
0991 v4l2_ctrl_handler_free(ctrl_hdlr);
0992 return ctrl_hdlr->error;
0993 }
0994
0995 ov9282->sd.ctrl_handler = ctrl_hdlr;
0996
0997 return 0;
0998 }
0999
1000
1001
1002
1003
1004
1005
1006 static int ov9282_probe(struct i2c_client *client)
1007 {
1008 struct ov9282 *ov9282;
1009 int ret;
1010
1011 ov9282 = devm_kzalloc(&client->dev, sizeof(*ov9282), GFP_KERNEL);
1012 if (!ov9282)
1013 return -ENOMEM;
1014
1015 ov9282->dev = &client->dev;
1016
1017
1018 v4l2_i2c_subdev_init(&ov9282->sd, client, &ov9282_subdev_ops);
1019
1020 ret = ov9282_parse_hw_config(ov9282);
1021 if (ret) {
1022 dev_err(ov9282->dev, "HW configuration is not supported");
1023 return ret;
1024 }
1025
1026 mutex_init(&ov9282->mutex);
1027
1028 ret = ov9282_power_on(ov9282->dev);
1029 if (ret) {
1030 dev_err(ov9282->dev, "failed to power-on the sensor");
1031 goto error_mutex_destroy;
1032 }
1033
1034
1035 ret = ov9282_detect(ov9282);
1036 if (ret) {
1037 dev_err(ov9282->dev, "failed to find sensor: %d", ret);
1038 goto error_power_off;
1039 }
1040
1041
1042 ov9282->cur_mode = &supported_mode;
1043 ov9282->vblank = ov9282->cur_mode->vblank;
1044
1045 ret = ov9282_init_controls(ov9282);
1046 if (ret) {
1047 dev_err(ov9282->dev, "failed to init controls: %d", ret);
1048 goto error_power_off;
1049 }
1050
1051
1052 ov9282->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1053 ov9282->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1054
1055
1056 ov9282->pad.flags = MEDIA_PAD_FL_SOURCE;
1057 ret = media_entity_pads_init(&ov9282->sd.entity, 1, &ov9282->pad);
1058 if (ret) {
1059 dev_err(ov9282->dev, "failed to init entity pads: %d", ret);
1060 goto error_handler_free;
1061 }
1062
1063 ret = v4l2_async_register_subdev_sensor(&ov9282->sd);
1064 if (ret < 0) {
1065 dev_err(ov9282->dev,
1066 "failed to register async subdev: %d", ret);
1067 goto error_media_entity;
1068 }
1069
1070 pm_runtime_set_active(ov9282->dev);
1071 pm_runtime_enable(ov9282->dev);
1072 pm_runtime_idle(ov9282->dev);
1073
1074 return 0;
1075
1076 error_media_entity:
1077 media_entity_cleanup(&ov9282->sd.entity);
1078 error_handler_free:
1079 v4l2_ctrl_handler_free(ov9282->sd.ctrl_handler);
1080 error_power_off:
1081 ov9282_power_off(ov9282->dev);
1082 error_mutex_destroy:
1083 mutex_destroy(&ov9282->mutex);
1084
1085 return ret;
1086 }
1087
1088
1089
1090
1091
1092
1093
1094 static int ov9282_remove(struct i2c_client *client)
1095 {
1096 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1097 struct ov9282 *ov9282 = to_ov9282(sd);
1098
1099 v4l2_async_unregister_subdev(sd);
1100 media_entity_cleanup(&sd->entity);
1101 v4l2_ctrl_handler_free(sd->ctrl_handler);
1102
1103 pm_runtime_disable(&client->dev);
1104 if (!pm_runtime_status_suspended(&client->dev))
1105 ov9282_power_off(&client->dev);
1106 pm_runtime_set_suspended(&client->dev);
1107
1108 mutex_destroy(&ov9282->mutex);
1109
1110 return 0;
1111 }
1112
1113 static const struct dev_pm_ops ov9282_pm_ops = {
1114 SET_RUNTIME_PM_OPS(ov9282_power_off, ov9282_power_on, NULL)
1115 };
1116
1117 static const struct of_device_id ov9282_of_match[] = {
1118 { .compatible = "ovti,ov9282" },
1119 { }
1120 };
1121
1122 MODULE_DEVICE_TABLE(of, ov9282_of_match);
1123
1124 static struct i2c_driver ov9282_driver = {
1125 .probe_new = ov9282_probe,
1126 .remove = ov9282_remove,
1127 .driver = {
1128 .name = "ov9282",
1129 .pm = &ov9282_pm_ops,
1130 .of_match_table = ov9282_of_match,
1131 },
1132 };
1133
1134 module_i2c_driver(ov9282_driver);
1135
1136 MODULE_DESCRIPTION("OmniVision ov9282 sensor driver");
1137 MODULE_LICENSE("GPL");