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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * A V4L2 driver for OmniVision OV7670 cameras.
0004  *
0005  * Copyright 2006 One Laptop Per Child Association, Inc.  Written
0006  * by Jonathan Corbet with substantial inspiration from Mark
0007  * McClelland's ovcamchip code.
0008  *
0009  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
0010  */
0011 #include <linux/clk.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/slab.h>
0015 #include <linux/i2c.h>
0016 #include <linux/delay.h>
0017 #include <linux/videodev2.h>
0018 #include <linux/gpio.h>
0019 #include <linux/gpio/consumer.h>
0020 #include <media/v4l2-device.h>
0021 #include <media/v4l2-event.h>
0022 #include <media/v4l2-ctrls.h>
0023 #include <media/v4l2-fwnode.h>
0024 #include <media/v4l2-mediabus.h>
0025 #include <media/v4l2-image-sizes.h>
0026 #include <media/i2c/ov7670.h>
0027 
0028 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
0029 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
0030 MODULE_LICENSE("GPL");
0031 
0032 static bool debug;
0033 module_param(debug, bool, 0644);
0034 MODULE_PARM_DESC(debug, "Debug level (0-1)");
0035 
0036 /*
0037  * The 7670 sits on i2c with ID 0x42
0038  */
0039 #define OV7670_I2C_ADDR 0x42
0040 
0041 #define PLL_FACTOR  4
0042 
0043 /* Registers */
0044 #define REG_GAIN    0x00    /* Gain lower 8 bits (rest in vref) */
0045 #define REG_BLUE    0x01    /* blue gain */
0046 #define REG_RED     0x02    /* red gain */
0047 #define REG_VREF    0x03    /* Pieces of GAIN, VSTART, VSTOP */
0048 #define REG_COM1    0x04    /* Control 1 */
0049 #define  COM1_CCIR656     0x40  /* CCIR656 enable */
0050 #define REG_BAVE    0x05    /* U/B Average level */
0051 #define REG_GbAVE   0x06    /* Y/Gb Average level */
0052 #define REG_AECHH   0x07    /* AEC MS 5 bits */
0053 #define REG_RAVE    0x08    /* V/R Average level */
0054 #define REG_COM2    0x09    /* Control 2 */
0055 #define  COM2_SSLEEP      0x10  /* Soft sleep mode */
0056 #define REG_PID     0x0a    /* Product ID MSB */
0057 #define REG_VER     0x0b    /* Product ID LSB */
0058 #define REG_COM3    0x0c    /* Control 3 */
0059 #define  COM3_SWAP    0x40    /* Byte swap */
0060 #define  COM3_SCALEEN     0x08    /* Enable scaling */
0061 #define  COM3_DCWEN   0x04    /* Enable downsamp/crop/window */
0062 #define REG_COM4    0x0d    /* Control 4 */
0063 #define REG_COM5    0x0e    /* All "reserved" */
0064 #define REG_COM6    0x0f    /* Control 6 */
0065 #define REG_AECH    0x10    /* More bits of AEC value */
0066 #define REG_CLKRC   0x11    /* Clocl control */
0067 #define   CLK_EXT     0x40    /* Use external clock directly */
0068 #define   CLK_SCALE   0x3f    /* Mask for internal clock scale */
0069 #define REG_COM7    0x12    /* Control 7 */
0070 #define   COM7_RESET      0x80    /* Register reset */
0071 #define   COM7_FMT_MASK   0x38
0072 #define   COM7_FMT_VGA    0x00
0073 #define   COM7_FMT_CIF    0x20    /* CIF format */
0074 #define   COM7_FMT_QVGA   0x10    /* QVGA format */
0075 #define   COM7_FMT_QCIF   0x08    /* QCIF format */
0076 #define   COM7_RGB    0x04    /* bits 0 and 2 - RGB format */
0077 #define   COM7_YUV    0x00    /* YUV */
0078 #define   COM7_BAYER      0x01    /* Bayer format */
0079 #define   COM7_PBAYER     0x05    /* "Processed bayer" */
0080 #define REG_COM8    0x13    /* Control 8 */
0081 #define   COM8_FASTAEC    0x80    /* Enable fast AGC/AEC */
0082 #define   COM8_AECSTEP    0x40    /* Unlimited AEC step size */
0083 #define   COM8_BFILT      0x20    /* Band filter enable */
0084 #define   COM8_AGC    0x04    /* Auto gain enable */
0085 #define   COM8_AWB    0x02    /* White balance enable */
0086 #define   COM8_AEC    0x01    /* Auto exposure enable */
0087 #define REG_COM9    0x14    /* Control 9  - gain ceiling */
0088 #define REG_COM10   0x15    /* Control 10 */
0089 #define   COM10_HSYNC     0x40    /* HSYNC instead of HREF */
0090 #define   COM10_PCLK_HB   0x20    /* Suppress PCLK on horiz blank */
0091 #define   COM10_HREF_REV  0x08    /* Reverse HREF */
0092 #define   COM10_VS_LEAD   0x04    /* VSYNC on clock leading edge */
0093 #define   COM10_VS_NEG    0x02    /* VSYNC negative */
0094 #define   COM10_HS_NEG    0x01    /* HSYNC negative */
0095 #define REG_HSTART  0x17    /* Horiz start high bits */
0096 #define REG_HSTOP   0x18    /* Horiz stop high bits */
0097 #define REG_VSTART  0x19    /* Vert start high bits */
0098 #define REG_VSTOP   0x1a    /* Vert stop high bits */
0099 #define REG_PSHFT   0x1b    /* Pixel delay after HREF */
0100 #define REG_MIDH    0x1c    /* Manuf. ID high */
0101 #define REG_MIDL    0x1d    /* Manuf. ID low */
0102 #define REG_MVFP    0x1e    /* Mirror / vflip */
0103 #define   MVFP_MIRROR     0x20    /* Mirror image */
0104 #define   MVFP_FLIP   0x10    /* Vertical flip */
0105 
0106 #define REG_AEW     0x24    /* AGC upper limit */
0107 #define REG_AEB     0x25    /* AGC lower limit */
0108 #define REG_VPT     0x26    /* AGC/AEC fast mode op region */
0109 #define REG_HSYST   0x30    /* HSYNC rising edge delay */
0110 #define REG_HSYEN   0x31    /* HSYNC falling edge delay */
0111 #define REG_HREF    0x32    /* HREF pieces */
0112 #define REG_TSLB    0x3a    /* lots of stuff */
0113 #define   TSLB_YLAST      0x04    /* UYVY or VYUY - see com13 */
0114 #define REG_COM11   0x3b    /* Control 11 */
0115 #define   COM11_NIGHT     0x80    /* NIght mode enable */
0116 #define   COM11_NMFR      0x60    /* Two bit NM frame rate */
0117 #define   COM11_HZAUTO    0x10    /* Auto detect 50/60 Hz */
0118 #define   COM11_50HZ      0x08    /* Manual 50Hz select */
0119 #define   COM11_EXP   0x02
0120 #define REG_COM12   0x3c    /* Control 12 */
0121 #define   COM12_HREF      0x80    /* HREF always */
0122 #define REG_COM13   0x3d    /* Control 13 */
0123 #define   COM13_GAMMA     0x80    /* Gamma enable */
0124 #define   COM13_UVSAT     0x40    /* UV saturation auto adjustment */
0125 #define   COM13_UVSWAP    0x01    /* V before U - w/TSLB */
0126 #define REG_COM14   0x3e    /* Control 14 */
0127 #define   COM14_DCWEN     0x10    /* DCW/PCLK-scale enable */
0128 #define REG_EDGE    0x3f    /* Edge enhancement factor */
0129 #define REG_COM15   0x40    /* Control 15 */
0130 #define   COM15_R10F0     0x00    /* Data range 10 to F0 */
0131 #define   COM15_R01FE     0x80    /*            01 to FE */
0132 #define   COM15_R00FF     0xc0    /*            00 to FF */
0133 #define   COM15_RGB565    0x10    /* RGB565 output */
0134 #define   COM15_RGB555    0x30    /* RGB555 output */
0135 #define REG_COM16   0x41    /* Control 16 */
0136 #define   COM16_AWBGAIN   0x08    /* AWB gain enable */
0137 #define REG_COM17   0x42    /* Control 17 */
0138 #define   COM17_AECWIN    0xc0    /* AEC window - must match COM4 */
0139 #define   COM17_CBAR      0x08    /* DSP Color bar */
0140 
0141 /*
0142  * This matrix defines how the colors are generated, must be
0143  * tweaked to adjust hue and saturation.
0144  *
0145  * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
0146  *
0147  * They are nine-bit signed quantities, with the sign bit
0148  * stored in 0x58.  Sign for v-red is bit 0, and up from there.
0149  */
0150 #define REG_CMATRIX_BASE 0x4f
0151 #define   CMATRIX_LEN 6
0152 #define REG_CMATRIX_SIGN 0x58
0153 
0154 
0155 #define REG_BRIGHT  0x55    /* Brightness */
0156 #define REG_CONTRAS 0x56    /* Contrast control */
0157 
0158 #define REG_GFIX    0x69    /* Fix gain control */
0159 
0160 #define REG_DBLV    0x6b    /* PLL control an debugging */
0161 #define   DBLV_BYPASS     0x0a    /* Bypass PLL */
0162 #define   DBLV_X4     0x4a    /* clock x4 */
0163 #define   DBLV_X6     0x8a    /* clock x6 */
0164 #define   DBLV_X8     0xca    /* clock x8 */
0165 
0166 #define REG_SCALING_XSC 0x70    /* Test pattern and horizontal scale factor */
0167 #define   TEST_PATTTERN_0 0x80
0168 #define REG_SCALING_YSC 0x71    /* Test pattern and vertical scale factor */
0169 #define   TEST_PATTTERN_1 0x80
0170 
0171 #define REG_REG76   0x76    /* OV's name */
0172 #define   R76_BLKPCOR     0x80    /* Black pixel correction enable */
0173 #define   R76_WHTPCOR     0x40    /* White pixel correction enable */
0174 
0175 #define REG_RGB444  0x8c    /* RGB 444 control */
0176 #define   R444_ENABLE     0x02    /* Turn on RGB444, overrides 5x5 */
0177 #define   R444_RGBX   0x01    /* Empty nibble at end */
0178 
0179 #define REG_HAECC1  0x9f    /* Hist AEC/AGC control 1 */
0180 #define REG_HAECC2  0xa0    /* Hist AEC/AGC control 2 */
0181 
0182 #define REG_BD50MAX 0xa5    /* 50hz banding step limit */
0183 #define REG_HAECC3  0xa6    /* Hist AEC/AGC control 3 */
0184 #define REG_HAECC4  0xa7    /* Hist AEC/AGC control 4 */
0185 #define REG_HAECC5  0xa8    /* Hist AEC/AGC control 5 */
0186 #define REG_HAECC6  0xa9    /* Hist AEC/AGC control 6 */
0187 #define REG_HAECC7  0xaa    /* Hist AEC/AGC control 7 */
0188 #define REG_BD60MAX 0xab    /* 60hz banding step limit */
0189 
0190 enum ov7670_model {
0191     MODEL_OV7670 = 0,
0192     MODEL_OV7675,
0193 };
0194 
0195 struct ov7670_win_size {
0196     int width;
0197     int height;
0198     unsigned char com7_bit;
0199     int hstart;     /* Start/stop values for the camera.  Note */
0200     int hstop;      /* that they do not always make complete */
0201     int vstart;     /* sense to humans, but evidently the sensor */
0202     int vstop;      /* will do the right thing... */
0203     struct regval_list *regs; /* Regs to tweak */
0204 };
0205 
0206 struct ov7670_devtype {
0207     /* formats supported for each model */
0208     struct ov7670_win_size *win_sizes;
0209     unsigned int n_win_sizes;
0210     /* callbacks for frame rate control */
0211     int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
0212     void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
0213 };
0214 
0215 /*
0216  * Information we maintain about a known sensor.
0217  */
0218 struct ov7670_format_struct;  /* coming later */
0219 struct ov7670_info {
0220     struct v4l2_subdev sd;
0221 #if defined(CONFIG_MEDIA_CONTROLLER)
0222     struct media_pad pad;
0223 #endif
0224     struct v4l2_ctrl_handler hdl;
0225     struct {
0226         /* gain cluster */
0227         struct v4l2_ctrl *auto_gain;
0228         struct v4l2_ctrl *gain;
0229     };
0230     struct {
0231         /* exposure cluster */
0232         struct v4l2_ctrl *auto_exposure;
0233         struct v4l2_ctrl *exposure;
0234     };
0235     struct {
0236         /* saturation/hue cluster */
0237         struct v4l2_ctrl *saturation;
0238         struct v4l2_ctrl *hue;
0239     };
0240     struct v4l2_mbus_framefmt format;
0241     struct ov7670_format_struct *fmt;  /* Current format */
0242     struct ov7670_win_size *wsize;
0243     struct clk *clk;
0244     int on;
0245     struct gpio_desc *resetb_gpio;
0246     struct gpio_desc *pwdn_gpio;
0247     unsigned int mbus_config;   /* Media bus configuration flags */
0248     int min_width;          /* Filter out smaller sizes */
0249     int min_height;         /* Filter out smaller sizes */
0250     int clock_speed;        /* External clock speed (MHz) */
0251     u8 clkrc;           /* Clock divider value */
0252     bool use_smbus;         /* Use smbus I/O instead of I2C */
0253     bool pll_bypass;
0254     bool pclk_hb_disable;
0255     const struct ov7670_devtype *devtype; /* Device specifics */
0256 };
0257 
0258 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
0259 {
0260     return container_of(sd, struct ov7670_info, sd);
0261 }
0262 
0263 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
0264 {
0265     return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
0266 }
0267 
0268 
0269 
0270 /*
0271  * The default register settings, as obtained from OmniVision.  There
0272  * is really no making sense of most of these - lots of "reserved" values
0273  * and such.
0274  *
0275  * These settings give VGA YUYV.
0276  */
0277 
0278 struct regval_list {
0279     unsigned char reg_num;
0280     unsigned char value;
0281 };
0282 
0283 static struct regval_list ov7670_default_regs[] = {
0284     { REG_COM7, COM7_RESET },
0285 /*
0286  * Clock scale: 3 = 15fps
0287  *              2 = 20fps
0288  *              1 = 30fps
0289  */
0290     { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
0291     { REG_TSLB,  0x04 },    /* OV */
0292     { REG_COM7, 0 },    /* VGA */
0293     /*
0294      * Set the hardware window.  These values from OV don't entirely
0295      * make sense - hstop is less than hstart.  But they work...
0296      */
0297     { REG_HSTART, 0x13 },   { REG_HSTOP, 0x01 },
0298     { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
0299     { REG_VSTOP, 0x7a },    { REG_VREF, 0x0a },
0300 
0301     { REG_COM3, 0 },    { REG_COM14, 0 },
0302     /* Mystery scaling numbers */
0303     { REG_SCALING_XSC, 0x3a },
0304     { REG_SCALING_YSC, 0x35 },
0305     { 0x72, 0x11 },     { 0x73, 0xf0 },
0306     { 0xa2, 0x02 },     { REG_COM10, 0x0 },
0307 
0308     /* Gamma curve values */
0309     { 0x7a, 0x20 },     { 0x7b, 0x10 },
0310     { 0x7c, 0x1e },     { 0x7d, 0x35 },
0311     { 0x7e, 0x5a },     { 0x7f, 0x69 },
0312     { 0x80, 0x76 },     { 0x81, 0x80 },
0313     { 0x82, 0x88 },     { 0x83, 0x8f },
0314     { 0x84, 0x96 },     { 0x85, 0xa3 },
0315     { 0x86, 0xaf },     { 0x87, 0xc4 },
0316     { 0x88, 0xd7 },     { 0x89, 0xe8 },
0317 
0318     /* AGC and AEC parameters.  Note we start by disabling those features,
0319        then turn them only after tweaking the values. */
0320     { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
0321     { REG_GAIN, 0 },    { REG_AECH, 0 },
0322     { REG_COM4, 0x40 }, /* magic reserved bit */
0323     { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
0324     { REG_BD50MAX, 0x05 },  { REG_BD60MAX, 0x07 },
0325     { REG_AEW, 0x95 },  { REG_AEB, 0x33 },
0326     { REG_VPT, 0xe3 },  { REG_HAECC1, 0x78 },
0327     { REG_HAECC2, 0x68 },   { 0xa1, 0x03 }, /* magic */
0328     { REG_HAECC3, 0xd8 },   { REG_HAECC4, 0xd8 },
0329     { REG_HAECC5, 0xf0 },   { REG_HAECC6, 0x90 },
0330     { REG_HAECC7, 0x94 },
0331     { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
0332 
0333     /* Almost all of these are magic "reserved" values.  */
0334     { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
0335     { 0x16, 0x02 },     { REG_MVFP, 0x07 },
0336     { 0x21, 0x02 },     { 0x22, 0x91 },
0337     { 0x29, 0x07 },     { 0x33, 0x0b },
0338     { 0x35, 0x0b },     { 0x37, 0x1d },
0339     { 0x38, 0x71 },     { 0x39, 0x2a },
0340     { REG_COM12, 0x78 },    { 0x4d, 0x40 },
0341     { 0x4e, 0x20 },     { REG_GFIX, 0 },
0342     { 0x6b, 0x4a },     { 0x74, 0x10 },
0343     { 0x8d, 0x4f },     { 0x8e, 0 },
0344     { 0x8f, 0 },        { 0x90, 0 },
0345     { 0x91, 0 },        { 0x96, 0 },
0346     { 0x9a, 0 },        { 0xb0, 0x84 },
0347     { 0xb1, 0x0c },     { 0xb2, 0x0e },
0348     { 0xb3, 0x82 },     { 0xb8, 0x0a },
0349 
0350     /* More reserved magic, some of which tweaks white balance */
0351     { 0x43, 0x0a },     { 0x44, 0xf0 },
0352     { 0x45, 0x34 },     { 0x46, 0x58 },
0353     { 0x47, 0x28 },     { 0x48, 0x3a },
0354     { 0x59, 0x88 },     { 0x5a, 0x88 },
0355     { 0x5b, 0x44 },     { 0x5c, 0x67 },
0356     { 0x5d, 0x49 },     { 0x5e, 0x0e },
0357     { 0x6c, 0x0a },     { 0x6d, 0x55 },
0358     { 0x6e, 0x11 },     { 0x6f, 0x9f }, /* "9e for advance AWB" */
0359     { 0x6a, 0x40 },     { REG_BLUE, 0x40 },
0360     { REG_RED, 0x60 },
0361     { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
0362 
0363     /* Matrix coefficients */
0364     { 0x4f, 0x80 },     { 0x50, 0x80 },
0365     { 0x51, 0 },        { 0x52, 0x22 },
0366     { 0x53, 0x5e },     { 0x54, 0x80 },
0367     { 0x58, 0x9e },
0368 
0369     { REG_COM16, COM16_AWBGAIN },   { REG_EDGE, 0 },
0370     { 0x75, 0x05 },     { 0x76, 0xe1 },
0371     { 0x4c, 0 },        { 0x77, 0x01 },
0372     { REG_COM13, 0xc3 },    { 0x4b, 0x09 },
0373     { 0xc9, 0x60 },     { REG_COM16, 0x38 },
0374     { 0x56, 0x40 },
0375 
0376     { 0x34, 0x11 },     { REG_COM11, COM11_EXP|COM11_HZAUTO },
0377     { 0xa4, 0x88 },     { 0x96, 0 },
0378     { 0x97, 0x30 },     { 0x98, 0x20 },
0379     { 0x99, 0x30 },     { 0x9a, 0x84 },
0380     { 0x9b, 0x29 },     { 0x9c, 0x03 },
0381     { 0x9d, 0x4c },     { 0x9e, 0x3f },
0382     { 0x78, 0x04 },
0383 
0384     /* Extra-weird stuff.  Some sort of multiplexor register */
0385     { 0x79, 0x01 },     { 0xc8, 0xf0 },
0386     { 0x79, 0x0f },     { 0xc8, 0x00 },
0387     { 0x79, 0x10 },     { 0xc8, 0x7e },
0388     { 0x79, 0x0a },     { 0xc8, 0x80 },
0389     { 0x79, 0x0b },     { 0xc8, 0x01 },
0390     { 0x79, 0x0c },     { 0xc8, 0x0f },
0391     { 0x79, 0x0d },     { 0xc8, 0x20 },
0392     { 0x79, 0x09 },     { 0xc8, 0x80 },
0393     { 0x79, 0x02 },     { 0xc8, 0xc0 },
0394     { 0x79, 0x03 },     { 0xc8, 0x40 },
0395     { 0x79, 0x05 },     { 0xc8, 0x30 },
0396     { 0x79, 0x26 },
0397 
0398     { 0xff, 0xff }, /* END MARKER */
0399 };
0400 
0401 
0402 /*
0403  * Here we'll try to encapsulate the changes for just the output
0404  * video format.
0405  *
0406  * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
0407  *
0408  * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
0409  */
0410 
0411 
0412 static struct regval_list ov7670_fmt_yuv422[] = {
0413     { REG_COM7, 0x0 },  /* Selects YUV mode */
0414     { REG_RGB444, 0 },  /* No RGB444 please */
0415     { REG_COM1, 0 },    /* CCIR601 */
0416     { REG_COM15, COM15_R00FF },
0417     { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
0418     { 0x4f, 0x80 },     /* "matrix coefficient 1" */
0419     { 0x50, 0x80 },     /* "matrix coefficient 2" */
0420     { 0x51, 0    },     /* vb */
0421     { 0x52, 0x22 },     /* "matrix coefficient 4" */
0422     { 0x53, 0x5e },     /* "matrix coefficient 5" */
0423     { 0x54, 0x80 },     /* "matrix coefficient 6" */
0424     { REG_COM13, COM13_GAMMA|COM13_UVSAT },
0425     { 0xff, 0xff },
0426 };
0427 
0428 static struct regval_list ov7670_fmt_rgb565[] = {
0429     { REG_COM7, COM7_RGB }, /* Selects RGB mode */
0430     { REG_RGB444, 0 },  /* No RGB444 please */
0431     { REG_COM1, 0x0 },  /* CCIR601 */
0432     { REG_COM15, COM15_RGB565 },
0433     { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
0434     { 0x4f, 0xb3 },     /* "matrix coefficient 1" */
0435     { 0x50, 0xb3 },     /* "matrix coefficient 2" */
0436     { 0x51, 0    },     /* vb */
0437     { 0x52, 0x3d },     /* "matrix coefficient 4" */
0438     { 0x53, 0xa7 },     /* "matrix coefficient 5" */
0439     { 0x54, 0xe4 },     /* "matrix coefficient 6" */
0440     { REG_COM13, COM13_GAMMA|COM13_UVSAT },
0441     { 0xff, 0xff },
0442 };
0443 
0444 static struct regval_list ov7670_fmt_rgb444[] = {
0445     { REG_COM7, COM7_RGB }, /* Selects RGB mode */
0446     { REG_RGB444, R444_ENABLE },    /* Enable xxxxrrrr ggggbbbb */
0447     { REG_COM1, 0x0 },  /* CCIR601 */
0448     { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
0449     { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
0450     { 0x4f, 0xb3 },     /* "matrix coefficient 1" */
0451     { 0x50, 0xb3 },     /* "matrix coefficient 2" */
0452     { 0x51, 0    },     /* vb */
0453     { 0x52, 0x3d },     /* "matrix coefficient 4" */
0454     { 0x53, 0xa7 },     /* "matrix coefficient 5" */
0455     { 0x54, 0xe4 },     /* "matrix coefficient 6" */
0456     { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 },  /* Magic rsvd bit */
0457     { 0xff, 0xff },
0458 };
0459 
0460 static struct regval_list ov7670_fmt_raw[] = {
0461     { REG_COM7, COM7_BAYER },
0462     { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
0463     { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
0464     { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
0465     { 0xff, 0xff },
0466 };
0467 
0468 
0469 
0470 /*
0471  * Low-level register I/O.
0472  *
0473  * Note that there are two versions of these.  On the XO 1, the
0474  * i2c controller only does SMBUS, so that's what we use.  The
0475  * ov7670 is not really an SMBUS device, though, so the communication
0476  * is not always entirely reliable.
0477  */
0478 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
0479         unsigned char *value)
0480 {
0481     struct i2c_client *client = v4l2_get_subdevdata(sd);
0482     int ret;
0483 
0484     ret = i2c_smbus_read_byte_data(client, reg);
0485     if (ret >= 0) {
0486         *value = (unsigned char)ret;
0487         ret = 0;
0488     }
0489     return ret;
0490 }
0491 
0492 
0493 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
0494         unsigned char value)
0495 {
0496     struct i2c_client *client = v4l2_get_subdevdata(sd);
0497     int ret = i2c_smbus_write_byte_data(client, reg, value);
0498 
0499     if (reg == REG_COM7 && (value & COM7_RESET))
0500         msleep(5);  /* Wait for reset to run */
0501     return ret;
0502 }
0503 
0504 /*
0505  * On most platforms, we'd rather do straight i2c I/O.
0506  */
0507 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
0508         unsigned char *value)
0509 {
0510     struct i2c_client *client = v4l2_get_subdevdata(sd);
0511     u8 data = reg;
0512     struct i2c_msg msg;
0513     int ret;
0514 
0515     /*
0516      * Send out the register address...
0517      */
0518     msg.addr = client->addr;
0519     msg.flags = 0;
0520     msg.len = 1;
0521     msg.buf = &data;
0522     ret = i2c_transfer(client->adapter, &msg, 1);
0523     if (ret < 0) {
0524         printk(KERN_ERR "Error %d on register write\n", ret);
0525         return ret;
0526     }
0527     /*
0528      * ...then read back the result.
0529      */
0530     msg.flags = I2C_M_RD;
0531     ret = i2c_transfer(client->adapter, &msg, 1);
0532     if (ret >= 0) {
0533         *value = data;
0534         ret = 0;
0535     }
0536     return ret;
0537 }
0538 
0539 
0540 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
0541         unsigned char value)
0542 {
0543     struct i2c_client *client = v4l2_get_subdevdata(sd);
0544     struct i2c_msg msg;
0545     unsigned char data[2] = { reg, value };
0546     int ret;
0547 
0548     msg.addr = client->addr;
0549     msg.flags = 0;
0550     msg.len = 2;
0551     msg.buf = data;
0552     ret = i2c_transfer(client->adapter, &msg, 1);
0553     if (ret > 0)
0554         ret = 0;
0555     if (reg == REG_COM7 && (value & COM7_RESET))
0556         msleep(5);  /* Wait for reset to run */
0557     return ret;
0558 }
0559 
0560 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
0561         unsigned char *value)
0562 {
0563     struct ov7670_info *info = to_state(sd);
0564 
0565     if (info->use_smbus)
0566         return ov7670_read_smbus(sd, reg, value);
0567     else
0568         return ov7670_read_i2c(sd, reg, value);
0569 }
0570 
0571 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
0572         unsigned char value)
0573 {
0574     struct ov7670_info *info = to_state(sd);
0575 
0576     if (info->use_smbus)
0577         return ov7670_write_smbus(sd, reg, value);
0578     else
0579         return ov7670_write_i2c(sd, reg, value);
0580 }
0581 
0582 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg,
0583         unsigned char mask, unsigned char value)
0584 {
0585     unsigned char orig;
0586     int ret;
0587 
0588     ret = ov7670_read(sd, reg, &orig);
0589     if (ret)
0590         return ret;
0591 
0592     return ov7670_write(sd, reg, (orig & ~mask) | (value & mask));
0593 }
0594 
0595 /*
0596  * Write a list of register settings; ff/ff stops the process.
0597  */
0598 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
0599 {
0600     while (vals->reg_num != 0xff || vals->value != 0xff) {
0601         int ret = ov7670_write(sd, vals->reg_num, vals->value);
0602 
0603         if (ret < 0)
0604             return ret;
0605         vals++;
0606     }
0607     return 0;
0608 }
0609 
0610 
0611 /*
0612  * Stuff that knows about the sensor.
0613  */
0614 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
0615 {
0616     ov7670_write(sd, REG_COM7, COM7_RESET);
0617     msleep(1);
0618     return 0;
0619 }
0620 
0621 
0622 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
0623 {
0624     return ov7670_write_array(sd, ov7670_default_regs);
0625 }
0626 
0627 static int ov7670_detect(struct v4l2_subdev *sd)
0628 {
0629     unsigned char v;
0630     int ret;
0631 
0632     ret = ov7670_init(sd, 0);
0633     if (ret < 0)
0634         return ret;
0635     ret = ov7670_read(sd, REG_MIDH, &v);
0636     if (ret < 0)
0637         return ret;
0638     if (v != 0x7f) /* OV manuf. id. */
0639         return -ENODEV;
0640     ret = ov7670_read(sd, REG_MIDL, &v);
0641     if (ret < 0)
0642         return ret;
0643     if (v != 0xa2)
0644         return -ENODEV;
0645     /*
0646      * OK, we know we have an OmniVision chip...but which one?
0647      */
0648     ret = ov7670_read(sd, REG_PID, &v);
0649     if (ret < 0)
0650         return ret;
0651     if (v != 0x76)  /* PID + VER = 0x76 / 0x73 */
0652         return -ENODEV;
0653     ret = ov7670_read(sd, REG_VER, &v);
0654     if (ret < 0)
0655         return ret;
0656     if (v != 0x73)  /* PID + VER = 0x76 / 0x73 */
0657         return -ENODEV;
0658     return 0;
0659 }
0660 
0661 
0662 /*
0663  * Store information about the video data format.  The color matrix
0664  * is deeply tied into the format, so keep the relevant values here.
0665  * The magic matrix numbers come from OmniVision.
0666  */
0667 static struct ov7670_format_struct {
0668     u32 mbus_code;
0669     enum v4l2_colorspace colorspace;
0670     struct regval_list *regs;
0671     int cmatrix[CMATRIX_LEN];
0672 } ov7670_formats[] = {
0673     {
0674         .mbus_code  = MEDIA_BUS_FMT_YUYV8_2X8,
0675         .colorspace = V4L2_COLORSPACE_SRGB,
0676         .regs       = ov7670_fmt_yuv422,
0677         .cmatrix    = { 128, -128, 0, -34, -94, 128 },
0678     },
0679     {
0680         .mbus_code  = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
0681         .colorspace = V4L2_COLORSPACE_SRGB,
0682         .regs       = ov7670_fmt_rgb444,
0683         .cmatrix    = { 179, -179, 0, -61, -176, 228 },
0684     },
0685     {
0686         .mbus_code  = MEDIA_BUS_FMT_RGB565_2X8_LE,
0687         .colorspace = V4L2_COLORSPACE_SRGB,
0688         .regs       = ov7670_fmt_rgb565,
0689         .cmatrix    = { 179, -179, 0, -61, -176, 228 },
0690     },
0691     {
0692         .mbus_code  = MEDIA_BUS_FMT_SBGGR8_1X8,
0693         .colorspace = V4L2_COLORSPACE_SRGB,
0694         .regs       = ov7670_fmt_raw,
0695         .cmatrix    = { 0, 0, 0, 0, 0, 0 },
0696     },
0697 };
0698 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
0699 
0700 
0701 /*
0702  * Then there is the issue of window sizes.  Try to capture the info here.
0703  */
0704 
0705 /*
0706  * QCIF mode is done (by OV) in a very strange way - it actually looks like
0707  * VGA with weird scaling options - they do *not* use the canned QCIF mode
0708  * which is allegedly provided by the sensor.  So here's the weird register
0709  * settings.
0710  */
0711 static struct regval_list ov7670_qcif_regs[] = {
0712     { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
0713     { REG_COM3, COM3_DCWEN },
0714     { REG_COM14, COM14_DCWEN | 0x01},
0715     { 0x73, 0xf1 },
0716     { 0xa2, 0x52 },
0717     { 0x7b, 0x1c },
0718     { 0x7c, 0x28 },
0719     { 0x7d, 0x3c },
0720     { 0x7f, 0x69 },
0721     { REG_COM9, 0x38 },
0722     { 0xa1, 0x0b },
0723     { 0x74, 0x19 },
0724     { 0x9a, 0x80 },
0725     { 0x43, 0x14 },
0726     { REG_COM13, 0xc0 },
0727     { 0xff, 0xff },
0728 };
0729 
0730 static struct ov7670_win_size ov7670_win_sizes[] = {
0731     /* VGA */
0732     {
0733         .width      = VGA_WIDTH,
0734         .height     = VGA_HEIGHT,
0735         .com7_bit   = COM7_FMT_VGA,
0736         .hstart     = 158,  /* These values from */
0737         .hstop      =  14,  /* Omnivision */
0738         .vstart     =  10,
0739         .vstop      = 490,
0740         .regs       = NULL,
0741     },
0742     /* CIF */
0743     {
0744         .width      = CIF_WIDTH,
0745         .height     = CIF_HEIGHT,
0746         .com7_bit   = COM7_FMT_CIF,
0747         .hstart     = 170,  /* Empirically determined */
0748         .hstop      =  90,
0749         .vstart     =  14,
0750         .vstop      = 494,
0751         .regs       = NULL,
0752     },
0753     /* QVGA */
0754     {
0755         .width      = QVGA_WIDTH,
0756         .height     = QVGA_HEIGHT,
0757         .com7_bit   = COM7_FMT_QVGA,
0758         .hstart     = 168,  /* Empirically determined */
0759         .hstop      =  24,
0760         .vstart     =  12,
0761         .vstop      = 492,
0762         .regs       = NULL,
0763     },
0764     /* QCIF */
0765     {
0766         .width      = QCIF_WIDTH,
0767         .height     = QCIF_HEIGHT,
0768         .com7_bit   = COM7_FMT_VGA, /* see comment above */
0769         .hstart     = 456,  /* Empirically determined */
0770         .hstop      =  24,
0771         .vstart     =  14,
0772         .vstop      = 494,
0773         .regs       = ov7670_qcif_regs,
0774     }
0775 };
0776 
0777 static struct ov7670_win_size ov7675_win_sizes[] = {
0778     /*
0779      * Currently, only VGA is supported. Theoretically it could be possible
0780      * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
0781      * base and tweak them empirically could be required.
0782      */
0783     {
0784         .width      = VGA_WIDTH,
0785         .height     = VGA_HEIGHT,
0786         .com7_bit   = COM7_FMT_VGA,
0787         .hstart     = 158,  /* These values from */
0788         .hstop      =  14,  /* Omnivision */
0789         .vstart     =  14,  /* Empirically determined */
0790         .vstop      = 494,
0791         .regs       = NULL,
0792     }
0793 };
0794 
0795 static void ov7675_get_framerate(struct v4l2_subdev *sd,
0796                  struct v4l2_fract *tpf)
0797 {
0798     struct ov7670_info *info = to_state(sd);
0799     u32 clkrc = info->clkrc;
0800     int pll_factor;
0801 
0802     if (info->pll_bypass)
0803         pll_factor = 1;
0804     else
0805         pll_factor = PLL_FACTOR;
0806 
0807     clkrc++;
0808     if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
0809         clkrc = (clkrc >> 1);
0810 
0811     tpf->numerator = 1;
0812     tpf->denominator = (5 * pll_factor * info->clock_speed) /
0813             (4 * clkrc);
0814 }
0815 
0816 static int ov7675_apply_framerate(struct v4l2_subdev *sd)
0817 {
0818     struct ov7670_info *info = to_state(sd);
0819     int ret;
0820 
0821     ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
0822     if (ret < 0)
0823         return ret;
0824 
0825     return ov7670_write(sd, REG_DBLV,
0826                 info->pll_bypass ? DBLV_BYPASS : DBLV_X4);
0827 }
0828 
0829 static int ov7675_set_framerate(struct v4l2_subdev *sd,
0830                  struct v4l2_fract *tpf)
0831 {
0832     struct ov7670_info *info = to_state(sd);
0833     u32 clkrc;
0834     int pll_factor;
0835 
0836     /*
0837      * The formula is fps = 5/4*pixclk for YUV/RGB and
0838      * fps = 5/2*pixclk for RAW.
0839      *
0840      * pixclk = clock_speed / (clkrc + 1) * PLLfactor
0841      *
0842      */
0843     if (tpf->numerator == 0 || tpf->denominator == 0) {
0844         clkrc = 0;
0845     } else {
0846         pll_factor = info->pll_bypass ? 1 : PLL_FACTOR;
0847         clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
0848             (4 * tpf->denominator);
0849         if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
0850             clkrc = (clkrc << 1);
0851         clkrc--;
0852     }
0853 
0854     /*
0855      * The datasheet claims that clkrc = 0 will divide the input clock by 1
0856      * but we've checked with an oscilloscope that it divides by 2 instead.
0857      * So, if clkrc = 0 just bypass the divider.
0858      */
0859     if (clkrc <= 0)
0860         clkrc = CLK_EXT;
0861     else if (clkrc > CLK_SCALE)
0862         clkrc = CLK_SCALE;
0863     info->clkrc = clkrc;
0864 
0865     /* Recalculate frame rate */
0866     ov7675_get_framerate(sd, tpf);
0867 
0868     /*
0869      * If the device is not powered up by the host driver do
0870      * not apply any changes to H/W at this time. Instead
0871      * the framerate will be restored right after power-up.
0872      */
0873     if (info->on)
0874         return ov7675_apply_framerate(sd);
0875 
0876     return 0;
0877 }
0878 
0879 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
0880                  struct v4l2_fract *tpf)
0881 {
0882     struct ov7670_info *info = to_state(sd);
0883 
0884     tpf->numerator = 1;
0885     tpf->denominator = info->clock_speed;
0886     if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
0887         tpf->denominator /= (info->clkrc & CLK_SCALE);
0888 }
0889 
0890 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
0891                     struct v4l2_fract *tpf)
0892 {
0893     struct ov7670_info *info = to_state(sd);
0894     int div;
0895 
0896     if (tpf->numerator == 0 || tpf->denominator == 0)
0897         div = 1;  /* Reset to full rate */
0898     else
0899         div = (tpf->numerator * info->clock_speed) / tpf->denominator;
0900     if (div == 0)
0901         div = 1;
0902     else if (div > CLK_SCALE)
0903         div = CLK_SCALE;
0904     info->clkrc = (info->clkrc & 0x80) | div;
0905     tpf->numerator = 1;
0906     tpf->denominator = info->clock_speed / div;
0907 
0908     /*
0909      * If the device is not powered up by the host driver do
0910      * not apply any changes to H/W at this time. Instead
0911      * the framerate will be restored right after power-up.
0912      */
0913     if (info->on)
0914         return ov7670_write(sd, REG_CLKRC, info->clkrc);
0915 
0916     return 0;
0917 }
0918 
0919 /*
0920  * Store a set of start/stop values into the camera.
0921  */
0922 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
0923         int vstart, int vstop)
0924 {
0925     int ret;
0926     unsigned char v;
0927     /*
0928      * Horizontal: 11 bits, top 8 live in hstart and hstop.  Bottom 3 of
0929      * hstart are in href[2:0], bottom 3 of hstop in href[5:3].  There is
0930      * a mystery "edge offset" value in the top two bits of href.
0931      */
0932     ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
0933     if (ret)
0934         return ret;
0935     ret = ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
0936     if (ret)
0937         return ret;
0938     ret = ov7670_read(sd, REG_HREF, &v);
0939     if (ret)
0940         return ret;
0941     v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
0942     msleep(10);
0943     ret = ov7670_write(sd, REG_HREF, v);
0944     if (ret)
0945         return ret;
0946     /* Vertical: similar arrangement, but only 10 bits. */
0947     ret = ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
0948     if (ret)
0949         return ret;
0950     ret = ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
0951     if (ret)
0952         return ret;
0953     ret = ov7670_read(sd, REG_VREF, &v);
0954     if (ret)
0955         return ret;
0956     v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
0957     msleep(10);
0958     return ov7670_write(sd, REG_VREF, v);
0959 }
0960 
0961 
0962 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
0963         struct v4l2_subdev_state *sd_state,
0964         struct v4l2_subdev_mbus_code_enum *code)
0965 {
0966     if (code->pad || code->index >= N_OV7670_FMTS)
0967         return -EINVAL;
0968 
0969     code->code = ov7670_formats[code->index].mbus_code;
0970     return 0;
0971 }
0972 
0973 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
0974         struct v4l2_mbus_framefmt *fmt,
0975         struct ov7670_format_struct **ret_fmt,
0976         struct ov7670_win_size **ret_wsize)
0977 {
0978     int index, i;
0979     struct ov7670_win_size *wsize;
0980     struct ov7670_info *info = to_state(sd);
0981     unsigned int n_win_sizes = info->devtype->n_win_sizes;
0982     unsigned int win_sizes_limit = n_win_sizes;
0983 
0984     for (index = 0; index < N_OV7670_FMTS; index++)
0985         if (ov7670_formats[index].mbus_code == fmt->code)
0986             break;
0987     if (index >= N_OV7670_FMTS) {
0988         /* default to first format */
0989         index = 0;
0990         fmt->code = ov7670_formats[0].mbus_code;
0991     }
0992     if (ret_fmt != NULL)
0993         *ret_fmt = ov7670_formats + index;
0994     /*
0995      * Fields: the OV devices claim to be progressive.
0996      */
0997     fmt->field = V4L2_FIELD_NONE;
0998 
0999     /*
1000      * Don't consider values that don't match min_height and min_width
1001      * constraints.
1002      */
1003     if (info->min_width || info->min_height)
1004         for (i = 0; i < n_win_sizes; i++) {
1005             wsize = info->devtype->win_sizes + i;
1006 
1007             if (wsize->width < info->min_width ||
1008                 wsize->height < info->min_height) {
1009                 win_sizes_limit = i;
1010                 break;
1011             }
1012         }
1013     /*
1014      * Round requested image size down to the nearest
1015      * we support, but not below the smallest.
1016      */
1017     for (wsize = info->devtype->win_sizes;
1018          wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
1019         if (fmt->width >= wsize->width && fmt->height >= wsize->height)
1020             break;
1021     if (wsize >= info->devtype->win_sizes + win_sizes_limit)
1022         wsize--;   /* Take the smallest one */
1023     if (ret_wsize != NULL)
1024         *ret_wsize = wsize;
1025     /*
1026      * Note the size we'll actually handle.
1027      */
1028     fmt->width = wsize->width;
1029     fmt->height = wsize->height;
1030     fmt->colorspace = ov7670_formats[index].colorspace;
1031 
1032     info->format = *fmt;
1033 
1034     return 0;
1035 }
1036 
1037 static int ov7670_apply_fmt(struct v4l2_subdev *sd)
1038 {
1039     struct ov7670_info *info = to_state(sd);
1040     struct ov7670_win_size *wsize = info->wsize;
1041     unsigned char com7, com10 = 0;
1042     int ret;
1043 
1044     /*
1045      * COM7 is a pain in the ass, it doesn't like to be read then
1046      * quickly written afterward.  But we have everything we need
1047      * to set it absolutely here, as long as the format-specific
1048      * register sets list it first.
1049      */
1050     com7 = info->fmt->regs[0].value;
1051     com7 |= wsize->com7_bit;
1052     ret = ov7670_write(sd, REG_COM7, com7);
1053     if (ret)
1054         return ret;
1055 
1056     /*
1057      * Configure the media bus through COM10 register
1058      */
1059     if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1060         com10 |= COM10_VS_NEG;
1061     if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1062         com10 |= COM10_HREF_REV;
1063     if (info->pclk_hb_disable)
1064         com10 |= COM10_PCLK_HB;
1065     ret = ov7670_write(sd, REG_COM10, com10);
1066     if (ret)
1067         return ret;
1068 
1069     /*
1070      * Now write the rest of the array.  Also store start/stops
1071      */
1072     ret = ov7670_write_array(sd, info->fmt->regs + 1);
1073     if (ret)
1074         return ret;
1075 
1076     ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1077                 wsize->vstop);
1078     if (ret)
1079         return ret;
1080 
1081     if (wsize->regs) {
1082         ret = ov7670_write_array(sd, wsize->regs);
1083         if (ret)
1084             return ret;
1085     }
1086 
1087     /*
1088      * If we're running RGB565, we must rewrite clkrc after setting
1089      * the other parameters or the image looks poor.  If we're *not*
1090      * doing RGB565, we must not rewrite clkrc or the image looks
1091      * *really* poor.
1092      *
1093      * (Update) Now that we retain clkrc state, we should be able
1094      * to write it unconditionally, and that will make the frame
1095      * rate persistent too.
1096      */
1097     ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1098     if (ret)
1099         return ret;
1100 
1101     return 0;
1102 }
1103 
1104 /*
1105  * Set a format.
1106  */
1107 static int ov7670_set_fmt(struct v4l2_subdev *sd,
1108         struct v4l2_subdev_state *sd_state,
1109         struct v4l2_subdev_format *format)
1110 {
1111     struct ov7670_info *info = to_state(sd);
1112 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1113     struct v4l2_mbus_framefmt *mbus_fmt;
1114 #endif
1115     int ret;
1116 
1117     if (format->pad)
1118         return -EINVAL;
1119 
1120     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1121         ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
1122         if (ret)
1123             return ret;
1124 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1125         mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state,
1126                               format->pad);
1127         *mbus_fmt = format->format;
1128 #endif
1129         return 0;
1130     }
1131 
1132     ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize);
1133     if (ret)
1134         return ret;
1135 
1136     /*
1137      * If the device is not powered up by the host driver do
1138      * not apply any changes to H/W at this time. Instead
1139      * the frame format will be restored right after power-up.
1140      */
1141     if (info->on)
1142         return ov7670_apply_fmt(sd);
1143 
1144     return 0;
1145 }
1146 
1147 static int ov7670_get_fmt(struct v4l2_subdev *sd,
1148               struct v4l2_subdev_state *sd_state,
1149               struct v4l2_subdev_format *format)
1150 {
1151     struct ov7670_info *info = to_state(sd);
1152 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1153     struct v4l2_mbus_framefmt *mbus_fmt;
1154 #endif
1155 
1156     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1157 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1158         mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
1159         format->format = *mbus_fmt;
1160         return 0;
1161 #else
1162         return -EINVAL;
1163 #endif
1164     } else {
1165         format->format = info->format;
1166     }
1167 
1168     return 0;
1169 }
1170 
1171 /*
1172  * Implement G/S_PARM.  There is a "high quality" mode we could try
1173  * to do someday; for now, we just do the frame rate tweak.
1174  */
1175 static int ov7670_g_frame_interval(struct v4l2_subdev *sd,
1176                    struct v4l2_subdev_frame_interval *ival)
1177 {
1178     struct ov7670_info *info = to_state(sd);
1179 
1180 
1181     info->devtype->get_framerate(sd, &ival->interval);
1182 
1183     return 0;
1184 }
1185 
1186 static int ov7670_s_frame_interval(struct v4l2_subdev *sd,
1187                    struct v4l2_subdev_frame_interval *ival)
1188 {
1189     struct v4l2_fract *tpf = &ival->interval;
1190     struct ov7670_info *info = to_state(sd);
1191 
1192 
1193     return info->devtype->set_framerate(sd, tpf);
1194 }
1195 
1196 
1197 /*
1198  * Frame intervals.  Since frame rates are controlled with the clock
1199  * divider, we can only do 30/n for integer n values.  So no continuous
1200  * or stepwise options.  Here we just pick a handful of logical values.
1201  */
1202 
1203 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
1204 
1205 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
1206                       struct v4l2_subdev_state *sd_state,
1207                       struct v4l2_subdev_frame_interval_enum *fie)
1208 {
1209     struct ov7670_info *info = to_state(sd);
1210     unsigned int n_win_sizes = info->devtype->n_win_sizes;
1211     int i;
1212 
1213     if (fie->pad)
1214         return -EINVAL;
1215     if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1216         return -EINVAL;
1217 
1218     /*
1219      * Check if the width/height is valid.
1220      *
1221      * If a minimum width/height was requested, filter out the capture
1222      * windows that fall outside that.
1223      */
1224     for (i = 0; i < n_win_sizes; i++) {
1225         struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1226 
1227         if (info->min_width && win->width < info->min_width)
1228             continue;
1229         if (info->min_height && win->height < info->min_height)
1230             continue;
1231         if (fie->width == win->width && fie->height == win->height)
1232             break;
1233     }
1234     if (i == n_win_sizes)
1235         return -EINVAL;
1236     fie->interval.numerator = 1;
1237     fie->interval.denominator = ov7670_frame_rates[fie->index];
1238     return 0;
1239 }
1240 
1241 /*
1242  * Frame size enumeration
1243  */
1244 static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
1245                   struct v4l2_subdev_state *sd_state,
1246                   struct v4l2_subdev_frame_size_enum *fse)
1247 {
1248     struct ov7670_info *info = to_state(sd);
1249     int i;
1250     int num_valid = -1;
1251     __u32 index = fse->index;
1252     unsigned int n_win_sizes = info->devtype->n_win_sizes;
1253 
1254     if (fse->pad)
1255         return -EINVAL;
1256 
1257     /*
1258      * If a minimum width/height was requested, filter out the capture
1259      * windows that fall outside that.
1260      */
1261     for (i = 0; i < n_win_sizes; i++) {
1262         struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1263 
1264         if (info->min_width && win->width < info->min_width)
1265             continue;
1266         if (info->min_height && win->height < info->min_height)
1267             continue;
1268         if (index == ++num_valid) {
1269             fse->min_width = fse->max_width = win->width;
1270             fse->min_height = fse->max_height = win->height;
1271             return 0;
1272         }
1273     }
1274 
1275     return -EINVAL;
1276 }
1277 
1278 /*
1279  * Code for dealing with controls.
1280  */
1281 
1282 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
1283         int matrix[CMATRIX_LEN])
1284 {
1285     int i, ret;
1286     unsigned char signbits = 0;
1287 
1288     /*
1289      * Weird crap seems to exist in the upper part of
1290      * the sign bits register, so let's preserve it.
1291      */
1292     ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
1293     signbits &= 0xc0;
1294 
1295     for (i = 0; i < CMATRIX_LEN; i++) {
1296         unsigned char raw;
1297 
1298         if (matrix[i] < 0) {
1299             signbits |= (1 << i);
1300             if (matrix[i] < -255)
1301                 raw = 0xff;
1302             else
1303                 raw = (-1 * matrix[i]) & 0xff;
1304         } else {
1305             if (matrix[i] > 255)
1306                 raw = 0xff;
1307             else
1308                 raw = matrix[i] & 0xff;
1309         }
1310         ret = ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1311         if (ret)
1312             return ret;
1313     }
1314     return ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
1315 }
1316 
1317 
1318 /*
1319  * Hue also requires messing with the color matrix.  It also requires
1320  * trig functions, which tend not to be well supported in the kernel.
1321  * So here is a simple table of sine values, 0-90 degrees, in steps
1322  * of five degrees.  Values are multiplied by 1000.
1323  *
1324  * The following naive approximate trig functions require an argument
1325  * carefully limited to -180 <= theta <= 180.
1326  */
1327 #define SIN_STEP 5
1328 static const int ov7670_sin_table[] = {
1329        0,    87,   173,   258,   342,   422,
1330      499,   573,   642,   707,   766,   819,
1331      866,   906,   939,   965,   984,   996,
1332     1000
1333 };
1334 
1335 static int ov7670_sine(int theta)
1336 {
1337     int chs = 1;
1338     int sine;
1339 
1340     if (theta < 0) {
1341         theta = -theta;
1342         chs = -1;
1343     }
1344     if (theta <= 90)
1345         sine = ov7670_sin_table[theta/SIN_STEP];
1346     else {
1347         theta -= 90;
1348         sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1349     }
1350     return sine*chs;
1351 }
1352 
1353 static int ov7670_cosine(int theta)
1354 {
1355     theta = 90 - theta;
1356     if (theta > 180)
1357         theta -= 360;
1358     else if (theta < -180)
1359         theta += 360;
1360     return ov7670_sine(theta);
1361 }
1362 
1363 
1364 
1365 
1366 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1367         int matrix[CMATRIX_LEN], int sat, int hue)
1368 {
1369     int i;
1370     /*
1371      * Apply the current saturation setting first.
1372      */
1373     for (i = 0; i < CMATRIX_LEN; i++)
1374         matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
1375     /*
1376      * Then, if need be, rotate the hue value.
1377      */
1378     if (hue != 0) {
1379         int sinth, costh, tmpmatrix[CMATRIX_LEN];
1380 
1381         memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1382         sinth = ov7670_sine(hue);
1383         costh = ov7670_cosine(hue);
1384 
1385         matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1386         matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1387         matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1388         matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1389         matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1390         matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1391     }
1392 }
1393 
1394 
1395 
1396 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
1397 {
1398     struct ov7670_info *info = to_state(sd);
1399     int matrix[CMATRIX_LEN];
1400 
1401     ov7670_calc_cmatrix(info, matrix, sat, hue);
1402     return ov7670_store_cmatrix(sd, matrix);
1403 }
1404 
1405 
1406 /*
1407  * Some weird registers seem to store values in a sign/magnitude format!
1408  */
1409 
1410 static unsigned char ov7670_abs_to_sm(unsigned char v)
1411 {
1412     if (v > 127)
1413         return v & 0x7f;
1414     return (128 - v) | 0x80;
1415 }
1416 
1417 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1418 {
1419     unsigned char com8 = 0, v;
1420 
1421     ov7670_read(sd, REG_COM8, &com8);
1422     com8 &= ~COM8_AEC;
1423     ov7670_write(sd, REG_COM8, com8);
1424     v = ov7670_abs_to_sm(value);
1425     return ov7670_write(sd, REG_BRIGHT, v);
1426 }
1427 
1428 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1429 {
1430     return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1431 }
1432 
1433 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1434 {
1435     unsigned char v = 0;
1436     int ret;
1437 
1438     ret = ov7670_read(sd, REG_MVFP, &v);
1439     if (ret)
1440         return ret;
1441     if (value)
1442         v |= MVFP_MIRROR;
1443     else
1444         v &= ~MVFP_MIRROR;
1445     msleep(10);  /* FIXME */
1446     return ov7670_write(sd, REG_MVFP, v);
1447 }
1448 
1449 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1450 {
1451     unsigned char v = 0;
1452     int ret;
1453 
1454     ret = ov7670_read(sd, REG_MVFP, &v);
1455     if (ret)
1456         return ret;
1457     if (value)
1458         v |= MVFP_FLIP;
1459     else
1460         v &= ~MVFP_FLIP;
1461     msleep(10);  /* FIXME */
1462     return ov7670_write(sd, REG_MVFP, v);
1463 }
1464 
1465 /*
1466  * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
1467  * the data sheet, the VREF parts should be the most significant, but
1468  * experience shows otherwise.  There seems to be little value in
1469  * messing with the VREF bits, so we leave them alone.
1470  */
1471 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1472 {
1473     int ret;
1474     unsigned char gain;
1475 
1476     ret = ov7670_read(sd, REG_GAIN, &gain);
1477     if (ret)
1478         return ret;
1479     *value = gain;
1480     return 0;
1481 }
1482 
1483 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1484 {
1485     int ret;
1486     unsigned char com8;
1487 
1488     ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1489     if (ret)
1490         return ret;
1491     /* Have to turn off AGC as well */
1492     ret = ov7670_read(sd, REG_COM8, &com8);
1493     if (ret)
1494         return ret;
1495     return ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1496 }
1497 
1498 /*
1499  * Tweak autogain.
1500  */
1501 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1502 {
1503     int ret;
1504     unsigned char com8;
1505 
1506     ret = ov7670_read(sd, REG_COM8, &com8);
1507     if (ret == 0) {
1508         if (value)
1509             com8 |= COM8_AGC;
1510         else
1511             com8 &= ~COM8_AGC;
1512         ret = ov7670_write(sd, REG_COM8, com8);
1513     }
1514     return ret;
1515 }
1516 
1517 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1518 {
1519     int ret;
1520     unsigned char com1, com8, aech, aechh;
1521 
1522     ret = ov7670_read(sd, REG_COM1, &com1) +
1523         ov7670_read(sd, REG_COM8, &com8) +
1524         ov7670_read(sd, REG_AECHH, &aechh);
1525     if (ret)
1526         return ret;
1527 
1528     com1 = (com1 & 0xfc) | (value & 0x03);
1529     aech = (value >> 2) & 0xff;
1530     aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1531     ret = ov7670_write(sd, REG_COM1, com1) +
1532         ov7670_write(sd, REG_AECH, aech) +
1533         ov7670_write(sd, REG_AECHH, aechh);
1534     /* Have to turn off AEC as well */
1535     if (ret == 0)
1536         ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1537     return ret;
1538 }
1539 
1540 /*
1541  * Tweak autoexposure.
1542  */
1543 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1544         enum v4l2_exposure_auto_type value)
1545 {
1546     int ret;
1547     unsigned char com8;
1548 
1549     ret = ov7670_read(sd, REG_COM8, &com8);
1550     if (ret == 0) {
1551         if (value == V4L2_EXPOSURE_AUTO)
1552             com8 |= COM8_AEC;
1553         else
1554             com8 &= ~COM8_AEC;
1555         ret = ov7670_write(sd, REG_COM8, com8);
1556     }
1557     return ret;
1558 }
1559 
1560 static const char * const ov7670_test_pattern_menu[] = {
1561     "No test output",
1562     "Shifting \"1\"",
1563     "8-bar color bar",
1564     "Fade to gray color bar",
1565 };
1566 
1567 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value)
1568 {
1569     int ret;
1570 
1571     ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0,
1572                 value & BIT(0) ? TEST_PATTTERN_0 : 0);
1573     if (ret)
1574         return ret;
1575 
1576     return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1,
1577                 value & BIT(1) ? TEST_PATTTERN_1 : 0);
1578 }
1579 
1580 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1581 {
1582     struct v4l2_subdev *sd = to_sd(ctrl);
1583     struct ov7670_info *info = to_state(sd);
1584 
1585     switch (ctrl->id) {
1586     case V4L2_CID_AUTOGAIN:
1587         return ov7670_g_gain(sd, &info->gain->val);
1588     }
1589     return -EINVAL;
1590 }
1591 
1592 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
1593 {
1594     struct v4l2_subdev *sd = to_sd(ctrl);
1595     struct ov7670_info *info = to_state(sd);
1596 
1597     switch (ctrl->id) {
1598     case V4L2_CID_BRIGHTNESS:
1599         return ov7670_s_brightness(sd, ctrl->val);
1600     case V4L2_CID_CONTRAST:
1601         return ov7670_s_contrast(sd, ctrl->val);
1602     case V4L2_CID_SATURATION:
1603         return ov7670_s_sat_hue(sd,
1604                 info->saturation->val, info->hue->val);
1605     case V4L2_CID_VFLIP:
1606         return ov7670_s_vflip(sd, ctrl->val);
1607     case V4L2_CID_HFLIP:
1608         return ov7670_s_hflip(sd, ctrl->val);
1609     case V4L2_CID_AUTOGAIN:
1610         /* Only set manual gain if auto gain is not explicitly
1611            turned on. */
1612         if (!ctrl->val) {
1613             /* ov7670_s_gain turns off auto gain */
1614             return ov7670_s_gain(sd, info->gain->val);
1615         }
1616         return ov7670_s_autogain(sd, ctrl->val);
1617     case V4L2_CID_EXPOSURE_AUTO:
1618         /* Only set manual exposure if auto exposure is not explicitly
1619            turned on. */
1620         if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1621             /* ov7670_s_exp turns off auto exposure */
1622             return ov7670_s_exp(sd, info->exposure->val);
1623         }
1624         return ov7670_s_autoexp(sd, ctrl->val);
1625     case V4L2_CID_TEST_PATTERN:
1626         return ov7670_s_test_pattern(sd, ctrl->val);
1627     }
1628     return -EINVAL;
1629 }
1630 
1631 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1632     .s_ctrl = ov7670_s_ctrl,
1633     .g_volatile_ctrl = ov7670_g_volatile_ctrl,
1634 };
1635 
1636 #ifdef CONFIG_VIDEO_ADV_DEBUG
1637 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1638 {
1639     unsigned char val = 0;
1640     int ret;
1641 
1642     ret = ov7670_read(sd, reg->reg & 0xff, &val);
1643     reg->val = val;
1644     reg->size = 1;
1645     return ret;
1646 }
1647 
1648 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1649 {
1650     ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1651     return 0;
1652 }
1653 #endif
1654 
1655 static void ov7670_power_on(struct v4l2_subdev *sd)
1656 {
1657     struct ov7670_info *info = to_state(sd);
1658 
1659     if (info->on)
1660         return;
1661 
1662     clk_prepare_enable(info->clk);
1663 
1664     if (info->pwdn_gpio)
1665         gpiod_set_value(info->pwdn_gpio, 0);
1666     if (info->resetb_gpio) {
1667         gpiod_set_value(info->resetb_gpio, 1);
1668         usleep_range(500, 1000);
1669         gpiod_set_value(info->resetb_gpio, 0);
1670     }
1671     if (info->pwdn_gpio || info->resetb_gpio || info->clk)
1672         usleep_range(3000, 5000);
1673 
1674     info->on = true;
1675 }
1676 
1677 static void ov7670_power_off(struct v4l2_subdev *sd)
1678 {
1679     struct ov7670_info *info = to_state(sd);
1680 
1681     if (!info->on)
1682         return;
1683 
1684     clk_disable_unprepare(info->clk);
1685 
1686     if (info->pwdn_gpio)
1687         gpiod_set_value(info->pwdn_gpio, 1);
1688 
1689     info->on = false;
1690 }
1691 
1692 static int ov7670_s_power(struct v4l2_subdev *sd, int on)
1693 {
1694     struct ov7670_info *info = to_state(sd);
1695 
1696     if (info->on == on)
1697         return 0;
1698 
1699     if (on) {
1700         ov7670_power_on(sd);
1701         ov7670_init(sd, 0);
1702         ov7670_apply_fmt(sd);
1703         ov7675_apply_framerate(sd);
1704         v4l2_ctrl_handler_setup(&info->hdl);
1705     } else {
1706         ov7670_power_off(sd);
1707     }
1708 
1709     return 0;
1710 }
1711 
1712 static void ov7670_get_default_format(struct v4l2_subdev *sd,
1713                       struct v4l2_mbus_framefmt *format)
1714 {
1715     struct ov7670_info *info = to_state(sd);
1716 
1717     format->width = info->devtype->win_sizes[0].width;
1718     format->height = info->devtype->win_sizes[0].height;
1719     format->colorspace = info->fmt->colorspace;
1720     format->code = info->fmt->mbus_code;
1721     format->field = V4L2_FIELD_NONE;
1722 }
1723 
1724 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1725 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1726 {
1727     struct v4l2_mbus_framefmt *format =
1728                 v4l2_subdev_get_try_format(sd, fh->state, 0);
1729 
1730     ov7670_get_default_format(sd, format);
1731 
1732     return 0;
1733 }
1734 #endif
1735 
1736 /* ----------------------------------------------------------------------- */
1737 
1738 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1739     .reset = ov7670_reset,
1740     .init = ov7670_init,
1741     .s_power = ov7670_s_power,
1742     .log_status = v4l2_ctrl_subdev_log_status,
1743     .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1744     .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1745 #ifdef CONFIG_VIDEO_ADV_DEBUG
1746     .g_register = ov7670_g_register,
1747     .s_register = ov7670_s_register,
1748 #endif
1749 };
1750 
1751 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1752     .s_frame_interval = ov7670_s_frame_interval,
1753     .g_frame_interval = ov7670_g_frame_interval,
1754 };
1755 
1756 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1757     .enum_frame_interval = ov7670_enum_frame_interval,
1758     .enum_frame_size = ov7670_enum_frame_size,
1759     .enum_mbus_code = ov7670_enum_mbus_code,
1760     .get_fmt = ov7670_get_fmt,
1761     .set_fmt = ov7670_set_fmt,
1762 };
1763 
1764 static const struct v4l2_subdev_ops ov7670_ops = {
1765     .core = &ov7670_core_ops,
1766     .video = &ov7670_video_ops,
1767     .pad = &ov7670_pad_ops,
1768 };
1769 
1770 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1771 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = {
1772     .open = ov7670_open,
1773 };
1774 #endif
1775 
1776 /* ----------------------------------------------------------------------- */
1777 
1778 static const struct ov7670_devtype ov7670_devdata[] = {
1779     [MODEL_OV7670] = {
1780         .win_sizes = ov7670_win_sizes,
1781         .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
1782         .set_framerate = ov7670_set_framerate_legacy,
1783         .get_framerate = ov7670_get_framerate_legacy,
1784     },
1785     [MODEL_OV7675] = {
1786         .win_sizes = ov7675_win_sizes,
1787         .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
1788         .set_framerate = ov7675_set_framerate,
1789         .get_framerate = ov7675_get_framerate,
1790     },
1791 };
1792 
1793 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
1794 {
1795     info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1796             GPIOD_OUT_LOW);
1797     if (IS_ERR(info->pwdn_gpio)) {
1798         dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
1799         return PTR_ERR(info->pwdn_gpio);
1800     }
1801 
1802     info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1803             GPIOD_OUT_LOW);
1804     if (IS_ERR(info->resetb_gpio)) {
1805         dev_info(&client->dev, "can't get %s GPIO\n", "reset");
1806         return PTR_ERR(info->resetb_gpio);
1807     }
1808 
1809     usleep_range(3000, 5000);
1810 
1811     return 0;
1812 }
1813 
1814 /*
1815  * ov7670_parse_dt() - Parse device tree to collect mbus configuration
1816  *          properties
1817  */
1818 static int ov7670_parse_dt(struct device *dev,
1819                struct ov7670_info *info)
1820 {
1821     struct fwnode_handle *fwnode = dev_fwnode(dev);
1822     struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
1823     struct fwnode_handle *ep;
1824     int ret;
1825 
1826     if (!fwnode)
1827         return -EINVAL;
1828 
1829     info->pclk_hb_disable = false;
1830     if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable"))
1831         info->pclk_hb_disable = true;
1832 
1833     ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1834     if (!ep)
1835         return -EINVAL;
1836 
1837     ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
1838     fwnode_handle_put(ep);
1839     if (ret)
1840         return ret;
1841 
1842     if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) {
1843         dev_err(dev, "Unsupported media bus type\n");
1844         return ret;
1845     }
1846     info->mbus_config = bus_cfg.bus.parallel.flags;
1847 
1848     return 0;
1849 }
1850 
1851 static int ov7670_probe(struct i2c_client *client,
1852             const struct i2c_device_id *id)
1853 {
1854     struct v4l2_fract tpf;
1855     struct v4l2_subdev *sd;
1856     struct ov7670_info *info;
1857     int ret;
1858 
1859     info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
1860     if (info == NULL)
1861         return -ENOMEM;
1862     sd = &info->sd;
1863     v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1864 
1865 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1866     sd->internal_ops = &ov7670_subdev_internal_ops;
1867     sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1868 #endif
1869 
1870     info->clock_speed = 30; /* default: a guess */
1871 
1872     if (dev_fwnode(&client->dev)) {
1873         ret = ov7670_parse_dt(&client->dev, info);
1874         if (ret)
1875             return ret;
1876 
1877     } else if (client->dev.platform_data) {
1878         struct ov7670_config *config = client->dev.platform_data;
1879 
1880         /*
1881          * Must apply configuration before initializing device, because it
1882          * selects I/O method.
1883          */
1884         info->min_width = config->min_width;
1885         info->min_height = config->min_height;
1886         info->use_smbus = config->use_smbus;
1887 
1888         if (config->clock_speed)
1889             info->clock_speed = config->clock_speed;
1890 
1891         if (config->pll_bypass)
1892             info->pll_bypass = true;
1893 
1894         if (config->pclk_hb_disable)
1895             info->pclk_hb_disable = true;
1896     }
1897 
1898     info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */
1899     if (IS_ERR(info->clk)) {
1900         ret = PTR_ERR(info->clk);
1901         if (ret == -ENOENT)
1902             info->clk = NULL;
1903         else
1904             return ret;
1905     }
1906 
1907     ret = ov7670_init_gpio(client, info);
1908     if (ret)
1909         return ret;
1910 
1911     ov7670_power_on(sd);
1912 
1913     if (info->clk) {
1914         info->clock_speed = clk_get_rate(info->clk) / 1000000;
1915         if (info->clock_speed < 10 || info->clock_speed > 48) {
1916             ret = -EINVAL;
1917             goto power_off;
1918         }
1919     }
1920 
1921     /* Make sure it's an ov7670 */
1922     ret = ov7670_detect(sd);
1923     if (ret) {
1924         v4l_dbg(1, debug, client,
1925             "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1926             client->addr << 1, client->adapter->name);
1927         goto power_off;
1928     }
1929     v4l_info(client, "chip found @ 0x%02x (%s)\n",
1930             client->addr << 1, client->adapter->name);
1931 
1932     info->devtype = &ov7670_devdata[id->driver_data];
1933     info->fmt = &ov7670_formats[0];
1934     info->wsize = &info->devtype->win_sizes[0];
1935 
1936     ov7670_get_default_format(sd, &info->format);
1937 
1938     info->clkrc = 0;
1939 
1940     /* Set default frame rate to 30 fps */
1941     tpf.numerator = 1;
1942     tpf.denominator = 30;
1943     info->devtype->set_framerate(sd, &tpf);
1944 
1945     v4l2_ctrl_handler_init(&info->hdl, 10);
1946     v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1947             V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1948     v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1949             V4L2_CID_CONTRAST, 0, 127, 1, 64);
1950     v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1951             V4L2_CID_VFLIP, 0, 1, 1, 0);
1952     v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1953             V4L2_CID_HFLIP, 0, 1, 1, 0);
1954     info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1955             V4L2_CID_SATURATION, 0, 256, 1, 128);
1956     info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1957             V4L2_CID_HUE, -180, 180, 5, 0);
1958     info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1959             V4L2_CID_GAIN, 0, 255, 1, 128);
1960     info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1961             V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1962     info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1963             V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1964     info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1965             V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1966             V4L2_EXPOSURE_AUTO);
1967     v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops,
1968             V4L2_CID_TEST_PATTERN,
1969             ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0,
1970             ov7670_test_pattern_menu);
1971     sd->ctrl_handler = &info->hdl;
1972     if (info->hdl.error) {
1973         ret = info->hdl.error;
1974 
1975         goto hdl_free;
1976     }
1977     /*
1978      * We have checked empirically that hw allows to read back the gain
1979      * value chosen by auto gain but that's not the case for auto exposure.
1980      */
1981     v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1982     v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1983                    V4L2_EXPOSURE_MANUAL, false);
1984     v4l2_ctrl_cluster(2, &info->saturation);
1985 
1986 #if defined(CONFIG_MEDIA_CONTROLLER)
1987     info->pad.flags = MEDIA_PAD_FL_SOURCE;
1988     info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1989     ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
1990     if (ret < 0)
1991         goto hdl_free;
1992 #endif
1993 
1994     v4l2_ctrl_handler_setup(&info->hdl);
1995 
1996     ret = v4l2_async_register_subdev(&info->sd);
1997     if (ret < 0)
1998         goto entity_cleanup;
1999 
2000     ov7670_power_off(sd);
2001     return 0;
2002 
2003 entity_cleanup:
2004     media_entity_cleanup(&info->sd.entity);
2005 hdl_free:
2006     v4l2_ctrl_handler_free(&info->hdl);
2007 power_off:
2008     ov7670_power_off(sd);
2009     return ret;
2010 }
2011 
2012 static int ov7670_remove(struct i2c_client *client)
2013 {
2014     struct v4l2_subdev *sd = i2c_get_clientdata(client);
2015     struct ov7670_info *info = to_state(sd);
2016 
2017     v4l2_async_unregister_subdev(sd);
2018     v4l2_ctrl_handler_free(&info->hdl);
2019     media_entity_cleanup(&info->sd.entity);
2020     return 0;
2021 }
2022 
2023 static const struct i2c_device_id ov7670_id[] = {
2024     { "ov7670", MODEL_OV7670 },
2025     { "ov7675", MODEL_OV7675 },
2026     { }
2027 };
2028 MODULE_DEVICE_TABLE(i2c, ov7670_id);
2029 
2030 #if IS_ENABLED(CONFIG_OF)
2031 static const struct of_device_id ov7670_of_match[] = {
2032     { .compatible = "ovti,ov7670", },
2033     { /* sentinel */ },
2034 };
2035 MODULE_DEVICE_TABLE(of, ov7670_of_match);
2036 #endif
2037 
2038 static struct i2c_driver ov7670_driver = {
2039     .driver = {
2040         .name   = "ov7670",
2041         .of_match_table = of_match_ptr(ov7670_of_match),
2042     },
2043     .probe      = ov7670_probe,
2044     .remove     = ov7670_remove,
2045     .id_table   = ov7670_id,
2046 };
2047 
2048 module_i2c_driver(ov7670_driver);
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