Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the OV7251 camera sensor.
0004  *
0005  * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
0006  * Copyright (c) 2017-2018, Linaro Ltd.
0007  */
0008 
0009 #include <linux/bitops.h>
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/i2c.h>
0015 #include <linux/init.h>
0016 #include <linux/module.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/slab.h>
0021 #include <linux/types.h>
0022 #include <media/v4l2-ctrls.h>
0023 #include <media/v4l2-fwnode.h>
0024 #include <media/v4l2-subdev.h>
0025 
0026 #define OV7251_SC_MODE_SELECT       0x0100
0027 #define OV7251_SC_MODE_SELECT_SW_STANDBY    0x0
0028 #define OV7251_SC_MODE_SELECT_STREAMING     0x1
0029 
0030 #define OV7251_CHIP_ID_HIGH     0x300a
0031 #define OV7251_CHIP_ID_HIGH_BYTE    0x77
0032 #define OV7251_CHIP_ID_LOW      0x300b
0033 #define OV7251_CHIP_ID_LOW_BYTE     0x50
0034 #define OV7251_SC_GP_IO_IN1     0x3029
0035 #define OV7251_AEC_EXPO_0       0x3500
0036 #define OV7251_AEC_EXPO_1       0x3501
0037 #define OV7251_AEC_EXPO_2       0x3502
0038 #define OV7251_AEC_AGC_ADJ_0        0x350a
0039 #define OV7251_AEC_AGC_ADJ_1        0x350b
0040 #define OV7251_TIMING_FORMAT1       0x3820
0041 #define OV7251_TIMING_FORMAT1_VFLIP BIT(2)
0042 #define OV7251_TIMING_FORMAT2       0x3821
0043 #define OV7251_TIMING_FORMAT2_MIRROR    BIT(2)
0044 #define OV7251_PRE_ISP_00       0x5e00
0045 #define OV7251_PRE_ISP_00_TEST_PATTERN  BIT(7)
0046 #define OV7251_PLL1_PRE_DIV_REG     0x30b4
0047 #define OV7251_PLL1_MULT_REG        0x30b3
0048 #define OV7251_PLL1_DIVIDER_REG     0x30b1
0049 #define OV7251_PLL1_PIX_DIV_REG     0x30b0
0050 #define OV7251_PLL1_MIPI_DIV_REG    0x30b5
0051 #define OV7251_PLL2_PRE_DIV_REG     0x3098
0052 #define OV7251_PLL2_MULT_REG        0x3099
0053 #define OV7251_PLL2_DIVIDER_REG     0x309d
0054 #define OV7251_PLL2_SYS_DIV_REG     0x309a
0055 #define OV7251_PLL2_ADC_DIV_REG     0x309b
0056 
0057 #define OV7251_NATIVE_WIDTH     656
0058 #define OV7251_NATIVE_HEIGHT        496
0059 #define OV7251_ACTIVE_START_LEFT    4
0060 #define OV7251_ACTIVE_START_TOP     4
0061 #define OV7251_ACTIVE_WIDTH     648
0062 #define OV7251_ACTIVE_HEIGHT        488
0063 
0064 #define OV7251_FIXED_PPL        928
0065 #define OV7251_TIMING_VTS_REG       0x380e
0066 #define OV7251_TIMING_MIN_VTS       1
0067 #define OV7251_TIMING_MAX_VTS       0xffff
0068 #define OV7251_INTEGRATION_MARGIN   20
0069 
0070 struct reg_value {
0071     u16 reg;
0072     u8 val;
0073 };
0074 
0075 struct ov7251_mode_info {
0076     u32 width;
0077     u32 height;
0078     u32 vts;
0079     const struct reg_value *data;
0080     u32 data_size;
0081     u32 pixel_clock;
0082     u32 link_freq;
0083     u16 exposure_max;
0084     u16 exposure_def;
0085     struct v4l2_fract timeperframe;
0086 };
0087 
0088 struct ov7251_pll1_cfg {
0089     unsigned int pre_div;
0090     unsigned int mult;
0091     unsigned int div;
0092     unsigned int pix_div;
0093     unsigned int mipi_div;
0094 };
0095 
0096 struct ov7251_pll2_cfg {
0097     unsigned int pre_div;
0098     unsigned int mult;
0099     unsigned int div;
0100     unsigned int sys_div;
0101     unsigned int adc_div;
0102 };
0103 
0104 /*
0105  * Rubbish ordering, but only PLL1 needs to have a separate configuration per
0106  * link frequency and the array member needs to be last.
0107  */
0108 struct ov7251_pll_cfgs {
0109     const struct ov7251_pll2_cfg *pll2;
0110     const struct ov7251_pll1_cfg *pll1[];
0111 };
0112 
0113 enum xclk_rate {
0114     OV7251_19_2_MHZ,
0115     OV7251_24_MHZ,
0116     OV7251_NUM_SUPPORTED_RATES
0117 };
0118 
0119 enum supported_link_freqs {
0120     OV7251_LINK_FREQ_240_MHZ,
0121     OV7251_LINK_FREQ_319_2_MHZ,
0122     OV7251_NUM_SUPPORTED_LINK_FREQS
0123 };
0124 
0125 struct ov7251 {
0126     struct i2c_client *i2c_client;
0127     struct device *dev;
0128     struct v4l2_subdev sd;
0129     struct media_pad pad;
0130     struct v4l2_fwnode_endpoint ep;
0131     struct v4l2_mbus_framefmt fmt;
0132     struct v4l2_rect crop;
0133     struct clk *xclk;
0134     u32 xclk_freq;
0135 
0136     struct regulator *io_regulator;
0137     struct regulator *core_regulator;
0138     struct regulator *analog_regulator;
0139 
0140     const struct ov7251_pll_cfgs *pll_cfgs;
0141     enum supported_link_freqs link_freq_idx;
0142     const struct ov7251_mode_info *current_mode;
0143 
0144     struct v4l2_ctrl_handler ctrls;
0145     struct v4l2_ctrl *pixel_clock;
0146     struct v4l2_ctrl *link_freq;
0147     struct v4l2_ctrl *exposure;
0148     struct v4l2_ctrl *gain;
0149     struct v4l2_ctrl *hblank;
0150     struct v4l2_ctrl *vblank;
0151 
0152     /* Cached register values */
0153     u8 aec_pk_manual;
0154     u8 pre_isp_00;
0155     u8 timing_format1;
0156     u8 timing_format2;
0157 
0158     struct mutex lock; /* lock to protect power state, ctrls and mode */
0159     bool power_on;
0160 
0161     struct gpio_desc *enable_gpio;
0162 };
0163 
0164 static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
0165 {
0166     return container_of(sd, struct ov7251, sd);
0167 }
0168 
0169 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_240_mhz = {
0170     .pre_div = 0x03,
0171     .mult = 0x4b,
0172     .div = 0x01,
0173     .pix_div = 0x0a,
0174     .mipi_div = 0x05,
0175 };
0176 
0177 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_319_2_mhz = {
0178     .pre_div = 0x01,
0179     .mult = 0x85,
0180     .div = 0x04,
0181     .pix_div = 0x0a,
0182     .mipi_div = 0x05,
0183 };
0184 
0185 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = {
0186     .pre_div = 0x03,
0187     .mult = 0x64,
0188     .div = 0x01,
0189     .pix_div = 0x0a,
0190     .mipi_div = 0x05,
0191 };
0192 
0193 static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_319_2_mhz = {
0194     .pre_div = 0x05,
0195     .mult = 0x85,
0196     .div = 0x02,
0197     .pix_div = 0x0a,
0198     .mipi_div = 0x05,
0199 };
0200 
0201 static const struct ov7251_pll2_cfg ov7251_pll2_cfg_19_2_mhz = {
0202     .pre_div = 0x04,
0203     .mult = 0x32,
0204     .div = 0x00,
0205     .sys_div = 0x05,
0206     .adc_div = 0x04,
0207 };
0208 
0209 static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = {
0210     .pre_div = 0x04,
0211     .mult = 0x28,
0212     .div = 0x00,
0213     .sys_div = 0x05,
0214     .adc_div = 0x04,
0215 };
0216 
0217 static const struct ov7251_pll_cfgs ov7251_pll_cfgs_19_2_mhz = {
0218     .pll2 = &ov7251_pll2_cfg_19_2_mhz,
0219     .pll1 = {
0220         [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_19_2_mhz_240_mhz,
0221         [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_19_2_mhz_319_2_mhz,
0222     },
0223 };
0224 
0225 static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = {
0226     .pll2 = &ov7251_pll2_cfg_24_mhz,
0227     .pll1 = {
0228         [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz,
0229         [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_24_mhz_319_2_mhz,
0230     },
0231 };
0232 
0233 static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = {
0234     [OV7251_19_2_MHZ] = &ov7251_pll_cfgs_19_2_mhz,
0235     [OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz,
0236 };
0237 
0238 static const struct reg_value ov7251_global_init_setting[] = {
0239     { 0x0103, 0x01 },
0240     { 0x303b, 0x02 },
0241 };
0242 
0243 static const struct reg_value ov7251_setting_vga_30fps[] = {
0244     { 0x3005, 0x00 },
0245     { 0x3012, 0xc0 },
0246     { 0x3013, 0xd2 },
0247     { 0x3014, 0x04 },
0248     { 0x3016, 0xf0 },
0249     { 0x3017, 0xf0 },
0250     { 0x3018, 0xf0 },
0251     { 0x301a, 0xf0 },
0252     { 0x301b, 0xf0 },
0253     { 0x301c, 0xf0 },
0254     { 0x3023, 0x05 },
0255     { 0x3037, 0xf0 },
0256     { 0x3106, 0xda },
0257     { 0x3503, 0x07 },
0258     { 0x3509, 0x10 },
0259     { 0x3600, 0x1c },
0260     { 0x3602, 0x62 },
0261     { 0x3620, 0xb7 },
0262     { 0x3622, 0x04 },
0263     { 0x3626, 0x21 },
0264     { 0x3627, 0x30 },
0265     { 0x3630, 0x44 },
0266     { 0x3631, 0x35 },
0267     { 0x3634, 0x60 },
0268     { 0x3636, 0x00 },
0269     { 0x3662, 0x01 },
0270     { 0x3663, 0x70 },
0271     { 0x3664, 0x50 },
0272     { 0x3666, 0x0a },
0273     { 0x3669, 0x1a },
0274     { 0x366a, 0x00 },
0275     { 0x366b, 0x50 },
0276     { 0x3673, 0x01 },
0277     { 0x3674, 0xff },
0278     { 0x3675, 0x03 },
0279     { 0x3705, 0xc1 },
0280     { 0x3709, 0x40 },
0281     { 0x373c, 0x08 },
0282     { 0x3742, 0x00 },
0283     { 0x3757, 0xb3 },
0284     { 0x3788, 0x00 },
0285     { 0x37a8, 0x01 },
0286     { 0x37a9, 0xc0 },
0287     { 0x3800, 0x00 },
0288     { 0x3801, 0x04 },
0289     { 0x3802, 0x00 },
0290     { 0x3803, 0x04 },
0291     { 0x3804, 0x02 },
0292     { 0x3805, 0x8b },
0293     { 0x3806, 0x01 },
0294     { 0x3807, 0xeb },
0295     { 0x3808, 0x02 }, /* width high */
0296     { 0x3809, 0x80 }, /* width low */
0297     { 0x380a, 0x01 }, /* height high */
0298     { 0x380b, 0xe0 }, /* height low */
0299     { 0x380c, 0x03 }, /* total horiz timing high */
0300     { 0x380d, 0xa0 }, /* total horiz timing low */
0301     { 0x380e, 0x06 }, /* total vertical timing high */
0302     { 0x380f, 0xbc }, /* total vertical timing low */
0303     { 0x3810, 0x00 },
0304     { 0x3811, 0x04 },
0305     { 0x3812, 0x00 },
0306     { 0x3813, 0x05 },
0307     { 0x3814, 0x11 },
0308     { 0x3815, 0x11 },
0309     { 0x3820, 0x40 },
0310     { 0x3821, 0x00 },
0311     { 0x382f, 0x0e },
0312     { 0x3832, 0x00 },
0313     { 0x3833, 0x05 },
0314     { 0x3834, 0x00 },
0315     { 0x3835, 0x0c },
0316     { 0x3837, 0x00 },
0317     { 0x3b80, 0x00 },
0318     { 0x3b81, 0xa5 },
0319     { 0x3b82, 0x10 },
0320     { 0x3b83, 0x00 },
0321     { 0x3b84, 0x08 },
0322     { 0x3b85, 0x00 },
0323     { 0x3b86, 0x01 },
0324     { 0x3b87, 0x00 },
0325     { 0x3b88, 0x00 },
0326     { 0x3b89, 0x00 },
0327     { 0x3b8a, 0x00 },
0328     { 0x3b8b, 0x05 },
0329     { 0x3b8c, 0x00 },
0330     { 0x3b8d, 0x00 },
0331     { 0x3b8e, 0x00 },
0332     { 0x3b8f, 0x1a },
0333     { 0x3b94, 0x05 },
0334     { 0x3b95, 0xf2 },
0335     { 0x3b96, 0x40 },
0336     { 0x3c00, 0x89 },
0337     { 0x3c01, 0x63 },
0338     { 0x3c02, 0x01 },
0339     { 0x3c03, 0x00 },
0340     { 0x3c04, 0x00 },
0341     { 0x3c05, 0x03 },
0342     { 0x3c06, 0x00 },
0343     { 0x3c07, 0x06 },
0344     { 0x3c0c, 0x01 },
0345     { 0x3c0d, 0xd0 },
0346     { 0x3c0e, 0x02 },
0347     { 0x3c0f, 0x0a },
0348     { 0x4001, 0x42 },
0349     { 0x4004, 0x04 },
0350     { 0x4005, 0x00 },
0351     { 0x404e, 0x01 },
0352     { 0x4300, 0xff },
0353     { 0x4301, 0x00 },
0354     { 0x4315, 0x00 },
0355     { 0x4501, 0x48 },
0356     { 0x4600, 0x00 },
0357     { 0x4601, 0x4e },
0358     { 0x4801, 0x0f },
0359     { 0x4806, 0x0f },
0360     { 0x4819, 0xaa },
0361     { 0x4823, 0x3e },
0362     { 0x4837, 0x19 },
0363     { 0x4a0d, 0x00 },
0364     { 0x4a47, 0x7f },
0365     { 0x4a49, 0xf0 },
0366     { 0x4a4b, 0x30 },
0367     { 0x5000, 0x85 },
0368     { 0x5001, 0x80 },
0369 };
0370 
0371 static const struct reg_value ov7251_setting_vga_60fps[] = {
0372     { 0x3005, 0x00 },
0373     { 0x3012, 0xc0 },
0374     { 0x3013, 0xd2 },
0375     { 0x3014, 0x04 },
0376     { 0x3016, 0x10 },
0377     { 0x3017, 0x00 },
0378     { 0x3018, 0x00 },
0379     { 0x301a, 0x00 },
0380     { 0x301b, 0x00 },
0381     { 0x301c, 0x00 },
0382     { 0x3023, 0x05 },
0383     { 0x3037, 0xf0 },
0384     { 0x3106, 0xda },
0385     { 0x3503, 0x07 },
0386     { 0x3509, 0x10 },
0387     { 0x3600, 0x1c },
0388     { 0x3602, 0x62 },
0389     { 0x3620, 0xb7 },
0390     { 0x3622, 0x04 },
0391     { 0x3626, 0x21 },
0392     { 0x3627, 0x30 },
0393     { 0x3630, 0x44 },
0394     { 0x3631, 0x35 },
0395     { 0x3634, 0x60 },
0396     { 0x3636, 0x00 },
0397     { 0x3662, 0x01 },
0398     { 0x3663, 0x70 },
0399     { 0x3664, 0x50 },
0400     { 0x3666, 0x0a },
0401     { 0x3669, 0x1a },
0402     { 0x366a, 0x00 },
0403     { 0x366b, 0x50 },
0404     { 0x3673, 0x01 },
0405     { 0x3674, 0xff },
0406     { 0x3675, 0x03 },
0407     { 0x3705, 0xc1 },
0408     { 0x3709, 0x40 },
0409     { 0x373c, 0x08 },
0410     { 0x3742, 0x00 },
0411     { 0x3757, 0xb3 },
0412     { 0x3788, 0x00 },
0413     { 0x37a8, 0x01 },
0414     { 0x37a9, 0xc0 },
0415     { 0x3800, 0x00 },
0416     { 0x3801, 0x04 },
0417     { 0x3802, 0x00 },
0418     { 0x3803, 0x04 },
0419     { 0x3804, 0x02 },
0420     { 0x3805, 0x8b },
0421     { 0x3806, 0x01 },
0422     { 0x3807, 0xeb },
0423     { 0x3808, 0x02 }, /* width high */
0424     { 0x3809, 0x80 }, /* width low */
0425     { 0x380a, 0x01 }, /* height high */
0426     { 0x380b, 0xe0 }, /* height low */
0427     { 0x380c, 0x03 }, /* total horiz timing high */
0428     { 0x380d, 0xa0 }, /* total horiz timing low */
0429     { 0x380e, 0x03 }, /* total vertical timing high */
0430     { 0x380f, 0x5c }, /* total vertical timing low */
0431     { 0x3810, 0x00 },
0432     { 0x3811, 0x04 },
0433     { 0x3812, 0x00 },
0434     { 0x3813, 0x05 },
0435     { 0x3814, 0x11 },
0436     { 0x3815, 0x11 },
0437     { 0x3820, 0x40 },
0438     { 0x3821, 0x00 },
0439     { 0x382f, 0x0e },
0440     { 0x3832, 0x00 },
0441     { 0x3833, 0x05 },
0442     { 0x3834, 0x00 },
0443     { 0x3835, 0x0c },
0444     { 0x3837, 0x00 },
0445     { 0x3b80, 0x00 },
0446     { 0x3b81, 0xa5 },
0447     { 0x3b82, 0x10 },
0448     { 0x3b83, 0x00 },
0449     { 0x3b84, 0x08 },
0450     { 0x3b85, 0x00 },
0451     { 0x3b86, 0x01 },
0452     { 0x3b87, 0x00 },
0453     { 0x3b88, 0x00 },
0454     { 0x3b89, 0x00 },
0455     { 0x3b8a, 0x00 },
0456     { 0x3b8b, 0x05 },
0457     { 0x3b8c, 0x00 },
0458     { 0x3b8d, 0x00 },
0459     { 0x3b8e, 0x00 },
0460     { 0x3b8f, 0x1a },
0461     { 0x3b94, 0x05 },
0462     { 0x3b95, 0xf2 },
0463     { 0x3b96, 0x40 },
0464     { 0x3c00, 0x89 },
0465     { 0x3c01, 0x63 },
0466     { 0x3c02, 0x01 },
0467     { 0x3c03, 0x00 },
0468     { 0x3c04, 0x00 },
0469     { 0x3c05, 0x03 },
0470     { 0x3c06, 0x00 },
0471     { 0x3c07, 0x06 },
0472     { 0x3c0c, 0x01 },
0473     { 0x3c0d, 0xd0 },
0474     { 0x3c0e, 0x02 },
0475     { 0x3c0f, 0x0a },
0476     { 0x4001, 0x42 },
0477     { 0x4004, 0x04 },
0478     { 0x4005, 0x00 },
0479     { 0x404e, 0x01 },
0480     { 0x4300, 0xff },
0481     { 0x4301, 0x00 },
0482     { 0x4315, 0x00 },
0483     { 0x4501, 0x48 },
0484     { 0x4600, 0x00 },
0485     { 0x4601, 0x4e },
0486     { 0x4801, 0x0f },
0487     { 0x4806, 0x0f },
0488     { 0x4819, 0xaa },
0489     { 0x4823, 0x3e },
0490     { 0x4837, 0x19 },
0491     { 0x4a0d, 0x00 },
0492     { 0x4a47, 0x7f },
0493     { 0x4a49, 0xf0 },
0494     { 0x4a4b, 0x30 },
0495     { 0x5000, 0x85 },
0496     { 0x5001, 0x80 },
0497 };
0498 
0499 static const struct reg_value ov7251_setting_vga_90fps[] = {
0500     { 0x3005, 0x00 },
0501     { 0x3012, 0xc0 },
0502     { 0x3013, 0xd2 },
0503     { 0x3014, 0x04 },
0504     { 0x3016, 0x10 },
0505     { 0x3017, 0x00 },
0506     { 0x3018, 0x00 },
0507     { 0x301a, 0x00 },
0508     { 0x301b, 0x00 },
0509     { 0x301c, 0x00 },
0510     { 0x3023, 0x05 },
0511     { 0x3037, 0xf0 },
0512     { 0x3106, 0xda },
0513     { 0x3503, 0x07 },
0514     { 0x3509, 0x10 },
0515     { 0x3600, 0x1c },
0516     { 0x3602, 0x62 },
0517     { 0x3620, 0xb7 },
0518     { 0x3622, 0x04 },
0519     { 0x3626, 0x21 },
0520     { 0x3627, 0x30 },
0521     { 0x3630, 0x44 },
0522     { 0x3631, 0x35 },
0523     { 0x3634, 0x60 },
0524     { 0x3636, 0x00 },
0525     { 0x3662, 0x01 },
0526     { 0x3663, 0x70 },
0527     { 0x3664, 0x50 },
0528     { 0x3666, 0x0a },
0529     { 0x3669, 0x1a },
0530     { 0x366a, 0x00 },
0531     { 0x366b, 0x50 },
0532     { 0x3673, 0x01 },
0533     { 0x3674, 0xff },
0534     { 0x3675, 0x03 },
0535     { 0x3705, 0xc1 },
0536     { 0x3709, 0x40 },
0537     { 0x373c, 0x08 },
0538     { 0x3742, 0x00 },
0539     { 0x3757, 0xb3 },
0540     { 0x3788, 0x00 },
0541     { 0x37a8, 0x01 },
0542     { 0x37a9, 0xc0 },
0543     { 0x3800, 0x00 },
0544     { 0x3801, 0x04 },
0545     { 0x3802, 0x00 },
0546     { 0x3803, 0x04 },
0547     { 0x3804, 0x02 },
0548     { 0x3805, 0x8b },
0549     { 0x3806, 0x01 },
0550     { 0x3807, 0xeb },
0551     { 0x3808, 0x02 }, /* width high */
0552     { 0x3809, 0x80 }, /* width low */
0553     { 0x380a, 0x01 }, /* height high */
0554     { 0x380b, 0xe0 }, /* height low */
0555     { 0x380c, 0x03 }, /* total horiz timing high */
0556     { 0x380d, 0xa0 }, /* total horiz timing low */
0557     { 0x380e, 0x02 }, /* total vertical timing high */
0558     { 0x380f, 0x3c }, /* total vertical timing low */
0559     { 0x3810, 0x00 },
0560     { 0x3811, 0x04 },
0561     { 0x3812, 0x00 },
0562     { 0x3813, 0x05 },
0563     { 0x3814, 0x11 },
0564     { 0x3815, 0x11 },
0565     { 0x3820, 0x40 },
0566     { 0x3821, 0x00 },
0567     { 0x382f, 0x0e },
0568     { 0x3832, 0x00 },
0569     { 0x3833, 0x05 },
0570     { 0x3834, 0x00 },
0571     { 0x3835, 0x0c },
0572     { 0x3837, 0x00 },
0573     { 0x3b80, 0x00 },
0574     { 0x3b81, 0xa5 },
0575     { 0x3b82, 0x10 },
0576     { 0x3b83, 0x00 },
0577     { 0x3b84, 0x08 },
0578     { 0x3b85, 0x00 },
0579     { 0x3b86, 0x01 },
0580     { 0x3b87, 0x00 },
0581     { 0x3b88, 0x00 },
0582     { 0x3b89, 0x00 },
0583     { 0x3b8a, 0x00 },
0584     { 0x3b8b, 0x05 },
0585     { 0x3b8c, 0x00 },
0586     { 0x3b8d, 0x00 },
0587     { 0x3b8e, 0x00 },
0588     { 0x3b8f, 0x1a },
0589     { 0x3b94, 0x05 },
0590     { 0x3b95, 0xf2 },
0591     { 0x3b96, 0x40 },
0592     { 0x3c00, 0x89 },
0593     { 0x3c01, 0x63 },
0594     { 0x3c02, 0x01 },
0595     { 0x3c03, 0x00 },
0596     { 0x3c04, 0x00 },
0597     { 0x3c05, 0x03 },
0598     { 0x3c06, 0x00 },
0599     { 0x3c07, 0x06 },
0600     { 0x3c0c, 0x01 },
0601     { 0x3c0d, 0xd0 },
0602     { 0x3c0e, 0x02 },
0603     { 0x3c0f, 0x0a },
0604     { 0x4001, 0x42 },
0605     { 0x4004, 0x04 },
0606     { 0x4005, 0x00 },
0607     { 0x404e, 0x01 },
0608     { 0x4300, 0xff },
0609     { 0x4301, 0x00 },
0610     { 0x4315, 0x00 },
0611     { 0x4501, 0x48 },
0612     { 0x4600, 0x00 },
0613     { 0x4601, 0x4e },
0614     { 0x4801, 0x0f },
0615     { 0x4806, 0x0f },
0616     { 0x4819, 0xaa },
0617     { 0x4823, 0x3e },
0618     { 0x4837, 0x19 },
0619     { 0x4a0d, 0x00 },
0620     { 0x4a47, 0x7f },
0621     { 0x4a49, 0xf0 },
0622     { 0x4a4b, 0x30 },
0623     { 0x5000, 0x85 },
0624     { 0x5001, 0x80 },
0625 };
0626 
0627 static const unsigned long supported_xclk_rates[] = {
0628     [OV7251_19_2_MHZ] = 19200000,
0629     [OV7251_24_MHZ] = 24000000,
0630 };
0631 
0632 static const s64 link_freq[] = {
0633     [OV7251_LINK_FREQ_240_MHZ] = 240000000,
0634     [OV7251_LINK_FREQ_319_2_MHZ] = 319200000,
0635 };
0636 
0637 static const s64 pixel_rates[] = {
0638     [OV7251_LINK_FREQ_240_MHZ] = 48000000,
0639     [OV7251_LINK_FREQ_319_2_MHZ] = 63840000,
0640 };
0641 
0642 static const struct ov7251_mode_info ov7251_mode_info_data[] = {
0643     {
0644         .width = 640,
0645         .height = 480,
0646         .vts = 1724,
0647         .data = ov7251_setting_vga_30fps,
0648         .data_size = ARRAY_SIZE(ov7251_setting_vga_30fps),
0649         .exposure_max = 1704,
0650         .exposure_def = 504,
0651         .timeperframe = {
0652             .numerator = 100,
0653             .denominator = 3000
0654         }
0655     },
0656     {
0657         .width = 640,
0658         .height = 480,
0659         .vts = 860,
0660         .data = ov7251_setting_vga_60fps,
0661         .data_size = ARRAY_SIZE(ov7251_setting_vga_60fps),
0662         .exposure_max = 840,
0663         .exposure_def = 504,
0664         .timeperframe = {
0665             .numerator = 100,
0666             .denominator = 6014
0667         }
0668     },
0669     {
0670         .width = 640,
0671         .height = 480,
0672         .vts = 572,
0673         .data = ov7251_setting_vga_90fps,
0674         .data_size = ARRAY_SIZE(ov7251_setting_vga_90fps),
0675         .exposure_max = 552,
0676         .exposure_def = 504,
0677         .timeperframe = {
0678             .numerator = 100,
0679             .denominator = 9043
0680         }
0681     },
0682 };
0683 
0684 static int ov7251_regulators_enable(struct ov7251 *ov7251)
0685 {
0686     int ret;
0687 
0688     /* OV7251 power up sequence requires core regulator
0689      * to be enabled not earlier than io regulator
0690      */
0691 
0692     ret = regulator_enable(ov7251->io_regulator);
0693     if (ret < 0) {
0694         dev_err(ov7251->dev, "set io voltage failed\n");
0695         return ret;
0696     }
0697 
0698     ret = regulator_enable(ov7251->analog_regulator);
0699     if (ret) {
0700         dev_err(ov7251->dev, "set analog voltage failed\n");
0701         goto err_disable_io;
0702     }
0703 
0704     ret = regulator_enable(ov7251->core_regulator);
0705     if (ret) {
0706         dev_err(ov7251->dev, "set core voltage failed\n");
0707         goto err_disable_analog;
0708     }
0709 
0710     return 0;
0711 
0712 err_disable_analog:
0713     regulator_disable(ov7251->analog_regulator);
0714 
0715 err_disable_io:
0716     regulator_disable(ov7251->io_regulator);
0717 
0718     return ret;
0719 }
0720 
0721 static void ov7251_regulators_disable(struct ov7251 *ov7251)
0722 {
0723     int ret;
0724 
0725     ret = regulator_disable(ov7251->core_regulator);
0726     if (ret < 0)
0727         dev_err(ov7251->dev, "core regulator disable failed\n");
0728 
0729     ret = regulator_disable(ov7251->analog_regulator);
0730     if (ret < 0)
0731         dev_err(ov7251->dev, "analog regulator disable failed\n");
0732 
0733     ret = regulator_disable(ov7251->io_regulator);
0734     if (ret < 0)
0735         dev_err(ov7251->dev, "io regulator disable failed\n");
0736 }
0737 
0738 static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val)
0739 {
0740     u8 regbuf[3];
0741     int ret;
0742 
0743     regbuf[0] = reg >> 8;
0744     regbuf[1] = reg & 0xff;
0745     regbuf[2] = val;
0746 
0747     ret = i2c_master_send(ov7251->i2c_client, regbuf, 3);
0748     if (ret < 0) {
0749         dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n",
0750             __func__, ret, reg, val);
0751         return ret;
0752     }
0753 
0754     return 0;
0755 }
0756 
0757 static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val,
0758                  u8 num)
0759 {
0760     u8 regbuf[5];
0761     u8 nregbuf = sizeof(reg) + num * sizeof(*val);
0762     int ret = 0;
0763 
0764     if (nregbuf > sizeof(regbuf))
0765         return -EINVAL;
0766 
0767     regbuf[0] = reg >> 8;
0768     regbuf[1] = reg & 0xff;
0769 
0770     memcpy(regbuf + 2, val, num);
0771 
0772     ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf);
0773     if (ret < 0) {
0774         dev_err(ov7251->dev,
0775             "%s: write seq regs error %d: first reg=%x\n",
0776             __func__, ret, reg);
0777         return ret;
0778     }
0779 
0780     return 0;
0781 }
0782 
0783 static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val)
0784 {
0785     u8 regbuf[2];
0786     int ret;
0787 
0788     regbuf[0] = reg >> 8;
0789     regbuf[1] = reg & 0xff;
0790 
0791     ret = i2c_master_send(ov7251->i2c_client, regbuf, 2);
0792     if (ret < 0) {
0793         dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n",
0794             __func__, ret, reg);
0795         return ret;
0796     }
0797 
0798     ret = i2c_master_recv(ov7251->i2c_client, val, 1);
0799     if (ret < 0) {
0800         dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n",
0801             __func__, ret, reg);
0802         return ret;
0803     }
0804 
0805     return 0;
0806 }
0807 
0808 static int ov7251_pll_configure(struct ov7251 *ov7251)
0809 {
0810     const struct ov7251_pll_cfgs *configs;
0811     int ret;
0812 
0813     configs = ov7251->pll_cfgs;
0814 
0815     ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG,
0816                    configs->pll1[ov7251->link_freq_idx]->pre_div);
0817     if (ret < 0)
0818         return ret;
0819 
0820     ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG,
0821                    configs->pll1[ov7251->link_freq_idx]->mult);
0822     if (ret < 0)
0823         return ret;
0824     ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG,
0825                    configs->pll1[ov7251->link_freq_idx]->div);
0826     if (ret < 0)
0827         return ret;
0828 
0829     ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG,
0830                    configs->pll1[ov7251->link_freq_idx]->pix_div);
0831     if (ret < 0)
0832         return ret;
0833 
0834     ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG,
0835                    configs->pll1[ov7251->link_freq_idx]->mipi_div);
0836     if (ret < 0)
0837         return ret;
0838 
0839     ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG,
0840                    configs->pll2->pre_div);
0841     if (ret < 0)
0842         return ret;
0843 
0844     ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG,
0845                    configs->pll2->mult);
0846     if (ret < 0)
0847         return ret;
0848 
0849     ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG,
0850                    configs->pll2->div);
0851     if (ret < 0)
0852         return ret;
0853 
0854     ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG,
0855                    configs->pll2->sys_div);
0856     if (ret < 0)
0857         return ret;
0858 
0859     ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG,
0860                    configs->pll2->adc_div);
0861 
0862     return ret;
0863 }
0864 
0865 static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
0866 {
0867     u16 reg;
0868     u8 val[3];
0869 
0870     reg = OV7251_AEC_EXPO_0;
0871     val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */
0872     val[1] = (exposure & 0x0ff0) >> 4;  /* goes to OV7251_AEC_EXPO_1 */
0873     val[2] = (exposure & 0x000f) << 4;  /* goes to OV7251_AEC_EXPO_2 */
0874 
0875     return ov7251_write_seq_regs(ov7251, reg, val, 3);
0876 }
0877 
0878 static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain)
0879 {
0880     u16 reg;
0881     u8 val[2];
0882 
0883     reg = OV7251_AEC_AGC_ADJ_0;
0884     val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */
0885     val[1] = gain & 0xff;          /* goes to OV7251_AEC_AGC_ADJ_1 */
0886 
0887     return ov7251_write_seq_regs(ov7251, reg, val, 2);
0888 }
0889 
0890 static int ov7251_set_register_array(struct ov7251 *ov7251,
0891                      const struct reg_value *settings,
0892                      unsigned int num_settings)
0893 {
0894     unsigned int i;
0895     int ret;
0896 
0897     for (i = 0; i < num_settings; ++i, ++settings) {
0898         ret = ov7251_write_reg(ov7251, settings->reg, settings->val);
0899         if (ret < 0)
0900             return ret;
0901     }
0902 
0903     return 0;
0904 }
0905 
0906 static int ov7251_set_power_on(struct device *dev)
0907 {
0908     struct i2c_client *client = container_of(dev, struct i2c_client, dev);
0909     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0910     struct ov7251 *ov7251 = to_ov7251(sd);
0911     int ret;
0912     u32 wait_us;
0913 
0914     ret = ov7251_regulators_enable(ov7251);
0915     if (ret < 0)
0916         return ret;
0917 
0918     ret = clk_prepare_enable(ov7251->xclk);
0919     if (ret < 0) {
0920         dev_err(ov7251->dev, "clk prepare enable failed\n");
0921         ov7251_regulators_disable(ov7251);
0922         return ret;
0923     }
0924 
0925     gpiod_set_value_cansleep(ov7251->enable_gpio, 1);
0926 
0927     /* wait at least 65536 external clock cycles */
0928     wait_us = DIV_ROUND_UP(65536 * 1000,
0929                    DIV_ROUND_UP(ov7251->xclk_freq, 1000));
0930     usleep_range(wait_us, wait_us + 1000);
0931 
0932     ret = ov7251_set_register_array(ov7251,
0933                     ov7251_global_init_setting,
0934                     ARRAY_SIZE(ov7251_global_init_setting));
0935     if (ret < 0) {
0936         dev_err(ov7251->dev, "error during global init\n");
0937         gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
0938         clk_disable_unprepare(ov7251->xclk);
0939         ov7251_regulators_disable(ov7251);
0940         return ret;
0941     }
0942 
0943     return ret;
0944 }
0945 
0946 static int ov7251_set_power_off(struct device *dev)
0947 {
0948     struct i2c_client *client = container_of(dev, struct i2c_client, dev);
0949     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0950     struct ov7251 *ov7251 = to_ov7251(sd);
0951 
0952     clk_disable_unprepare(ov7251->xclk);
0953     gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
0954     ov7251_regulators_disable(ov7251);
0955 
0956     return 0;
0957 }
0958 
0959 static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value)
0960 {
0961     u8 val = ov7251->timing_format2;
0962     int ret;
0963 
0964     if (value)
0965         val |= OV7251_TIMING_FORMAT2_MIRROR;
0966     else
0967         val &= ~OV7251_TIMING_FORMAT2_MIRROR;
0968 
0969     ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val);
0970     if (!ret)
0971         ov7251->timing_format2 = val;
0972 
0973     return ret;
0974 }
0975 
0976 static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value)
0977 {
0978     u8 val = ov7251->timing_format1;
0979     int ret;
0980 
0981     if (value)
0982         val |= OV7251_TIMING_FORMAT1_VFLIP;
0983     else
0984         val &= ~OV7251_TIMING_FORMAT1_VFLIP;
0985 
0986     ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val);
0987     if (!ret)
0988         ov7251->timing_format1 = val;
0989 
0990     return ret;
0991 }
0992 
0993 static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value)
0994 {
0995     u8 val = ov7251->pre_isp_00;
0996     int ret;
0997 
0998     if (value)
0999         val |= OV7251_PRE_ISP_00_TEST_PATTERN;
1000     else
1001         val &= ~OV7251_PRE_ISP_00_TEST_PATTERN;
1002 
1003     ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val);
1004     if (!ret)
1005         ov7251->pre_isp_00 = val;
1006 
1007     return ret;
1008 }
1009 
1010 static const char * const ov7251_test_pattern_menu[] = {
1011     "Disabled",
1012     "Vertical Pattern Bars",
1013 };
1014 
1015 static int ov7251_vts_configure(struct ov7251 *ov7251, s32 vblank)
1016 {
1017     u8 vts[2];
1018 
1019     vts[0] = ((ov7251->current_mode->height + vblank) & 0xff00) >> 8;
1020     vts[1] = ((ov7251->current_mode->height + vblank) & 0x00ff);
1021 
1022     return ov7251_write_seq_regs(ov7251, OV7251_TIMING_VTS_REG, vts, 2);
1023 }
1024 
1025 static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
1026 {
1027     struct ov7251 *ov7251 = container_of(ctrl->handler,
1028                          struct ov7251, ctrls);
1029     int ret;
1030 
1031     /* If VBLANK is altered we need to update exposure to compensate */
1032     if (ctrl->id == V4L2_CID_VBLANK) {
1033         int exposure_max;
1034 
1035         exposure_max = ov7251->current_mode->height + ctrl->val -
1036                    OV7251_INTEGRATION_MARGIN;
1037         __v4l2_ctrl_modify_range(ov7251->exposure,
1038                      ov7251->exposure->minimum,
1039                      exposure_max,
1040                      ov7251->exposure->step,
1041                      min(ov7251->exposure->val,
1042                          exposure_max));
1043     }
1044 
1045     /* v4l2_ctrl_lock() locks our mutex */
1046 
1047     if (!pm_runtime_get_if_in_use(ov7251->dev))
1048         return 0;
1049 
1050     switch (ctrl->id) {
1051     case V4L2_CID_EXPOSURE:
1052         ret = ov7251_set_exposure(ov7251, ctrl->val);
1053         break;
1054     case V4L2_CID_GAIN:
1055         ret = ov7251_set_gain(ov7251, ctrl->val);
1056         break;
1057     case V4L2_CID_TEST_PATTERN:
1058         ret = ov7251_set_test_pattern(ov7251, ctrl->val);
1059         break;
1060     case V4L2_CID_HFLIP:
1061         ret = ov7251_set_hflip(ov7251, ctrl->val);
1062         break;
1063     case V4L2_CID_VFLIP:
1064         ret = ov7251_set_vflip(ov7251, ctrl->val);
1065         break;
1066     case V4L2_CID_VBLANK:
1067         ret = ov7251_vts_configure(ov7251, ctrl->val);
1068         break;
1069     default:
1070         ret = -EINVAL;
1071         break;
1072     }
1073 
1074     pm_runtime_put(ov7251->dev);
1075 
1076     return ret;
1077 }
1078 
1079 static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
1080     .s_ctrl = ov7251_s_ctrl,
1081 };
1082 
1083 static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
1084                  struct v4l2_subdev_state *sd_state,
1085                  struct v4l2_subdev_mbus_code_enum *code)
1086 {
1087     if (code->index > 0)
1088         return -EINVAL;
1089 
1090     code->code = MEDIA_BUS_FMT_Y10_1X10;
1091 
1092     return 0;
1093 }
1094 
1095 static int ov7251_enum_frame_size(struct v4l2_subdev *subdev,
1096                   struct v4l2_subdev_state *sd_state,
1097                   struct v4l2_subdev_frame_size_enum *fse)
1098 {
1099     if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
1100         return -EINVAL;
1101 
1102     if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data))
1103         return -EINVAL;
1104 
1105     fse->min_width = ov7251_mode_info_data[fse->index].width;
1106     fse->max_width = ov7251_mode_info_data[fse->index].width;
1107     fse->min_height = ov7251_mode_info_data[fse->index].height;
1108     fse->max_height = ov7251_mode_info_data[fse->index].height;
1109 
1110     return 0;
1111 }
1112 
1113 static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev,
1114                   struct v4l2_subdev_state *sd_state,
1115                   struct v4l2_subdev_frame_interval_enum *fie)
1116 {
1117     unsigned int index = fie->index;
1118     unsigned int i;
1119 
1120     for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1121         if (fie->width != ov7251_mode_info_data[i].width ||
1122             fie->height != ov7251_mode_info_data[i].height)
1123             continue;
1124 
1125         if (index-- == 0) {
1126             fie->interval = ov7251_mode_info_data[i].timeperframe;
1127             return 0;
1128         }
1129     }
1130 
1131     return -EINVAL;
1132 }
1133 
1134 static struct v4l2_mbus_framefmt *
1135 __ov7251_get_pad_format(struct ov7251 *ov7251,
1136             struct v4l2_subdev_state *sd_state,
1137             unsigned int pad,
1138             enum v4l2_subdev_format_whence which)
1139 {
1140     switch (which) {
1141     case V4L2_SUBDEV_FORMAT_TRY:
1142         return v4l2_subdev_get_try_format(&ov7251->sd, sd_state, pad);
1143     case V4L2_SUBDEV_FORMAT_ACTIVE:
1144         return &ov7251->fmt;
1145     default:
1146         return NULL;
1147     }
1148 }
1149 
1150 static int ov7251_get_format(struct v4l2_subdev *sd,
1151                  struct v4l2_subdev_state *sd_state,
1152                  struct v4l2_subdev_format *format)
1153 {
1154     struct ov7251 *ov7251 = to_ov7251(sd);
1155 
1156     mutex_lock(&ov7251->lock);
1157     format->format = *__ov7251_get_pad_format(ov7251, sd_state,
1158                           format->pad,
1159                           format->which);
1160     mutex_unlock(&ov7251->lock);
1161 
1162     return 0;
1163 }
1164 
1165 static struct v4l2_rect *
1166 __ov7251_get_pad_crop(struct ov7251 *ov7251,
1167               struct v4l2_subdev_state *sd_state,
1168               unsigned int pad, enum v4l2_subdev_format_whence which)
1169 {
1170     switch (which) {
1171     case V4L2_SUBDEV_FORMAT_TRY:
1172         return v4l2_subdev_get_try_crop(&ov7251->sd, sd_state, pad);
1173     case V4L2_SUBDEV_FORMAT_ACTIVE:
1174         return &ov7251->crop;
1175     default:
1176         return NULL;
1177     }
1178 }
1179 
1180 static inline u32 avg_fps(const struct v4l2_fract *t)
1181 {
1182     return (t->denominator + (t->numerator >> 1)) / t->numerator;
1183 }
1184 
1185 static const struct ov7251_mode_info *
1186 ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe)
1187 {
1188     const struct ov7251_mode_info *mode = ov7251->current_mode;
1189     unsigned int fps_req = avg_fps(timeperframe);
1190     unsigned int max_dist_match = (unsigned int) -1;
1191     unsigned int i, n = 0;
1192 
1193     for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1194         unsigned int dist;
1195         unsigned int fps_tmp;
1196 
1197         if (mode->width != ov7251_mode_info_data[i].width ||
1198             mode->height != ov7251_mode_info_data[i].height)
1199             continue;
1200 
1201         fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe);
1202 
1203         dist = abs(fps_req - fps_tmp);
1204 
1205         if (dist < max_dist_match) {
1206             n = i;
1207             max_dist_match = dist;
1208         }
1209     }
1210 
1211     return &ov7251_mode_info_data[n];
1212 }
1213 
1214 static int ov7251_set_format(struct v4l2_subdev *sd,
1215                  struct v4l2_subdev_state *sd_state,
1216                  struct v4l2_subdev_format *format)
1217 {
1218     struct ov7251 *ov7251 = to_ov7251(sd);
1219     struct v4l2_mbus_framefmt *__format;
1220     int vblank_max, vblank_def;
1221     struct v4l2_rect *__crop;
1222     const struct ov7251_mode_info *new_mode;
1223     int ret = 0;
1224 
1225     mutex_lock(&ov7251->lock);
1226 
1227     __crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad,
1228                        format->which);
1229 
1230     new_mode = v4l2_find_nearest_size(ov7251_mode_info_data,
1231                 ARRAY_SIZE(ov7251_mode_info_data),
1232                 width, height,
1233                 format->format.width, format->format.height);
1234 
1235     __crop->width = new_mode->width;
1236     __crop->height = new_mode->height;
1237 
1238     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1239         ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1240                            1, new_mode->exposure_max,
1241                            1, new_mode->exposure_def);
1242         if (ret < 0)
1243             goto exit;
1244 
1245         ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1246                      new_mode->exposure_def);
1247         if (ret < 0)
1248             goto exit;
1249 
1250         ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1251         if (ret < 0)
1252             goto exit;
1253 
1254         vblank_max = OV7251_TIMING_MAX_VTS - new_mode->height;
1255         vblank_def = new_mode->vts - new_mode->height;
1256         ret = __v4l2_ctrl_modify_range(ov7251->vblank,
1257                            OV7251_TIMING_MIN_VTS,
1258                            vblank_max, 1, vblank_def);
1259         if (ret < 0)
1260             goto exit;
1261 
1262         ov7251->current_mode = new_mode;
1263     }
1264 
1265     __format = __ov7251_get_pad_format(ov7251, sd_state, format->pad,
1266                        format->which);
1267     __format->width = __crop->width;
1268     __format->height = __crop->height;
1269     __format->code = MEDIA_BUS_FMT_Y10_1X10;
1270     __format->field = V4L2_FIELD_NONE;
1271     __format->colorspace = V4L2_COLORSPACE_SRGB;
1272     __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
1273     __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
1274                 __format->colorspace, __format->ycbcr_enc);
1275     __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
1276 
1277     format->format = *__format;
1278 
1279 exit:
1280     mutex_unlock(&ov7251->lock);
1281 
1282     return ret;
1283 }
1284 
1285 static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev,
1286                   struct v4l2_subdev_state *sd_state)
1287 {
1288     struct v4l2_subdev_format fmt = {
1289         .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
1290         : V4L2_SUBDEV_FORMAT_ACTIVE,
1291         .format = {
1292             .width = 640,
1293             .height = 480
1294         }
1295     };
1296 
1297     ov7251_set_format(subdev, sd_state, &fmt);
1298 
1299     return 0;
1300 }
1301 
1302 static int ov7251_get_selection(struct v4l2_subdev *sd,
1303                 struct v4l2_subdev_state *sd_state,
1304                 struct v4l2_subdev_selection *sel)
1305 {
1306     struct ov7251 *ov7251 = to_ov7251(sd);
1307 
1308     switch (sel->target) {
1309     case V4L2_SEL_TGT_CROP_DEFAULT:
1310     case V4L2_SEL_TGT_CROP:
1311     mutex_lock(&ov7251->lock);
1312         sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad,
1313                         sel->which);
1314         mutex_unlock(&ov7251->lock);
1315         break;
1316     case V4L2_SEL_TGT_NATIVE_SIZE:
1317         sel->r.top = 0;
1318         sel->r.left = 0;
1319         sel->r.width = OV7251_NATIVE_WIDTH;
1320         sel->r.height = OV7251_NATIVE_HEIGHT;
1321         break;
1322     case V4L2_SEL_TGT_CROP_BOUNDS:
1323         sel->r.top = OV7251_ACTIVE_START_TOP;
1324         sel->r.left = OV7251_ACTIVE_START_LEFT;
1325         sel->r.width = OV7251_ACTIVE_WIDTH;
1326         sel->r.height = OV7251_ACTIVE_HEIGHT;
1327         break;
1328     default:
1329         return -EINVAL;
1330     }
1331 
1332     return 0;
1333 }
1334 
1335 static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
1336 {
1337     struct ov7251 *ov7251 = to_ov7251(subdev);
1338     int ret;
1339 
1340     mutex_lock(&ov7251->lock);
1341 
1342     if (enable) {
1343         ret = pm_runtime_get_sync(ov7251->dev);
1344         if (ret < 0)
1345             goto err_power_down;
1346 
1347         ret = ov7251_pll_configure(ov7251);
1348         if (ret) {
1349             dev_err(ov7251->dev, "error configuring PLLs\n");
1350             goto err_power_down;
1351         }
1352 
1353         ret = ov7251_set_register_array(ov7251,
1354                     ov7251->current_mode->data,
1355                     ov7251->current_mode->data_size);
1356         if (ret < 0) {
1357             dev_err(ov7251->dev, "could not set mode %dx%d\n",
1358                 ov7251->current_mode->width,
1359                 ov7251->current_mode->height);
1360             goto err_power_down;
1361         }
1362         ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls);
1363         if (ret < 0) {
1364             dev_err(ov7251->dev, "could not sync v4l2 controls\n");
1365             goto err_power_down;
1366         }
1367         ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1368                        OV7251_SC_MODE_SELECT_STREAMING);
1369         if (ret)
1370             goto err_power_down;
1371     } else {
1372         ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1373                        OV7251_SC_MODE_SELECT_SW_STANDBY);
1374         pm_runtime_put(ov7251->dev);
1375     }
1376 
1377     mutex_unlock(&ov7251->lock);
1378     return ret;
1379 
1380 err_power_down:
1381     pm_runtime_put(ov7251->dev);
1382     mutex_unlock(&ov7251->lock);
1383     return ret;
1384 }
1385 
1386 static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,
1387                      struct v4l2_subdev_frame_interval *fi)
1388 {
1389     struct ov7251 *ov7251 = to_ov7251(subdev);
1390 
1391     mutex_lock(&ov7251->lock);
1392     fi->interval = ov7251->current_mode->timeperframe;
1393     mutex_unlock(&ov7251->lock);
1394 
1395     return 0;
1396 }
1397 
1398 static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,
1399                      struct v4l2_subdev_frame_interval *fi)
1400 {
1401     struct ov7251 *ov7251 = to_ov7251(subdev);
1402     const struct ov7251_mode_info *new_mode;
1403     int ret = 0;
1404 
1405     mutex_lock(&ov7251->lock);
1406     new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval);
1407 
1408     if (new_mode != ov7251->current_mode) {
1409         ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1410                            1, new_mode->exposure_max,
1411                            1, new_mode->exposure_def);
1412         if (ret < 0)
1413             goto exit;
1414 
1415         ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1416                      new_mode->exposure_def);
1417         if (ret < 0)
1418             goto exit;
1419 
1420         ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1421         if (ret < 0)
1422             goto exit;
1423 
1424         ov7251->current_mode = new_mode;
1425     }
1426 
1427     fi->interval = ov7251->current_mode->timeperframe;
1428 
1429 exit:
1430     mutex_unlock(&ov7251->lock);
1431 
1432     return ret;
1433 }
1434 
1435 static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1436     .s_stream = ov7251_s_stream,
1437     .g_frame_interval = ov7251_get_frame_interval,
1438     .s_frame_interval = ov7251_set_frame_interval,
1439 };
1440 
1441 static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {
1442     .init_cfg = ov7251_entity_init_cfg,
1443     .enum_mbus_code = ov7251_enum_mbus_code,
1444     .enum_frame_size = ov7251_enum_frame_size,
1445     .enum_frame_interval = ov7251_enum_frame_ival,
1446     .get_fmt = ov7251_get_format,
1447     .set_fmt = ov7251_set_format,
1448     .get_selection = ov7251_get_selection,
1449 };
1450 
1451 static const struct v4l2_subdev_ops ov7251_subdev_ops = {
1452     .video = &ov7251_video_ops,
1453     .pad = &ov7251_subdev_pad_ops,
1454 };
1455 
1456 static int ov7251_check_hwcfg(struct ov7251 *ov7251)
1457 {
1458     struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev);
1459     struct v4l2_fwnode_endpoint bus_cfg = {
1460         .bus_type = V4L2_MBUS_CSI2_DPHY,
1461     };
1462     struct fwnode_handle *endpoint;
1463     unsigned int i, j;
1464     int ret;
1465 
1466     endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL);
1467     if (!endpoint)
1468         return -EPROBE_DEFER; /* could be provided by cio2-bridge */
1469 
1470     ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1471     fwnode_handle_put(endpoint);
1472     if (ret)
1473         return dev_err_probe(ov7251->dev, ret,
1474                      "parsing endpoint node failed\n");
1475 
1476     if (!bus_cfg.nr_of_link_frequencies) {
1477         ret = dev_err_probe(ov7251->dev, -EINVAL,
1478                     "no link frequencies defined\n");
1479         goto out_free_bus_cfg;
1480     }
1481 
1482     for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
1483         for (j = 0; j < ARRAY_SIZE(link_freq); j++)
1484             if (bus_cfg.link_frequencies[i] == link_freq[j])
1485                 break;
1486 
1487         if (j < ARRAY_SIZE(link_freq))
1488             break;
1489     }
1490 
1491     if (i == bus_cfg.nr_of_link_frequencies) {
1492         ret = dev_err_probe(ov7251->dev, -EINVAL,
1493                     "no supported link freq found\n");
1494         goto out_free_bus_cfg;
1495     }
1496 
1497     ov7251->link_freq_idx = i;
1498 
1499 out_free_bus_cfg:
1500     v4l2_fwnode_endpoint_free(&bus_cfg);
1501 
1502     return ret;
1503 }
1504 
1505 static int ov7251_detect_chip(struct ov7251 *ov7251)
1506 {
1507     u8 chip_id_high, chip_id_low, chip_rev;
1508     int ret;
1509 
1510     ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high);
1511     if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE)
1512         return dev_err_probe(ov7251->dev, -ENODEV,
1513                      "could not read ID high\n");
1514 
1515     ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low);
1516     if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE)
1517         return dev_err_probe(ov7251->dev, -ENODEV,
1518                      "could not read ID low\n");
1519 
1520     ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev);
1521     if (ret < 0)
1522         return dev_err_probe(ov7251->dev, -ENODEV,
1523                      "could not read revision\n");
1524     chip_rev >>= 4;
1525 
1526     dev_info(ov7251->dev,
1527          "OV7251 revision %x (%s) detected at address 0x%02x\n",
1528          chip_rev,
1529          chip_rev == 0x4 ? "1A / 1B" :
1530          chip_rev == 0x5 ? "1C / 1D" :
1531          chip_rev == 0x6 ? "1E" :
1532          chip_rev == 0x7 ? "1F" : "unknown",
1533          ov7251->i2c_client->addr);
1534 
1535     return 0;
1536 }
1537 
1538 static int ov7251_init_ctrls(struct ov7251 *ov7251)
1539 {
1540     int vblank_max, vblank_def;
1541     s64 pixel_rate;
1542     int hblank;
1543 
1544     v4l2_ctrl_handler_init(&ov7251->ctrls, 7);
1545     ov7251->ctrls.lock = &ov7251->lock;
1546 
1547     v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1548               V4L2_CID_HFLIP, 0, 1, 1, 0);
1549     v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1550               V4L2_CID_VFLIP, 0, 1, 1, 0);
1551     ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1552                          V4L2_CID_EXPOSURE, 1, 32, 1, 32);
1553     ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1554                      V4L2_CID_GAIN, 16, 1023, 1, 16);
1555     v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops,
1556                      V4L2_CID_TEST_PATTERN,
1557                      ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1558                      0, 0, ov7251_test_pattern_menu);
1559 
1560     pixel_rate = pixel_rates[ov7251->link_freq_idx];
1561     ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls,
1562                         &ov7251_ctrl_ops,
1563                         V4L2_CID_PIXEL_RATE,
1564                         pixel_rate, INT_MAX,
1565                         pixel_rate, pixel_rate);
1566     ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls,
1567                            &ov7251_ctrl_ops,
1568                            V4L2_CID_LINK_FREQ,
1569                            ARRAY_SIZE(link_freq) - 1,
1570                            ov7251->link_freq_idx,
1571                            link_freq);
1572     if (ov7251->link_freq)
1573         ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1574     if (ov7251->pixel_clock)
1575         ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1576 
1577     hblank = OV7251_FIXED_PPL - ov7251->current_mode->width;
1578     ov7251->hblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1579                        V4L2_CID_HBLANK, hblank, hblank, 1,
1580                        hblank);
1581     if (ov7251->hblank)
1582         ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1583 
1584     vblank_max = OV7251_TIMING_MAX_VTS - ov7251->current_mode->height;
1585     vblank_def = ov7251->current_mode->vts - ov7251->current_mode->height;
1586     ov7251->vblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1587                        V4L2_CID_VBLANK,
1588                        OV7251_TIMING_MIN_VTS, vblank_max, 1,
1589                        vblank_def);
1590 
1591     ov7251->sd.ctrl_handler = &ov7251->ctrls;
1592 
1593     if (ov7251->ctrls.error) {
1594         v4l2_ctrl_handler_free(&ov7251->ctrls);
1595         return ov7251->ctrls.error;
1596     }
1597 
1598     return 0;
1599 }
1600 
1601 static int ov7251_probe(struct i2c_client *client)
1602 {
1603     struct device *dev = &client->dev;
1604     struct ov7251 *ov7251;
1605     unsigned int rate = 0, clk_rate = 0;
1606     int ret;
1607     int i;
1608 
1609     ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
1610     if (!ov7251)
1611         return -ENOMEM;
1612 
1613     ov7251->i2c_client = client;
1614     ov7251->dev = dev;
1615 
1616     ret = ov7251_check_hwcfg(ov7251);
1617     if (ret)
1618         return ret;
1619 
1620     /* get system clock (xclk) */
1621     ov7251->xclk = devm_clk_get_optional(dev, NULL);
1622     if (IS_ERR(ov7251->xclk))
1623         return dev_err_probe(dev, PTR_ERR(ov7251->xclk),
1624                      "could not get xclk");
1625 
1626     /*
1627      * We could have either a 24MHz or 19.2MHz clock rate from either DT or
1628      * ACPI. We also need to support the IPU3 case which will have both an
1629      * external clock AND a clock-frequency property.
1630      */
1631     ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1632                        &rate);
1633     if (ret && !ov7251->xclk)
1634         return dev_err_probe(dev, ret, "invalid clock config\n");
1635 
1636     clk_rate = clk_get_rate(ov7251->xclk);
1637     ov7251->xclk_freq = clk_rate ? clk_rate : rate;
1638 
1639     if (ov7251->xclk_freq == 0)
1640         return dev_err_probe(dev, -EINVAL, "invalid clock frequency\n");
1641 
1642     if (!ret && ov7251->xclk) {
1643         ret = clk_set_rate(ov7251->xclk, rate);
1644         if (ret)
1645             return dev_err_probe(dev, ret,
1646                          "failed to set clock rate\n");
1647     }
1648 
1649     for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++)
1650         if (ov7251->xclk_freq == supported_xclk_rates[i])
1651             break;
1652 
1653     if (i == ARRAY_SIZE(supported_xclk_rates))
1654         return dev_err_probe(dev, -EINVAL,
1655                      "clock rate %u Hz is unsupported\n",
1656                      ov7251->xclk_freq);
1657 
1658     ov7251->pll_cfgs = ov7251_pll_cfgs[i];
1659 
1660     ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
1661     if (IS_ERR(ov7251->io_regulator)) {
1662         dev_err(dev, "cannot get io regulator\n");
1663         return PTR_ERR(ov7251->io_regulator);
1664     }
1665 
1666     ov7251->core_regulator = devm_regulator_get(dev, "vddd");
1667     if (IS_ERR(ov7251->core_regulator)) {
1668         dev_err(dev, "cannot get core regulator\n");
1669         return PTR_ERR(ov7251->core_regulator);
1670     }
1671 
1672     ov7251->analog_regulator = devm_regulator_get(dev, "vdda");
1673     if (IS_ERR(ov7251->analog_regulator)) {
1674         dev_err(dev, "cannot get analog regulator\n");
1675         return PTR_ERR(ov7251->analog_regulator);
1676     }
1677 
1678     ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
1679     if (IS_ERR(ov7251->enable_gpio)) {
1680         dev_err(dev, "cannot get enable gpio\n");
1681         return PTR_ERR(ov7251->enable_gpio);
1682     }
1683 
1684     mutex_init(&ov7251->lock);
1685 
1686     ov7251->current_mode = &ov7251_mode_info_data[0];
1687     ret = ov7251_init_ctrls(ov7251);
1688     if (ret) {
1689         dev_err_probe(dev, ret, "error during v4l2 ctrl init\n");
1690         goto destroy_mutex;
1691     }
1692 
1693     v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);
1694     ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1695     ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
1696     ov7251->sd.dev = &client->dev;
1697     ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1698 
1699     ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad);
1700     if (ret < 0) {
1701         dev_err(dev, "could not register media entity\n");
1702         goto free_ctrl;
1703     }
1704 
1705     ret = ov7251_set_power_on(ov7251->dev);
1706     if (ret)
1707         goto free_entity;
1708 
1709     ret = ov7251_detect_chip(ov7251);
1710     if (ret)
1711         goto power_down;
1712 
1713     pm_runtime_set_active(&client->dev);
1714     pm_runtime_get_noresume(&client->dev);
1715     pm_runtime_enable(&client->dev);
1716 
1717     ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00,
1718                   &ov7251->pre_isp_00);
1719     if (ret < 0) {
1720         dev_err(dev, "could not read test pattern value\n");
1721         ret = -ENODEV;
1722         goto err_pm_runtime;
1723     }
1724 
1725     ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1,
1726                   &ov7251->timing_format1);
1727     if (ret < 0) {
1728         dev_err(dev, "could not read vflip value\n");
1729         ret = -ENODEV;
1730         goto err_pm_runtime;
1731     }
1732 
1733     ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2,
1734                   &ov7251->timing_format2);
1735     if (ret < 0) {
1736         dev_err(dev, "could not read hflip value\n");
1737         ret = -ENODEV;
1738         goto err_pm_runtime;
1739     }
1740 
1741     pm_runtime_set_autosuspend_delay(&client->dev, 1000);
1742     pm_runtime_use_autosuspend(&client->dev);
1743     pm_runtime_put_autosuspend(&client->dev);
1744 
1745     ret = v4l2_async_register_subdev(&ov7251->sd);
1746     if (ret < 0) {
1747         dev_err(dev, "could not register v4l2 device\n");
1748         goto free_entity;
1749     }
1750 
1751     ov7251_entity_init_cfg(&ov7251->sd, NULL);
1752 
1753     return 0;
1754 
1755 err_pm_runtime:
1756     pm_runtime_disable(ov7251->dev);
1757     pm_runtime_put_noidle(ov7251->dev);
1758 power_down:
1759     ov7251_set_power_off(ov7251->dev);
1760 free_entity:
1761     media_entity_cleanup(&ov7251->sd.entity);
1762 free_ctrl:
1763     v4l2_ctrl_handler_free(&ov7251->ctrls);
1764 destroy_mutex:
1765     mutex_destroy(&ov7251->lock);
1766 
1767     return ret;
1768 }
1769 
1770 static int ov7251_remove(struct i2c_client *client)
1771 {
1772     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1773     struct ov7251 *ov7251 = to_ov7251(sd);
1774 
1775     v4l2_async_unregister_subdev(&ov7251->sd);
1776     media_entity_cleanup(&ov7251->sd.entity);
1777     v4l2_ctrl_handler_free(&ov7251->ctrls);
1778     mutex_destroy(&ov7251->lock);
1779 
1780     pm_runtime_disable(ov7251->dev);
1781     if (!pm_runtime_status_suspended(ov7251->dev))
1782         ov7251_set_power_off(ov7251->dev);
1783     pm_runtime_set_suspended(ov7251->dev);
1784 
1785     return 0;
1786 }
1787 
1788 static const struct dev_pm_ops ov7251_pm_ops = {
1789     SET_RUNTIME_PM_OPS(ov7251_set_power_off, ov7251_set_power_on, NULL)
1790 };
1791 
1792 static const struct of_device_id ov7251_of_match[] = {
1793     { .compatible = "ovti,ov7251" },
1794     { /* sentinel */ }
1795 };
1796 MODULE_DEVICE_TABLE(of, ov7251_of_match);
1797 
1798 static const struct acpi_device_id ov7251_acpi_match[] = {
1799     { "INT347E" },
1800     { }
1801 };
1802 MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match);
1803 
1804 static struct i2c_driver ov7251_i2c_driver = {
1805     .driver = {
1806         .of_match_table = ov7251_of_match,
1807         .acpi_match_table = ov7251_acpi_match,
1808         .name  = "ov7251",
1809         .pm = &ov7251_pm_ops,
1810     },
1811     .probe_new  = ov7251_probe,
1812     .remove = ov7251_remove,
1813 };
1814 
1815 module_i2c_driver(ov7251_i2c_driver);
1816 
1817 MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver");
1818 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1819 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!