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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
0004  *
0005  * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
0006  *
0007  * Based on OmniVision OV96xx Camera Driver
0008  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
0009  *
0010  * Based on ov772x camera driver:
0011  * Copyright (C) 2008 Renesas Solutions Corp.
0012  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
0013  *
0014  * Based on ov7670 and soc_camera_platform driver,
0015  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
0016  * Copyright (C) 2008 Magnus Damm
0017  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
0018  *
0019  * Hardware specific bits initially based on former work by Matt Callow
0020  * drivers/media/video/omap/sensor_ov6650.c
0021  * Copyright (C) 2006 Matt Callow
0022  */
0023 
0024 #include <linux/bitops.h>
0025 #include <linux/clk.h>
0026 #include <linux/delay.h>
0027 #include <linux/i2c.h>
0028 #include <linux/slab.h>
0029 #include <linux/v4l2-mediabus.h>
0030 #include <linux/module.h>
0031 
0032 #include <media/v4l2-ctrls.h>
0033 #include <media/v4l2-device.h>
0034 
0035 /* Register definitions */
0036 #define REG_GAIN        0x00    /* range 00 - 3F */
0037 #define REG_BLUE        0x01
0038 #define REG_RED         0x02
0039 #define REG_SAT         0x03    /* [7:4] saturation [0:3] reserved */
0040 #define REG_HUE         0x04    /* [7:6] rsrvd [5] hue en [4:0] hue */
0041 
0042 #define REG_BRT         0x06
0043 
0044 #define REG_PIDH        0x0a
0045 #define REG_PIDL        0x0b
0046 
0047 #define REG_AECH        0x10
0048 #define REG_CLKRC       0x11    /* Data Format and Internal Clock */
0049                     /* [7:6] Input system clock (MHz)*/
0050                     /*   00=8, 01=12, 10=16, 11=24 */
0051                     /* [5:0]: Internal Clock Pre-Scaler */
0052 #define REG_COMA        0x12    /* [7] Reset */
0053 #define REG_COMB        0x13
0054 #define REG_COMC        0x14
0055 #define REG_COMD        0x15
0056 #define REG_COML        0x16
0057 #define REG_HSTRT       0x17
0058 #define REG_HSTOP       0x18
0059 #define REG_VSTRT       0x19
0060 #define REG_VSTOP       0x1a
0061 #define REG_PSHFT       0x1b
0062 #define REG_MIDH        0x1c
0063 #define REG_MIDL        0x1d
0064 #define REG_HSYNS       0x1e
0065 #define REG_HSYNE       0x1f
0066 #define REG_COME        0x20
0067 #define REG_YOFF        0x21
0068 #define REG_UOFF        0x22
0069 #define REG_VOFF        0x23
0070 #define REG_AEW         0x24
0071 #define REG_AEB         0x25
0072 #define REG_COMF        0x26
0073 #define REG_COMG        0x27
0074 #define REG_COMH        0x28
0075 #define REG_COMI        0x29
0076 
0077 #define REG_FRARL       0x2b
0078 #define REG_COMJ        0x2c
0079 #define REG_COMK        0x2d
0080 #define REG_AVGY        0x2e
0081 #define REG_REF0        0x2f
0082 #define REG_REF1        0x30
0083 #define REG_REF2        0x31
0084 #define REG_FRAJH       0x32
0085 #define REG_FRAJL       0x33
0086 #define REG_FACT        0x34
0087 #define REG_L1AEC       0x35
0088 #define REG_AVGU        0x36
0089 #define REG_AVGV        0x37
0090 
0091 #define REG_SPCB        0x60
0092 #define REG_SPCC        0x61
0093 #define REG_GAM1        0x62
0094 #define REG_GAM2        0x63
0095 #define REG_GAM3        0x64
0096 #define REG_SPCD        0x65
0097 
0098 #define REG_SPCE        0x68
0099 #define REG_ADCL        0x69
0100 
0101 #define REG_RMCO        0x6c
0102 #define REG_GMCO        0x6d
0103 #define REG_BMCO        0x6e
0104 
0105 
0106 /* Register bits, values, etc. */
0107 #define OV6650_PIDH     0x66    /* high byte of product ID number */
0108 #define OV6650_PIDL     0x50    /* low byte of product ID number */
0109 #define OV6650_MIDH     0x7F    /* high byte of mfg ID */
0110 #define OV6650_MIDL     0xA2    /* low byte of mfg ID */
0111 
0112 #define DEF_GAIN        0x00
0113 #define DEF_BLUE        0x80
0114 #define DEF_RED         0x80
0115 
0116 #define SAT_SHIFT       4
0117 #define SAT_MASK        (0xf << SAT_SHIFT)
0118 #define SET_SAT(x)      (((x) << SAT_SHIFT) & SAT_MASK)
0119 
0120 #define HUE_EN          BIT(5)
0121 #define HUE_MASK        0x1f
0122 #define DEF_HUE         0x10
0123 #define SET_HUE(x)      (HUE_EN | ((x) & HUE_MASK))
0124 
0125 #define DEF_AECH        0x4D
0126 
0127 #define CLKRC_8MHz      0x00
0128 #define CLKRC_12MHz     0x40
0129 #define CLKRC_16MHz     0x80
0130 #define CLKRC_24MHz     0xc0
0131 #define CLKRC_DIV_MASK      0x3f
0132 #define GET_CLKRC_DIV(x)    (((x) & CLKRC_DIV_MASK) + 1)
0133 #define DEF_CLKRC       0x00
0134 
0135 #define COMA_RESET      BIT(7)
0136 #define COMA_QCIF       BIT(5)
0137 #define COMA_RAW_RGB        BIT(4)
0138 #define COMA_RGB        BIT(3)
0139 #define COMA_BW         BIT(2)
0140 #define COMA_WORD_SWAP      BIT(1)
0141 #define COMA_BYTE_SWAP      BIT(0)
0142 #define DEF_COMA        0x00
0143 
0144 #define COMB_FLIP_V     BIT(7)
0145 #define COMB_FLIP_H     BIT(5)
0146 #define COMB_BAND_FILTER    BIT(4)
0147 #define COMB_AWB        BIT(2)
0148 #define COMB_AGC        BIT(1)
0149 #define COMB_AEC        BIT(0)
0150 #define DEF_COMB        0x5f
0151 
0152 #define COML_ONE_CHANNEL    BIT(7)
0153 
0154 #define DEF_HSTRT       0x24
0155 #define DEF_HSTOP       0xd4
0156 #define DEF_VSTRT       0x04
0157 #define DEF_VSTOP       0x94
0158 
0159 #define COMF_HREF_LOW       BIT(4)
0160 
0161 #define COMJ_PCLK_RISING    BIT(4)
0162 #define COMJ_VSYNC_HIGH     BIT(0)
0163 
0164 /* supported resolutions */
0165 #define W_QCIF          (DEF_HSTOP - DEF_HSTRT)
0166 #define W_CIF           (W_QCIF << 1)
0167 #define H_QCIF          (DEF_VSTOP - DEF_VSTRT)
0168 #define H_CIF           (H_QCIF << 1)
0169 
0170 #define FRAME_RATE_MAX      30
0171 
0172 
0173 struct ov6650_reg {
0174     u8  reg;
0175     u8  val;
0176 };
0177 
0178 struct ov6650 {
0179     struct v4l2_subdev  subdev;
0180     struct v4l2_ctrl_handler hdl;
0181     struct {
0182         /* exposure/autoexposure cluster */
0183         struct v4l2_ctrl *autoexposure;
0184         struct v4l2_ctrl *exposure;
0185     };
0186     struct {
0187         /* gain/autogain cluster */
0188         struct v4l2_ctrl *autogain;
0189         struct v4l2_ctrl *gain;
0190     };
0191     struct {
0192         /* blue/red/autowhitebalance cluster */
0193         struct v4l2_ctrl *autowb;
0194         struct v4l2_ctrl *blue;
0195         struct v4l2_ctrl *red;
0196     };
0197     struct clk      *clk;
0198     bool            half_scale; /* scale down output by 2 */
0199     struct v4l2_rect    rect;       /* sensor cropping window */
0200     struct v4l2_fract   tpf;        /* as requested with s_frame_interval */
0201     u32 code;
0202 };
0203 
0204 struct ov6650_xclk {
0205     unsigned long   rate;
0206     u8      clkrc;
0207 };
0208 
0209 static const struct ov6650_xclk ov6650_xclk[] = {
0210 {
0211     .rate   = 8000000,
0212     .clkrc  = CLKRC_8MHz,
0213 },
0214 {
0215     .rate   = 12000000,
0216     .clkrc  = CLKRC_12MHz,
0217 },
0218 {
0219     .rate   = 16000000,
0220     .clkrc  = CLKRC_16MHz,
0221 },
0222 {
0223     .rate   = 24000000,
0224     .clkrc  = CLKRC_24MHz,
0225 },
0226 };
0227 
0228 static u32 ov6650_codes[] = {
0229     MEDIA_BUS_FMT_YUYV8_2X8,
0230     MEDIA_BUS_FMT_UYVY8_2X8,
0231     MEDIA_BUS_FMT_YVYU8_2X8,
0232     MEDIA_BUS_FMT_VYUY8_2X8,
0233     MEDIA_BUS_FMT_SBGGR8_1X8,
0234     MEDIA_BUS_FMT_Y8_1X8,
0235 };
0236 
0237 static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
0238     .width      = W_CIF,
0239     .height     = H_CIF,
0240     .code       = MEDIA_BUS_FMT_SBGGR8_1X8,
0241     .colorspace = V4L2_COLORSPACE_SRGB,
0242     .field      = V4L2_FIELD_NONE,
0243     .ycbcr_enc  = V4L2_YCBCR_ENC_DEFAULT,
0244     .quantization   = V4L2_QUANTIZATION_DEFAULT,
0245     .xfer_func  = V4L2_XFER_FUNC_DEFAULT,
0246 };
0247 
0248 /* read a register */
0249 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
0250 {
0251     int ret;
0252     u8 data = reg;
0253     struct i2c_msg msg = {
0254         .addr   = client->addr,
0255         .flags  = 0,
0256         .len    = 1,
0257         .buf    = &data,
0258     };
0259 
0260     ret = i2c_transfer(client->adapter, &msg, 1);
0261     if (ret < 0)
0262         goto err;
0263 
0264     msg.flags = I2C_M_RD;
0265     ret = i2c_transfer(client->adapter, &msg, 1);
0266     if (ret < 0)
0267         goto err;
0268 
0269     *val = data;
0270     return 0;
0271 
0272 err:
0273     dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
0274     return ret;
0275 }
0276 
0277 /* write a register */
0278 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
0279 {
0280     int ret;
0281     unsigned char data[2] = { reg, val };
0282     struct i2c_msg msg = {
0283         .addr   = client->addr,
0284         .flags  = 0,
0285         .len    = 2,
0286         .buf    = data,
0287     };
0288 
0289     ret = i2c_transfer(client->adapter, &msg, 1);
0290     udelay(100);
0291 
0292     if (ret < 0) {
0293         dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
0294         return ret;
0295     }
0296     return 0;
0297 }
0298 
0299 
0300 /* Read a register, alter its bits, write it back */
0301 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
0302 {
0303     u8 val;
0304     int ret;
0305 
0306     ret = ov6650_reg_read(client, reg, &val);
0307     if (ret) {
0308         dev_err(&client->dev,
0309             "[Read]-Modify-Write of register 0x%02x failed!\n",
0310             reg);
0311         return ret;
0312     }
0313 
0314     val &= ~mask;
0315     val |= set;
0316 
0317     ret = ov6650_reg_write(client, reg, val);
0318     if (ret)
0319         dev_err(&client->dev,
0320             "Read-Modify-[Write] of register 0x%02x failed!\n",
0321             reg);
0322 
0323     return ret;
0324 }
0325 
0326 static struct ov6650 *to_ov6650(const struct i2c_client *client)
0327 {
0328     return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
0329 }
0330 
0331 /* Start/Stop streaming from the device */
0332 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
0333 {
0334     return 0;
0335 }
0336 
0337 /* Get status of additional camera capabilities */
0338 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
0339 {
0340     struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
0341     struct v4l2_subdev *sd = &priv->subdev;
0342     struct i2c_client *client = v4l2_get_subdevdata(sd);
0343     uint8_t reg, reg2;
0344     int ret;
0345 
0346     switch (ctrl->id) {
0347     case V4L2_CID_AUTOGAIN:
0348         ret = ov6650_reg_read(client, REG_GAIN, &reg);
0349         if (!ret)
0350             priv->gain->val = reg;
0351         return ret;
0352     case V4L2_CID_AUTO_WHITE_BALANCE:
0353         ret = ov6650_reg_read(client, REG_BLUE, &reg);
0354         if (!ret)
0355             ret = ov6650_reg_read(client, REG_RED, &reg2);
0356         if (!ret) {
0357             priv->blue->val = reg;
0358             priv->red->val = reg2;
0359         }
0360         return ret;
0361     case V4L2_CID_EXPOSURE_AUTO:
0362         ret = ov6650_reg_read(client, REG_AECH, &reg);
0363         if (!ret)
0364             priv->exposure->val = reg;
0365         return ret;
0366     }
0367     return -EINVAL;
0368 }
0369 
0370 /* Set status of additional camera capabilities */
0371 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
0372 {
0373     struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
0374     struct v4l2_subdev *sd = &priv->subdev;
0375     struct i2c_client *client = v4l2_get_subdevdata(sd);
0376     int ret;
0377 
0378     switch (ctrl->id) {
0379     case V4L2_CID_AUTOGAIN:
0380         ret = ov6650_reg_rmw(client, REG_COMB,
0381                 ctrl->val ? COMB_AGC : 0, COMB_AGC);
0382         if (!ret && !ctrl->val)
0383             ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
0384         return ret;
0385     case V4L2_CID_AUTO_WHITE_BALANCE:
0386         ret = ov6650_reg_rmw(client, REG_COMB,
0387                 ctrl->val ? COMB_AWB : 0, COMB_AWB);
0388         if (!ret && !ctrl->val) {
0389             ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
0390             if (!ret)
0391                 ret = ov6650_reg_write(client, REG_RED,
0392                             priv->red->val);
0393         }
0394         return ret;
0395     case V4L2_CID_SATURATION:
0396         return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
0397                 SAT_MASK);
0398     case V4L2_CID_HUE:
0399         return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
0400                 HUE_MASK);
0401     case V4L2_CID_BRIGHTNESS:
0402         return ov6650_reg_write(client, REG_BRT, ctrl->val);
0403     case V4L2_CID_EXPOSURE_AUTO:
0404         ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
0405                 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
0406         if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
0407             ret = ov6650_reg_write(client, REG_AECH,
0408                         priv->exposure->val);
0409         return ret;
0410     case V4L2_CID_GAMMA:
0411         return ov6650_reg_write(client, REG_GAM1, ctrl->val);
0412     case V4L2_CID_VFLIP:
0413         return ov6650_reg_rmw(client, REG_COMB,
0414                 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
0415     case V4L2_CID_HFLIP:
0416         return ov6650_reg_rmw(client, REG_COMB,
0417                 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
0418     }
0419 
0420     return -EINVAL;
0421 }
0422 
0423 #ifdef CONFIG_VIDEO_ADV_DEBUG
0424 static int ov6650_get_register(struct v4l2_subdev *sd,
0425                 struct v4l2_dbg_register *reg)
0426 {
0427     struct i2c_client *client = v4l2_get_subdevdata(sd);
0428     int ret;
0429     u8 val;
0430 
0431     if (reg->reg & ~0xff)
0432         return -EINVAL;
0433 
0434     reg->size = 1;
0435 
0436     ret = ov6650_reg_read(client, reg->reg, &val);
0437     if (!ret)
0438         reg->val = (__u64)val;
0439 
0440     return ret;
0441 }
0442 
0443 static int ov6650_set_register(struct v4l2_subdev *sd,
0444                 const struct v4l2_dbg_register *reg)
0445 {
0446     struct i2c_client *client = v4l2_get_subdevdata(sd);
0447 
0448     if (reg->reg & ~0xff || reg->val & ~0xff)
0449         return -EINVAL;
0450 
0451     return ov6650_reg_write(client, reg->reg, reg->val);
0452 }
0453 #endif
0454 
0455 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
0456 {
0457     struct i2c_client *client = v4l2_get_subdevdata(sd);
0458     struct ov6650 *priv = to_ov6650(client);
0459     int ret = 0;
0460 
0461     if (on)
0462         ret = clk_prepare_enable(priv->clk);
0463     else
0464         clk_disable_unprepare(priv->clk);
0465 
0466     return ret;
0467 }
0468 
0469 static int ov6650_get_selection(struct v4l2_subdev *sd,
0470         struct v4l2_subdev_state *sd_state,
0471         struct v4l2_subdev_selection *sel)
0472 {
0473     struct i2c_client *client = v4l2_get_subdevdata(sd);
0474     struct ov6650 *priv = to_ov6650(client);
0475     struct v4l2_rect *rect;
0476 
0477     if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
0478         /* pre-select try crop rectangle */
0479         rect = &sd_state->pads->try_crop;
0480 
0481     } else {
0482         /* pre-select active crop rectangle */
0483         rect = &priv->rect;
0484     }
0485 
0486     switch (sel->target) {
0487     case V4L2_SEL_TGT_CROP_BOUNDS:
0488         sel->r.left = DEF_HSTRT << 1;
0489         sel->r.top = DEF_VSTRT << 1;
0490         sel->r.width = W_CIF;
0491         sel->r.height = H_CIF;
0492         return 0;
0493 
0494     case V4L2_SEL_TGT_CROP:
0495         /* use selected crop rectangle */
0496         sel->r = *rect;
0497         return 0;
0498 
0499     default:
0500         return -EINVAL;
0501     }
0502 }
0503 
0504 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
0505 {
0506     return width > rect->width >> 1 || height > rect->height >> 1;
0507 }
0508 
0509 static void ov6650_bind_align_crop_rectangle(struct v4l2_rect *rect)
0510 {
0511     v4l_bound_align_image(&rect->width, 2, W_CIF, 1,
0512                   &rect->height, 2, H_CIF, 1, 0);
0513     v4l_bound_align_image(&rect->left, DEF_HSTRT << 1,
0514                   (DEF_HSTRT << 1) + W_CIF - (__s32)rect->width, 1,
0515                   &rect->top, DEF_VSTRT << 1,
0516                   (DEF_VSTRT << 1) + H_CIF - (__s32)rect->height,
0517                   1, 0);
0518 }
0519 
0520 static int ov6650_set_selection(struct v4l2_subdev *sd,
0521         struct v4l2_subdev_state *sd_state,
0522         struct v4l2_subdev_selection *sel)
0523 {
0524     struct i2c_client *client = v4l2_get_subdevdata(sd);
0525     struct ov6650 *priv = to_ov6650(client);
0526     int ret;
0527 
0528     if (sel->target != V4L2_SEL_TGT_CROP)
0529         return -EINVAL;
0530 
0531     ov6650_bind_align_crop_rectangle(&sel->r);
0532 
0533     if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
0534         struct v4l2_rect *crop = &sd_state->pads->try_crop;
0535         struct v4l2_mbus_framefmt *mf = &sd_state->pads->try_fmt;
0536         /* detect current pad config scaling factor */
0537         bool half_scale = !is_unscaled_ok(mf->width, mf->height, crop);
0538 
0539         /* store new crop rectangle */
0540         *crop = sel->r;
0541 
0542         /* adjust frame size */
0543         mf->width = crop->width >> half_scale;
0544         mf->height = crop->height >> half_scale;
0545 
0546         return 0;
0547     }
0548 
0549     /* V4L2_SUBDEV_FORMAT_ACTIVE */
0550 
0551     /* apply new crop rectangle */
0552     ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
0553     if (!ret) {
0554         priv->rect.width += priv->rect.left - sel->r.left;
0555         priv->rect.left = sel->r.left;
0556         ret = ov6650_reg_write(client, REG_HSTOP,
0557                        (sel->r.left + sel->r.width) >> 1);
0558     }
0559     if (!ret) {
0560         priv->rect.width = sel->r.width;
0561         ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
0562     }
0563     if (!ret) {
0564         priv->rect.height += priv->rect.top - sel->r.top;
0565         priv->rect.top = sel->r.top;
0566         ret = ov6650_reg_write(client, REG_VSTOP,
0567                        (sel->r.top + sel->r.height) >> 1);
0568     }
0569     if (!ret)
0570         priv->rect.height = sel->r.height;
0571 
0572     return ret;
0573 }
0574 
0575 static int ov6650_get_fmt(struct v4l2_subdev *sd,
0576         struct v4l2_subdev_state *sd_state,
0577         struct v4l2_subdev_format *format)
0578 {
0579     struct v4l2_mbus_framefmt *mf = &format->format;
0580     struct i2c_client *client = v4l2_get_subdevdata(sd);
0581     struct ov6650 *priv = to_ov6650(client);
0582 
0583     if (format->pad)
0584         return -EINVAL;
0585 
0586     /* initialize response with default media bus frame format */
0587     *mf = ov6650_def_fmt;
0588 
0589     /* update media bus format code and frame size */
0590     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
0591         mf->width = sd_state->pads->try_fmt.width;
0592         mf->height = sd_state->pads->try_fmt.height;
0593         mf->code = sd_state->pads->try_fmt.code;
0594 
0595     } else {
0596         mf->width = priv->rect.width >> priv->half_scale;
0597         mf->height = priv->rect.height >> priv->half_scale;
0598         mf->code = priv->code;
0599     }
0600     return 0;
0601 }
0602 
0603 #define to_clkrc(div)   ((div) - 1)
0604 
0605 /* set the format we will capture in */
0606 static int ov6650_s_fmt(struct v4l2_subdev *sd, u32 code, bool half_scale)
0607 {
0608     struct i2c_client *client = v4l2_get_subdevdata(sd);
0609     struct ov6650 *priv = to_ov6650(client);
0610     u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask;
0611     int ret;
0612 
0613     /* select color matrix configuration for given color encoding */
0614     switch (code) {
0615     case MEDIA_BUS_FMT_Y8_1X8:
0616         dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
0617         coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
0618         coma_set |= COMA_BW;
0619         break;
0620     case MEDIA_BUS_FMT_YUYV8_2X8:
0621         dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
0622         coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
0623         coma_set |= COMA_WORD_SWAP;
0624         break;
0625     case MEDIA_BUS_FMT_YVYU8_2X8:
0626         dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
0627         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
0628                 COMA_BYTE_SWAP;
0629         break;
0630     case MEDIA_BUS_FMT_UYVY8_2X8:
0631         dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
0632         if (half_scale) {
0633             coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
0634             coma_set |= COMA_BYTE_SWAP;
0635         } else {
0636             coma_mask |= COMA_RGB | COMA_BW;
0637             coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
0638         }
0639         break;
0640     case MEDIA_BUS_FMT_VYUY8_2X8:
0641         dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
0642         if (half_scale) {
0643             coma_mask |= COMA_RGB | COMA_BW;
0644             coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
0645         } else {
0646             coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
0647             coma_set |= COMA_BYTE_SWAP;
0648         }
0649         break;
0650     case MEDIA_BUS_FMT_SBGGR8_1X8:
0651         dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
0652         coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
0653         coma_set |= COMA_RAW_RGB | COMA_RGB;
0654         break;
0655     default:
0656         dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
0657         return -EINVAL;
0658     }
0659 
0660     if (code == MEDIA_BUS_FMT_Y8_1X8 ||
0661             code == MEDIA_BUS_FMT_SBGGR8_1X8) {
0662         coml_mask = COML_ONE_CHANNEL;
0663         coml_set = 0;
0664     } else {
0665         coml_mask = 0;
0666         coml_set = COML_ONE_CHANNEL;
0667     }
0668 
0669     if (half_scale) {
0670         dev_dbg(&client->dev, "max resolution: QCIF\n");
0671         coma_set |= COMA_QCIF;
0672     } else {
0673         dev_dbg(&client->dev, "max resolution: CIF\n");
0674         coma_mask |= COMA_QCIF;
0675     }
0676 
0677     ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
0678     if (!ret) {
0679         priv->half_scale = half_scale;
0680 
0681         ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
0682     }
0683     if (!ret)
0684         priv->code = code;
0685 
0686     return ret;
0687 }
0688 
0689 static int ov6650_set_fmt(struct v4l2_subdev *sd,
0690         struct v4l2_subdev_state *sd_state,
0691         struct v4l2_subdev_format *format)
0692 {
0693     struct v4l2_mbus_framefmt *mf = &format->format;
0694     struct i2c_client *client = v4l2_get_subdevdata(sd);
0695     struct ov6650 *priv = to_ov6650(client);
0696     struct v4l2_rect *crop;
0697     bool half_scale;
0698 
0699     if (format->pad)
0700         return -EINVAL;
0701 
0702     switch (mf->code) {
0703     case MEDIA_BUS_FMT_Y10_1X10:
0704         mf->code = MEDIA_BUS_FMT_Y8_1X8;
0705         fallthrough;
0706     case MEDIA_BUS_FMT_Y8_1X8:
0707     case MEDIA_BUS_FMT_YVYU8_2X8:
0708     case MEDIA_BUS_FMT_YUYV8_2X8:
0709     case MEDIA_BUS_FMT_VYUY8_2X8:
0710     case MEDIA_BUS_FMT_UYVY8_2X8:
0711         break;
0712     default:
0713         mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
0714         fallthrough;
0715     case MEDIA_BUS_FMT_SBGGR8_1X8:
0716         break;
0717     }
0718 
0719     if (format->which == V4L2_SUBDEV_FORMAT_TRY)
0720         crop = &sd_state->pads->try_crop;
0721     else
0722         crop = &priv->rect;
0723 
0724     half_scale = !is_unscaled_ok(mf->width, mf->height, crop);
0725 
0726     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
0727         /* store new mbus frame format code and size in pad config */
0728         sd_state->pads->try_fmt.width = crop->width >> half_scale;
0729         sd_state->pads->try_fmt.height = crop->height >> half_scale;
0730         sd_state->pads->try_fmt.code = mf->code;
0731 
0732         /* return default mbus frame format updated with pad config */
0733         *mf = ov6650_def_fmt;
0734         mf->width = sd_state->pads->try_fmt.width;
0735         mf->height = sd_state->pads->try_fmt.height;
0736         mf->code = sd_state->pads->try_fmt.code;
0737 
0738     } else {
0739         int ret = 0;
0740 
0741         /* apply new media bus frame format and scaling if changed */
0742         if (mf->code != priv->code || half_scale != priv->half_scale)
0743             ret = ov6650_s_fmt(sd, mf->code, half_scale);
0744         if (ret)
0745             return ret;
0746 
0747         /* return default format updated with active size and code */
0748         *mf = ov6650_def_fmt;
0749         mf->width = priv->rect.width >> priv->half_scale;
0750         mf->height = priv->rect.height >> priv->half_scale;
0751         mf->code = priv->code;
0752     }
0753     return 0;
0754 }
0755 
0756 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
0757         struct v4l2_subdev_state *sd_state,
0758         struct v4l2_subdev_mbus_code_enum *code)
0759 {
0760     if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
0761         return -EINVAL;
0762 
0763     code->code = ov6650_codes[code->index];
0764     return 0;
0765 }
0766 
0767 static int ov6650_enum_frame_interval(struct v4l2_subdev *sd,
0768                     struct v4l2_subdev_state *sd_state,
0769                     struct v4l2_subdev_frame_interval_enum *fie)
0770 {
0771     int i;
0772 
0773     /* enumerate supported frame intervals not exceeding 1 second */
0774     if (fie->index > CLKRC_DIV_MASK ||
0775         GET_CLKRC_DIV(fie->index) > FRAME_RATE_MAX)
0776         return -EINVAL;
0777 
0778     for (i = 0; i < ARRAY_SIZE(ov6650_codes); i++)
0779         if (fie->code == ov6650_codes[i])
0780             break;
0781     if (i == ARRAY_SIZE(ov6650_codes))
0782         return -EINVAL;
0783 
0784     if (!fie->width || fie->width > W_CIF ||
0785         !fie->height || fie->height > H_CIF)
0786         return -EINVAL;
0787 
0788     fie->interval.numerator = GET_CLKRC_DIV(fie->index);
0789     fie->interval.denominator = FRAME_RATE_MAX;
0790 
0791     return 0;
0792 }
0793 
0794 static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
0795                    struct v4l2_subdev_frame_interval *ival)
0796 {
0797     struct i2c_client *client = v4l2_get_subdevdata(sd);
0798     struct ov6650 *priv = to_ov6650(client);
0799 
0800     ival->interval = priv->tpf;
0801 
0802     dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
0803         ival->interval.numerator, ival->interval.denominator);
0804 
0805     return 0;
0806 }
0807 
0808 static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
0809                    struct v4l2_subdev_frame_interval *ival)
0810 {
0811     struct i2c_client *client = v4l2_get_subdevdata(sd);
0812     struct ov6650 *priv = to_ov6650(client);
0813     struct v4l2_fract *tpf = &ival->interval;
0814     int div, ret;
0815 
0816     if (tpf->numerator == 0 || tpf->denominator == 0)
0817         div = 1;  /* Reset to full rate */
0818     else
0819         div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
0820 
0821     if (div == 0)
0822         div = 1;
0823     else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
0824         div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
0825 
0826     ret = ov6650_reg_rmw(client, REG_CLKRC, to_clkrc(div), CLKRC_DIV_MASK);
0827     if (!ret) {
0828         priv->tpf.numerator = div;
0829         priv->tpf.denominator = FRAME_RATE_MAX;
0830 
0831         *tpf = priv->tpf;
0832     }
0833 
0834     return ret;
0835 }
0836 
0837 /* Soft reset the camera. This has nothing to do with the RESET pin! */
0838 static int ov6650_reset(struct i2c_client *client)
0839 {
0840     int ret;
0841 
0842     dev_dbg(&client->dev, "reset\n");
0843 
0844     ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
0845     if (ret)
0846         dev_err(&client->dev,
0847             "An error occurred while entering soft reset!\n");
0848 
0849     return ret;
0850 }
0851 
0852 /* program default register values */
0853 static int ov6650_prog_dflt(struct i2c_client *client, u8 clkrc)
0854 {
0855     int ret;
0856 
0857     dev_dbg(&client->dev, "initializing\n");
0858 
0859     ret = ov6650_reg_write(client, REG_COMA, 0);    /* ~COMA_RESET */
0860     if (!ret)
0861         ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
0862     if (!ret)
0863         ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
0864 
0865     return ret;
0866 }
0867 
0868 static int ov6650_video_probe(struct v4l2_subdev *sd)
0869 {
0870     struct i2c_client *client = v4l2_get_subdevdata(sd);
0871     struct ov6650 *priv = to_ov6650(client);
0872     const struct ov6650_xclk *xclk = NULL;
0873     unsigned long rate;
0874     u8 pidh, pidl, midh, midl;
0875     int i, ret = 0;
0876 
0877     priv->clk = devm_clk_get(&client->dev, NULL);
0878     if (IS_ERR(priv->clk)) {
0879         ret = PTR_ERR(priv->clk);
0880         dev_err(&client->dev, "clk request err: %d\n", ret);
0881         return ret;
0882     }
0883 
0884     rate = clk_get_rate(priv->clk);
0885     for (i = 0; rate && i < ARRAY_SIZE(ov6650_xclk); i++) {
0886         if (rate != ov6650_xclk[i].rate)
0887             continue;
0888 
0889         xclk = &ov6650_xclk[i];
0890         dev_info(&client->dev, "using host default clock rate %lukHz\n",
0891              rate / 1000);
0892         break;
0893     }
0894     for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) {
0895         ret = clk_set_rate(priv->clk, ov6650_xclk[i].rate);
0896         if (ret || clk_get_rate(priv->clk) != ov6650_xclk[i].rate)
0897             continue;
0898 
0899         xclk = &ov6650_xclk[i];
0900         dev_info(&client->dev, "using negotiated clock rate %lukHz\n",
0901              xclk->rate / 1000);
0902         break;
0903     }
0904     if (!xclk) {
0905         dev_err(&client->dev, "unable to get supported clock rate\n");
0906         if (!ret)
0907             ret = -EINVAL;
0908         return ret;
0909     }
0910 
0911     ret = ov6650_s_power(sd, 1);
0912     if (ret < 0)
0913         return ret;
0914 
0915     msleep(20);
0916 
0917     /*
0918      * check and show product ID and manufacturer ID
0919      */
0920     ret = ov6650_reg_read(client, REG_PIDH, &pidh);
0921     if (!ret)
0922         ret = ov6650_reg_read(client, REG_PIDL, &pidl);
0923     if (!ret)
0924         ret = ov6650_reg_read(client, REG_MIDH, &midh);
0925     if (!ret)
0926         ret = ov6650_reg_read(client, REG_MIDL, &midl);
0927 
0928     if (ret)
0929         goto done;
0930 
0931     if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
0932         dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
0933                 pidh, pidl);
0934         ret = -ENODEV;
0935         goto done;
0936     }
0937 
0938     dev_info(&client->dev,
0939         "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
0940         pidh, pidl, midh, midl);
0941 
0942     ret = ov6650_reset(client);
0943     if (!ret)
0944         ret = ov6650_prog_dflt(client, xclk->clkrc);
0945     if (!ret) {
0946         /* driver default frame format, no scaling */
0947         ret = ov6650_s_fmt(sd, ov6650_def_fmt.code, false);
0948     }
0949     if (!ret)
0950         ret = v4l2_ctrl_handler_setup(&priv->hdl);
0951 
0952 done:
0953     ov6650_s_power(sd, 0);
0954     return ret;
0955 }
0956 
0957 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
0958     .g_volatile_ctrl = ov6550_g_volatile_ctrl,
0959     .s_ctrl = ov6550_s_ctrl,
0960 };
0961 
0962 static const struct v4l2_subdev_core_ops ov6650_core_ops = {
0963 #ifdef CONFIG_VIDEO_ADV_DEBUG
0964     .g_register     = ov6650_get_register,
0965     .s_register     = ov6650_set_register,
0966 #endif
0967     .s_power        = ov6650_s_power,
0968 };
0969 
0970 /* Request bus settings on camera side */
0971 static int ov6650_get_mbus_config(struct v4l2_subdev *sd,
0972                   unsigned int pad,
0973                   struct v4l2_mbus_config *cfg)
0974 {
0975     struct i2c_client *client = v4l2_get_subdevdata(sd);
0976     u8 comj, comf;
0977     int ret;
0978 
0979     ret = ov6650_reg_read(client, REG_COMJ, &comj);
0980     if (ret)
0981         return ret;
0982 
0983     ret = ov6650_reg_read(client, REG_COMF, &comf);
0984     if (ret)
0985         return ret;
0986 
0987     cfg->type = V4L2_MBUS_PARALLEL;
0988 
0989     cfg->bus.parallel.flags = V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH
0990         | ((comj & COMJ_VSYNC_HIGH)  ? V4L2_MBUS_VSYNC_ACTIVE_HIGH
0991                          : V4L2_MBUS_VSYNC_ACTIVE_LOW)
0992         | ((comf & COMF_HREF_LOW)    ? V4L2_MBUS_HSYNC_ACTIVE_LOW
0993                          : V4L2_MBUS_HSYNC_ACTIVE_HIGH)
0994         | ((comj & COMJ_PCLK_RISING) ? V4L2_MBUS_PCLK_SAMPLE_RISING
0995                          : V4L2_MBUS_PCLK_SAMPLE_FALLING);
0996     return 0;
0997 }
0998 
0999 static const struct v4l2_subdev_video_ops ov6650_video_ops = {
1000     .s_stream   = ov6650_s_stream,
1001     .g_frame_interval = ov6650_g_frame_interval,
1002     .s_frame_interval = ov6650_s_frame_interval,
1003 };
1004 
1005 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
1006     .enum_mbus_code     = ov6650_enum_mbus_code,
1007     .enum_frame_interval    = ov6650_enum_frame_interval,
1008     .get_selection      = ov6650_get_selection,
1009     .set_selection      = ov6650_set_selection,
1010     .get_fmt        = ov6650_get_fmt,
1011     .set_fmt        = ov6650_set_fmt,
1012     .get_mbus_config    = ov6650_get_mbus_config,
1013 };
1014 
1015 static const struct v4l2_subdev_ops ov6650_subdev_ops = {
1016     .core   = &ov6650_core_ops,
1017     .video  = &ov6650_video_ops,
1018     .pad    = &ov6650_pad_ops,
1019 };
1020 
1021 static const struct v4l2_subdev_internal_ops ov6650_internal_ops = {
1022     .registered = ov6650_video_probe,
1023 };
1024 
1025 /*
1026  * i2c_driver function
1027  */
1028 static int ov6650_probe(struct i2c_client *client,
1029             const struct i2c_device_id *did)
1030 {
1031     struct ov6650 *priv;
1032     int ret;
1033 
1034     priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1035     if (!priv)
1036         return -ENOMEM;
1037 
1038     v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
1039     v4l2_ctrl_handler_init(&priv->hdl, 13);
1040     v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1041             V4L2_CID_VFLIP, 0, 1, 1, 0);
1042     v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1043             V4L2_CID_HFLIP, 0, 1, 1, 0);
1044     priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1045             V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1046     priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1047             V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
1048     priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1049             V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1050     priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1051             V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1052     priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1053             V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1054     v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1055             V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1056     v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1057             V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1058     v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1059             V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1060     priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1061             &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1062             V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1063     priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1064             V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1065     v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1066             V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1067 
1068     priv->subdev.ctrl_handler = &priv->hdl;
1069     if (priv->hdl.error) {
1070         ret = priv->hdl.error;
1071         goto ectlhdlfree;
1072     }
1073 
1074     v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1075     v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1076     v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1077                 V4L2_EXPOSURE_MANUAL, true);
1078 
1079     priv->rect.left   = DEF_HSTRT << 1;
1080     priv->rect.top    = DEF_VSTRT << 1;
1081     priv->rect.width  = W_CIF;
1082     priv->rect.height = H_CIF;
1083 
1084     /* Hardware default frame interval */
1085     priv->tpf.numerator   = GET_CLKRC_DIV(DEF_CLKRC);
1086     priv->tpf.denominator = FRAME_RATE_MAX;
1087 
1088     priv->subdev.internal_ops = &ov6650_internal_ops;
1089 
1090     ret = v4l2_async_register_subdev(&priv->subdev);
1091     if (!ret)
1092         return 0;
1093 ectlhdlfree:
1094     v4l2_ctrl_handler_free(&priv->hdl);
1095 
1096     return ret;
1097 }
1098 
1099 static int ov6650_remove(struct i2c_client *client)
1100 {
1101     struct ov6650 *priv = to_ov6650(client);
1102 
1103     v4l2_async_unregister_subdev(&priv->subdev);
1104     v4l2_ctrl_handler_free(&priv->hdl);
1105     return 0;
1106 }
1107 
1108 static const struct i2c_device_id ov6650_id[] = {
1109     { "ov6650", 0 },
1110     { }
1111 };
1112 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1113 
1114 static struct i2c_driver ov6650_i2c_driver = {
1115     .driver = {
1116         .name = "ov6650",
1117     },
1118     .probe    = ov6650_probe,
1119     .remove   = ov6650_remove,
1120     .id_table = ov6650_id,
1121 };
1122 
1123 module_i2c_driver(ov6650_i2c_driver);
1124 
1125 MODULE_DESCRIPTION("V4L2 subdevice driver for OmniVision OV6650 camera sensor");
1126 MODULE_AUTHOR("Janusz Krzysztofik <jmkrzyszt@gmail.com");
1127 MODULE_LICENSE("GPL v2");
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