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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for the OV5645 camera sensor.
0004  *
0005  * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
0006  * Copyright (C) 2015 By Tech Design S.L. All Rights Reserved.
0007  * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
0008  *
0009  * Based on:
0010  * - the OV5645 driver from QC msm-3.10 kernel on codeaurora.org:
0011  *   https://us.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/
0012  *       media/platform/msm/camera_v2/sensor/ov5645.c?h=LA.BR.1.2.4_rb1.41
0013  * - the OV5640 driver posted on linux-media:
0014  *   https://www.mail-archive.com/linux-media%40vger.kernel.org/msg92671.html
0015  */
0016 
0017 /*
0018  */
0019 
0020 #include <linux/bitops.h>
0021 #include <linux/clk.h>
0022 #include <linux/delay.h>
0023 #include <linux/device.h>
0024 #include <linux/gpio/consumer.h>
0025 #include <linux/i2c.h>
0026 #include <linux/init.h>
0027 #include <linux/module.h>
0028 #include <linux/of.h>
0029 #include <linux/of_graph.h>
0030 #include <linux/regulator/consumer.h>
0031 #include <linux/slab.h>
0032 #include <linux/types.h>
0033 #include <media/v4l2-ctrls.h>
0034 #include <media/v4l2-fwnode.h>
0035 #include <media/v4l2-subdev.h>
0036 
0037 #define OV5645_SYSTEM_CTRL0     0x3008
0038 #define     OV5645_SYSTEM_CTRL0_START   0x02
0039 #define     OV5645_SYSTEM_CTRL0_STOP    0x42
0040 #define OV5645_CHIP_ID_HIGH     0x300a
0041 #define     OV5645_CHIP_ID_HIGH_BYTE    0x56
0042 #define OV5645_CHIP_ID_LOW      0x300b
0043 #define     OV5645_CHIP_ID_LOW_BYTE     0x45
0044 #define OV5645_IO_MIPI_CTRL00       0x300e
0045 #define OV5645_PAD_OUTPUT00     0x3019
0046 #define OV5645_AWB_MANUAL_CONTROL   0x3406
0047 #define     OV5645_AWB_MANUAL_ENABLE    BIT(0)
0048 #define OV5645_AEC_PK_MANUAL        0x3503
0049 #define     OV5645_AEC_MANUAL_ENABLE    BIT(0)
0050 #define     OV5645_AGC_MANUAL_ENABLE    BIT(1)
0051 #define OV5645_TIMING_TC_REG20      0x3820
0052 #define     OV5645_SENSOR_VFLIP     BIT(1)
0053 #define     OV5645_ISP_VFLIP        BIT(2)
0054 #define OV5645_TIMING_TC_REG21      0x3821
0055 #define     OV5645_SENSOR_MIRROR        BIT(1)
0056 #define OV5645_MIPI_CTRL00      0x4800
0057 #define OV5645_PRE_ISP_TEST_SETTING_1   0x503d
0058 #define     OV5645_TEST_PATTERN_MASK    0x3
0059 #define     OV5645_SET_TEST_PATTERN(x)  ((x) & OV5645_TEST_PATTERN_MASK)
0060 #define     OV5645_TEST_PATTERN_ENABLE  BIT(7)
0061 #define OV5645_SDE_SAT_U        0x5583
0062 #define OV5645_SDE_SAT_V        0x5584
0063 
0064 /* regulator supplies */
0065 static const char * const ov5645_supply_name[] = {
0066     "vdddo", /* Digital I/O (1.8V) supply */
0067     "vdda",  /* Analog (2.8V) supply */
0068     "vddd",  /* Digital Core (1.5V) supply */
0069 };
0070 
0071 #define OV5645_NUM_SUPPLIES ARRAY_SIZE(ov5645_supply_name)
0072 
0073 struct reg_value {
0074     u16 reg;
0075     u8 val;
0076 };
0077 
0078 struct ov5645_mode_info {
0079     u32 width;
0080     u32 height;
0081     const struct reg_value *data;
0082     u32 data_size;
0083     u32 pixel_clock;
0084     u32 link_freq;
0085 };
0086 
0087 struct ov5645 {
0088     struct i2c_client *i2c_client;
0089     struct device *dev;
0090     struct v4l2_subdev sd;
0091     struct media_pad pad;
0092     struct v4l2_fwnode_endpoint ep;
0093     struct v4l2_mbus_framefmt fmt;
0094     struct v4l2_rect crop;
0095     struct clk *xclk;
0096 
0097     struct regulator_bulk_data supplies[OV5645_NUM_SUPPLIES];
0098 
0099     const struct ov5645_mode_info *current_mode;
0100 
0101     struct v4l2_ctrl_handler ctrls;
0102     struct v4l2_ctrl *pixel_clock;
0103     struct v4l2_ctrl *link_freq;
0104 
0105     /* Cached register values */
0106     u8 aec_pk_manual;
0107     u8 timing_tc_reg20;
0108     u8 timing_tc_reg21;
0109 
0110     struct mutex power_lock; /* lock to protect power state */
0111     int power_count;
0112 
0113     struct gpio_desc *enable_gpio;
0114     struct gpio_desc *rst_gpio;
0115 };
0116 
0117 static inline struct ov5645 *to_ov5645(struct v4l2_subdev *sd)
0118 {
0119     return container_of(sd, struct ov5645, sd);
0120 }
0121 
0122 static const struct reg_value ov5645_global_init_setting[] = {
0123     { 0x3103, 0x11 },
0124     { 0x3008, 0x82 },
0125     { 0x3008, 0x42 },
0126     { 0x3103, 0x03 },
0127     { 0x3503, 0x07 },
0128     { 0x3002, 0x1c },
0129     { 0x3006, 0xc3 },
0130     { 0x3017, 0x00 },
0131     { 0x3018, 0x00 },
0132     { 0x302e, 0x0b },
0133     { 0x3037, 0x13 },
0134     { 0x3108, 0x01 },
0135     { 0x3611, 0x06 },
0136     { 0x3500, 0x00 },
0137     { 0x3501, 0x01 },
0138     { 0x3502, 0x00 },
0139     { 0x350a, 0x00 },
0140     { 0x350b, 0x3f },
0141     { 0x3620, 0x33 },
0142     { 0x3621, 0xe0 },
0143     { 0x3622, 0x01 },
0144     { 0x3630, 0x2e },
0145     { 0x3631, 0x00 },
0146     { 0x3632, 0x32 },
0147     { 0x3633, 0x52 },
0148     { 0x3634, 0x70 },
0149     { 0x3635, 0x13 },
0150     { 0x3636, 0x03 },
0151     { 0x3703, 0x5a },
0152     { 0x3704, 0xa0 },
0153     { 0x3705, 0x1a },
0154     { 0x3709, 0x12 },
0155     { 0x370b, 0x61 },
0156     { 0x370f, 0x10 },
0157     { 0x3715, 0x78 },
0158     { 0x3717, 0x01 },
0159     { 0x371b, 0x20 },
0160     { 0x3731, 0x12 },
0161     { 0x3901, 0x0a },
0162     { 0x3905, 0x02 },
0163     { 0x3906, 0x10 },
0164     { 0x3719, 0x86 },
0165     { 0x3810, 0x00 },
0166     { 0x3811, 0x10 },
0167     { 0x3812, 0x00 },
0168     { 0x3821, 0x01 },
0169     { 0x3824, 0x01 },
0170     { 0x3826, 0x03 },
0171     { 0x3828, 0x08 },
0172     { 0x3a19, 0xf8 },
0173     { 0x3c01, 0x34 },
0174     { 0x3c04, 0x28 },
0175     { 0x3c05, 0x98 },
0176     { 0x3c07, 0x07 },
0177     { 0x3c09, 0xc2 },
0178     { 0x3c0a, 0x9c },
0179     { 0x3c0b, 0x40 },
0180     { 0x3c01, 0x34 },
0181     { 0x4001, 0x02 },
0182     { 0x4514, 0x00 },
0183     { 0x4520, 0xb0 },
0184     { 0x460b, 0x37 },
0185     { 0x460c, 0x20 },
0186     { 0x4818, 0x01 },
0187     { 0x481d, 0xf0 },
0188     { 0x481f, 0x50 },
0189     { 0x4823, 0x70 },
0190     { 0x4831, 0x14 },
0191     { 0x5000, 0xa7 },
0192     { 0x5001, 0x83 },
0193     { 0x501d, 0x00 },
0194     { 0x501f, 0x00 },
0195     { 0x503d, 0x00 },
0196     { 0x505c, 0x30 },
0197     { 0x5181, 0x59 },
0198     { 0x5183, 0x00 },
0199     { 0x5191, 0xf0 },
0200     { 0x5192, 0x03 },
0201     { 0x5684, 0x10 },
0202     { 0x5685, 0xa0 },
0203     { 0x5686, 0x0c },
0204     { 0x5687, 0x78 },
0205     { 0x5a00, 0x08 },
0206     { 0x5a21, 0x00 },
0207     { 0x5a24, 0x00 },
0208     { 0x3008, 0x02 },
0209     { 0x3503, 0x00 },
0210     { 0x5180, 0xff },
0211     { 0x5181, 0xf2 },
0212     { 0x5182, 0x00 },
0213     { 0x5183, 0x14 },
0214     { 0x5184, 0x25 },
0215     { 0x5185, 0x24 },
0216     { 0x5186, 0x09 },
0217     { 0x5187, 0x09 },
0218     { 0x5188, 0x0a },
0219     { 0x5189, 0x75 },
0220     { 0x518a, 0x52 },
0221     { 0x518b, 0xea },
0222     { 0x518c, 0xa8 },
0223     { 0x518d, 0x42 },
0224     { 0x518e, 0x38 },
0225     { 0x518f, 0x56 },
0226     { 0x5190, 0x42 },
0227     { 0x5191, 0xf8 },
0228     { 0x5192, 0x04 },
0229     { 0x5193, 0x70 },
0230     { 0x5194, 0xf0 },
0231     { 0x5195, 0xf0 },
0232     { 0x5196, 0x03 },
0233     { 0x5197, 0x01 },
0234     { 0x5198, 0x04 },
0235     { 0x5199, 0x12 },
0236     { 0x519a, 0x04 },
0237     { 0x519b, 0x00 },
0238     { 0x519c, 0x06 },
0239     { 0x519d, 0x82 },
0240     { 0x519e, 0x38 },
0241     { 0x5381, 0x1e },
0242     { 0x5382, 0x5b },
0243     { 0x5383, 0x08 },
0244     { 0x5384, 0x0a },
0245     { 0x5385, 0x7e },
0246     { 0x5386, 0x88 },
0247     { 0x5387, 0x7c },
0248     { 0x5388, 0x6c },
0249     { 0x5389, 0x10 },
0250     { 0x538a, 0x01 },
0251     { 0x538b, 0x98 },
0252     { 0x5300, 0x08 },
0253     { 0x5301, 0x30 },
0254     { 0x5302, 0x10 },
0255     { 0x5303, 0x00 },
0256     { 0x5304, 0x08 },
0257     { 0x5305, 0x30 },
0258     { 0x5306, 0x08 },
0259     { 0x5307, 0x16 },
0260     { 0x5309, 0x08 },
0261     { 0x530a, 0x30 },
0262     { 0x530b, 0x04 },
0263     { 0x530c, 0x06 },
0264     { 0x5480, 0x01 },
0265     { 0x5481, 0x08 },
0266     { 0x5482, 0x14 },
0267     { 0x5483, 0x28 },
0268     { 0x5484, 0x51 },
0269     { 0x5485, 0x65 },
0270     { 0x5486, 0x71 },
0271     { 0x5487, 0x7d },
0272     { 0x5488, 0x87 },
0273     { 0x5489, 0x91 },
0274     { 0x548a, 0x9a },
0275     { 0x548b, 0xaa },
0276     { 0x548c, 0xb8 },
0277     { 0x548d, 0xcd },
0278     { 0x548e, 0xdd },
0279     { 0x548f, 0xea },
0280     { 0x5490, 0x1d },
0281     { 0x5580, 0x02 },
0282     { 0x5583, 0x40 },
0283     { 0x5584, 0x10 },
0284     { 0x5589, 0x10 },
0285     { 0x558a, 0x00 },
0286     { 0x558b, 0xf8 },
0287     { 0x5800, 0x3f },
0288     { 0x5801, 0x16 },
0289     { 0x5802, 0x0e },
0290     { 0x5803, 0x0d },
0291     { 0x5804, 0x17 },
0292     { 0x5805, 0x3f },
0293     { 0x5806, 0x0b },
0294     { 0x5807, 0x06 },
0295     { 0x5808, 0x04 },
0296     { 0x5809, 0x04 },
0297     { 0x580a, 0x06 },
0298     { 0x580b, 0x0b },
0299     { 0x580c, 0x09 },
0300     { 0x580d, 0x03 },
0301     { 0x580e, 0x00 },
0302     { 0x580f, 0x00 },
0303     { 0x5810, 0x03 },
0304     { 0x5811, 0x08 },
0305     { 0x5812, 0x0a },
0306     { 0x5813, 0x03 },
0307     { 0x5814, 0x00 },
0308     { 0x5815, 0x00 },
0309     { 0x5816, 0x04 },
0310     { 0x5817, 0x09 },
0311     { 0x5818, 0x0f },
0312     { 0x5819, 0x08 },
0313     { 0x581a, 0x06 },
0314     { 0x581b, 0x06 },
0315     { 0x581c, 0x08 },
0316     { 0x581d, 0x0c },
0317     { 0x581e, 0x3f },
0318     { 0x581f, 0x1e },
0319     { 0x5820, 0x12 },
0320     { 0x5821, 0x13 },
0321     { 0x5822, 0x21 },
0322     { 0x5823, 0x3f },
0323     { 0x5824, 0x68 },
0324     { 0x5825, 0x28 },
0325     { 0x5826, 0x2c },
0326     { 0x5827, 0x28 },
0327     { 0x5828, 0x08 },
0328     { 0x5829, 0x48 },
0329     { 0x582a, 0x64 },
0330     { 0x582b, 0x62 },
0331     { 0x582c, 0x64 },
0332     { 0x582d, 0x28 },
0333     { 0x582e, 0x46 },
0334     { 0x582f, 0x62 },
0335     { 0x5830, 0x60 },
0336     { 0x5831, 0x62 },
0337     { 0x5832, 0x26 },
0338     { 0x5833, 0x48 },
0339     { 0x5834, 0x66 },
0340     { 0x5835, 0x44 },
0341     { 0x5836, 0x64 },
0342     { 0x5837, 0x28 },
0343     { 0x5838, 0x66 },
0344     { 0x5839, 0x48 },
0345     { 0x583a, 0x2c },
0346     { 0x583b, 0x28 },
0347     { 0x583c, 0x26 },
0348     { 0x583d, 0xae },
0349     { 0x5025, 0x00 },
0350     { 0x3a0f, 0x30 },
0351     { 0x3a10, 0x28 },
0352     { 0x3a1b, 0x30 },
0353     { 0x3a1e, 0x26 },
0354     { 0x3a11, 0x60 },
0355     { 0x3a1f, 0x14 },
0356     { 0x0601, 0x02 },
0357     { 0x3008, 0x42 },
0358     { 0x3008, 0x02 },
0359     { OV5645_IO_MIPI_CTRL00, 0x40 },
0360     { OV5645_MIPI_CTRL00, 0x24 },
0361     { OV5645_PAD_OUTPUT00, 0x70 }
0362 };
0363 
0364 static const struct reg_value ov5645_setting_sxga[] = {
0365     { 0x3612, 0xa9 },
0366     { 0x3614, 0x50 },
0367     { 0x3618, 0x00 },
0368     { 0x3034, 0x18 },
0369     { 0x3035, 0x21 },
0370     { 0x3036, 0x70 },
0371     { 0x3600, 0x09 },
0372     { 0x3601, 0x43 },
0373     { 0x3708, 0x66 },
0374     { 0x370c, 0xc3 },
0375     { 0x3800, 0x00 },
0376     { 0x3801, 0x00 },
0377     { 0x3802, 0x00 },
0378     { 0x3803, 0x06 },
0379     { 0x3804, 0x0a },
0380     { 0x3805, 0x3f },
0381     { 0x3806, 0x07 },
0382     { 0x3807, 0x9d },
0383     { 0x3808, 0x05 },
0384     { 0x3809, 0x00 },
0385     { 0x380a, 0x03 },
0386     { 0x380b, 0xc0 },
0387     { 0x380c, 0x07 },
0388     { 0x380d, 0x68 },
0389     { 0x380e, 0x03 },
0390     { 0x380f, 0xd8 },
0391     { 0x3813, 0x06 },
0392     { 0x3814, 0x31 },
0393     { 0x3815, 0x31 },
0394     { 0x3820, 0x47 },
0395     { 0x3a02, 0x03 },
0396     { 0x3a03, 0xd8 },
0397     { 0x3a08, 0x01 },
0398     { 0x3a09, 0xf8 },
0399     { 0x3a0a, 0x01 },
0400     { 0x3a0b, 0xa4 },
0401     { 0x3a0e, 0x02 },
0402     { 0x3a0d, 0x02 },
0403     { 0x3a14, 0x03 },
0404     { 0x3a15, 0xd8 },
0405     { 0x3a18, 0x00 },
0406     { 0x4004, 0x02 },
0407     { 0x4005, 0x18 },
0408     { 0x4300, 0x32 },
0409     { 0x4202, 0x00 }
0410 };
0411 
0412 static const struct reg_value ov5645_setting_1080p[] = {
0413     { 0x3612, 0xab },
0414     { 0x3614, 0x50 },
0415     { 0x3618, 0x04 },
0416     { 0x3034, 0x18 },
0417     { 0x3035, 0x11 },
0418     { 0x3036, 0x54 },
0419     { 0x3600, 0x08 },
0420     { 0x3601, 0x33 },
0421     { 0x3708, 0x63 },
0422     { 0x370c, 0xc0 },
0423     { 0x3800, 0x01 },
0424     { 0x3801, 0x50 },
0425     { 0x3802, 0x01 },
0426     { 0x3803, 0xb2 },
0427     { 0x3804, 0x08 },
0428     { 0x3805, 0xef },
0429     { 0x3806, 0x05 },
0430     { 0x3807, 0xf1 },
0431     { 0x3808, 0x07 },
0432     { 0x3809, 0x80 },
0433     { 0x380a, 0x04 },
0434     { 0x380b, 0x38 },
0435     { 0x380c, 0x09 },
0436     { 0x380d, 0xc4 },
0437     { 0x380e, 0x04 },
0438     { 0x380f, 0x60 },
0439     { 0x3813, 0x04 },
0440     { 0x3814, 0x11 },
0441     { 0x3815, 0x11 },
0442     { 0x3820, 0x47 },
0443     { 0x4514, 0x88 },
0444     { 0x3a02, 0x04 },
0445     { 0x3a03, 0x60 },
0446     { 0x3a08, 0x01 },
0447     { 0x3a09, 0x50 },
0448     { 0x3a0a, 0x01 },
0449     { 0x3a0b, 0x18 },
0450     { 0x3a0e, 0x03 },
0451     { 0x3a0d, 0x04 },
0452     { 0x3a14, 0x04 },
0453     { 0x3a15, 0x60 },
0454     { 0x3a18, 0x00 },
0455     { 0x4004, 0x06 },
0456     { 0x4005, 0x18 },
0457     { 0x4300, 0x32 },
0458     { 0x4202, 0x00 },
0459     { 0x4837, 0x0b }
0460 };
0461 
0462 static const struct reg_value ov5645_setting_full[] = {
0463     { 0x3612, 0xab },
0464     { 0x3614, 0x50 },
0465     { 0x3618, 0x04 },
0466     { 0x3034, 0x18 },
0467     { 0x3035, 0x11 },
0468     { 0x3036, 0x54 },
0469     { 0x3600, 0x08 },
0470     { 0x3601, 0x33 },
0471     { 0x3708, 0x63 },
0472     { 0x370c, 0xc0 },
0473     { 0x3800, 0x00 },
0474     { 0x3801, 0x00 },
0475     { 0x3802, 0x00 },
0476     { 0x3803, 0x00 },
0477     { 0x3804, 0x0a },
0478     { 0x3805, 0x3f },
0479     { 0x3806, 0x07 },
0480     { 0x3807, 0x9f },
0481     { 0x3808, 0x0a },
0482     { 0x3809, 0x20 },
0483     { 0x380a, 0x07 },
0484     { 0x380b, 0x98 },
0485     { 0x380c, 0x0b },
0486     { 0x380d, 0x1c },
0487     { 0x380e, 0x07 },
0488     { 0x380f, 0xb0 },
0489     { 0x3813, 0x06 },
0490     { 0x3814, 0x11 },
0491     { 0x3815, 0x11 },
0492     { 0x3820, 0x47 },
0493     { 0x4514, 0x88 },
0494     { 0x3a02, 0x07 },
0495     { 0x3a03, 0xb0 },
0496     { 0x3a08, 0x01 },
0497     { 0x3a09, 0x27 },
0498     { 0x3a0a, 0x00 },
0499     { 0x3a0b, 0xf6 },
0500     { 0x3a0e, 0x06 },
0501     { 0x3a0d, 0x08 },
0502     { 0x3a14, 0x07 },
0503     { 0x3a15, 0xb0 },
0504     { 0x3a18, 0x01 },
0505     { 0x4004, 0x06 },
0506     { 0x4005, 0x18 },
0507     { 0x4300, 0x32 },
0508     { 0x4837, 0x0b },
0509     { 0x4202, 0x00 }
0510 };
0511 
0512 static const s64 link_freq[] = {
0513     224000000,
0514     336000000
0515 };
0516 
0517 static const struct ov5645_mode_info ov5645_mode_info_data[] = {
0518     {
0519         .width = 1280,
0520         .height = 960,
0521         .data = ov5645_setting_sxga,
0522         .data_size = ARRAY_SIZE(ov5645_setting_sxga),
0523         .pixel_clock = 112000000,
0524         .link_freq = 0 /* an index in link_freq[] */
0525     },
0526     {
0527         .width = 1920,
0528         .height = 1080,
0529         .data = ov5645_setting_1080p,
0530         .data_size = ARRAY_SIZE(ov5645_setting_1080p),
0531         .pixel_clock = 168000000,
0532         .link_freq = 1 /* an index in link_freq[] */
0533     },
0534     {
0535         .width = 2592,
0536         .height = 1944,
0537         .data = ov5645_setting_full,
0538         .data_size = ARRAY_SIZE(ov5645_setting_full),
0539         .pixel_clock = 168000000,
0540         .link_freq = 1 /* an index in link_freq[] */
0541     },
0542 };
0543 
0544 static int ov5645_write_reg(struct ov5645 *ov5645, u16 reg, u8 val)
0545 {
0546     u8 regbuf[3];
0547     int ret;
0548 
0549     regbuf[0] = reg >> 8;
0550     regbuf[1] = reg & 0xff;
0551     regbuf[2] = val;
0552 
0553     ret = i2c_master_send(ov5645->i2c_client, regbuf, 3);
0554     if (ret < 0) {
0555         dev_err(ov5645->dev, "%s: write reg error %d: reg=%x, val=%x\n",
0556             __func__, ret, reg, val);
0557         return ret;
0558     }
0559 
0560     return 0;
0561 }
0562 
0563 static int ov5645_read_reg(struct ov5645 *ov5645, u16 reg, u8 *val)
0564 {
0565     u8 regbuf[2];
0566     int ret;
0567 
0568     regbuf[0] = reg >> 8;
0569     regbuf[1] = reg & 0xff;
0570 
0571     ret = i2c_master_send(ov5645->i2c_client, regbuf, 2);
0572     if (ret < 0) {
0573         dev_err(ov5645->dev, "%s: write reg error %d: reg=%x\n",
0574             __func__, ret, reg);
0575         return ret;
0576     }
0577 
0578     ret = i2c_master_recv(ov5645->i2c_client, val, 1);
0579     if (ret < 0) {
0580         dev_err(ov5645->dev, "%s: read reg error %d: reg=%x\n",
0581             __func__, ret, reg);
0582         return ret;
0583     }
0584 
0585     return 0;
0586 }
0587 
0588 static int ov5645_set_aec_mode(struct ov5645 *ov5645, u32 mode)
0589 {
0590     u8 val = ov5645->aec_pk_manual;
0591     int ret;
0592 
0593     if (mode == V4L2_EXPOSURE_AUTO)
0594         val &= ~OV5645_AEC_MANUAL_ENABLE;
0595     else /* V4L2_EXPOSURE_MANUAL */
0596         val |= OV5645_AEC_MANUAL_ENABLE;
0597 
0598     ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
0599     if (!ret)
0600         ov5645->aec_pk_manual = val;
0601 
0602     return ret;
0603 }
0604 
0605 static int ov5645_set_agc_mode(struct ov5645 *ov5645, u32 enable)
0606 {
0607     u8 val = ov5645->aec_pk_manual;
0608     int ret;
0609 
0610     if (enable)
0611         val &= ~OV5645_AGC_MANUAL_ENABLE;
0612     else
0613         val |= OV5645_AGC_MANUAL_ENABLE;
0614 
0615     ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
0616     if (!ret)
0617         ov5645->aec_pk_manual = val;
0618 
0619     return ret;
0620 }
0621 
0622 static int ov5645_set_register_array(struct ov5645 *ov5645,
0623                      const struct reg_value *settings,
0624                      unsigned int num_settings)
0625 {
0626     unsigned int i;
0627     int ret;
0628 
0629     for (i = 0; i < num_settings; ++i, ++settings) {
0630         ret = ov5645_write_reg(ov5645, settings->reg, settings->val);
0631         if (ret < 0)
0632             return ret;
0633     }
0634 
0635     return 0;
0636 }
0637 
0638 static int ov5645_set_power_on(struct ov5645 *ov5645)
0639 {
0640     int ret;
0641 
0642     ret = regulator_bulk_enable(OV5645_NUM_SUPPLIES, ov5645->supplies);
0643     if (ret < 0)
0644         return ret;
0645 
0646     ret = clk_prepare_enable(ov5645->xclk);
0647     if (ret < 0) {
0648         dev_err(ov5645->dev, "clk prepare enable failed\n");
0649         regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
0650         return ret;
0651     }
0652 
0653     usleep_range(5000, 15000);
0654     gpiod_set_value_cansleep(ov5645->enable_gpio, 1);
0655 
0656     usleep_range(1000, 2000);
0657     gpiod_set_value_cansleep(ov5645->rst_gpio, 0);
0658 
0659     msleep(20);
0660 
0661     return 0;
0662 }
0663 
0664 static void ov5645_set_power_off(struct ov5645 *ov5645)
0665 {
0666     gpiod_set_value_cansleep(ov5645->rst_gpio, 1);
0667     gpiod_set_value_cansleep(ov5645->enable_gpio, 0);
0668     clk_disable_unprepare(ov5645->xclk);
0669     regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
0670 }
0671 
0672 static int ov5645_s_power(struct v4l2_subdev *sd, int on)
0673 {
0674     struct ov5645 *ov5645 = to_ov5645(sd);
0675     int ret = 0;
0676 
0677     mutex_lock(&ov5645->power_lock);
0678 
0679     /* If the power count is modified from 0 to != 0 or from != 0 to 0,
0680      * update the power state.
0681      */
0682     if (ov5645->power_count == !on) {
0683         if (on) {
0684             ret = ov5645_set_power_on(ov5645);
0685             if (ret < 0)
0686                 goto exit;
0687 
0688             ret = ov5645_set_register_array(ov5645,
0689                     ov5645_global_init_setting,
0690                     ARRAY_SIZE(ov5645_global_init_setting));
0691             if (ret < 0) {
0692                 dev_err(ov5645->dev,
0693                     "could not set init registers\n");
0694                 ov5645_set_power_off(ov5645);
0695                 goto exit;
0696             }
0697 
0698             usleep_range(500, 1000);
0699         } else {
0700             ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x58);
0701             ov5645_set_power_off(ov5645);
0702         }
0703     }
0704 
0705     /* Update the power count. */
0706     ov5645->power_count += on ? 1 : -1;
0707     WARN_ON(ov5645->power_count < 0);
0708 
0709 exit:
0710     mutex_unlock(&ov5645->power_lock);
0711 
0712     return ret;
0713 }
0714 
0715 static int ov5645_set_saturation(struct ov5645 *ov5645, s32 value)
0716 {
0717     u32 reg_value = (value * 0x10) + 0x40;
0718     int ret;
0719 
0720     ret = ov5645_write_reg(ov5645, OV5645_SDE_SAT_U, reg_value);
0721     if (ret < 0)
0722         return ret;
0723 
0724     return ov5645_write_reg(ov5645, OV5645_SDE_SAT_V, reg_value);
0725 }
0726 
0727 static int ov5645_set_hflip(struct ov5645 *ov5645, s32 value)
0728 {
0729     u8 val = ov5645->timing_tc_reg21;
0730     int ret;
0731 
0732     if (value == 0)
0733         val &= ~(OV5645_SENSOR_MIRROR);
0734     else
0735         val |= (OV5645_SENSOR_MIRROR);
0736 
0737     ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG21, val);
0738     if (!ret)
0739         ov5645->timing_tc_reg21 = val;
0740 
0741     return ret;
0742 }
0743 
0744 static int ov5645_set_vflip(struct ov5645 *ov5645, s32 value)
0745 {
0746     u8 val = ov5645->timing_tc_reg20;
0747     int ret;
0748 
0749     if (value == 0)
0750         val |= (OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
0751     else
0752         val &= ~(OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
0753 
0754     ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG20, val);
0755     if (!ret)
0756         ov5645->timing_tc_reg20 = val;
0757 
0758     return ret;
0759 }
0760 
0761 static int ov5645_set_test_pattern(struct ov5645 *ov5645, s32 value)
0762 {
0763     u8 val = 0;
0764 
0765     if (value) {
0766         val = OV5645_SET_TEST_PATTERN(value - 1);
0767         val |= OV5645_TEST_PATTERN_ENABLE;
0768     }
0769 
0770     return ov5645_write_reg(ov5645, OV5645_PRE_ISP_TEST_SETTING_1, val);
0771 }
0772 
0773 static const char * const ov5645_test_pattern_menu[] = {
0774     "Disabled",
0775     "Vertical Color Bars",
0776     "Pseudo-Random Data",
0777     "Color Square",
0778     "Black Image",
0779 };
0780 
0781 static int ov5645_set_awb(struct ov5645 *ov5645, s32 enable_auto)
0782 {
0783     u8 val = 0;
0784 
0785     if (!enable_auto)
0786         val = OV5645_AWB_MANUAL_ENABLE;
0787 
0788     return ov5645_write_reg(ov5645, OV5645_AWB_MANUAL_CONTROL, val);
0789 }
0790 
0791 static int ov5645_s_ctrl(struct v4l2_ctrl *ctrl)
0792 {
0793     struct ov5645 *ov5645 = container_of(ctrl->handler,
0794                          struct ov5645, ctrls);
0795     int ret;
0796 
0797     mutex_lock(&ov5645->power_lock);
0798     if (!ov5645->power_count) {
0799         mutex_unlock(&ov5645->power_lock);
0800         return 0;
0801     }
0802 
0803     switch (ctrl->id) {
0804     case V4L2_CID_SATURATION:
0805         ret = ov5645_set_saturation(ov5645, ctrl->val);
0806         break;
0807     case V4L2_CID_AUTO_WHITE_BALANCE:
0808         ret = ov5645_set_awb(ov5645, ctrl->val);
0809         break;
0810     case V4L2_CID_AUTOGAIN:
0811         ret = ov5645_set_agc_mode(ov5645, ctrl->val);
0812         break;
0813     case V4L2_CID_EXPOSURE_AUTO:
0814         ret = ov5645_set_aec_mode(ov5645, ctrl->val);
0815         break;
0816     case V4L2_CID_TEST_PATTERN:
0817         ret = ov5645_set_test_pattern(ov5645, ctrl->val);
0818         break;
0819     case V4L2_CID_HFLIP:
0820         ret = ov5645_set_hflip(ov5645, ctrl->val);
0821         break;
0822     case V4L2_CID_VFLIP:
0823         ret = ov5645_set_vflip(ov5645, ctrl->val);
0824         break;
0825     default:
0826         ret = -EINVAL;
0827         break;
0828     }
0829 
0830     mutex_unlock(&ov5645->power_lock);
0831 
0832     return ret;
0833 }
0834 
0835 static const struct v4l2_ctrl_ops ov5645_ctrl_ops = {
0836     .s_ctrl = ov5645_s_ctrl,
0837 };
0838 
0839 static int ov5645_enum_mbus_code(struct v4l2_subdev *sd,
0840                  struct v4l2_subdev_state *sd_state,
0841                  struct v4l2_subdev_mbus_code_enum *code)
0842 {
0843     if (code->index > 0)
0844         return -EINVAL;
0845 
0846     code->code = MEDIA_BUS_FMT_UYVY8_1X16;
0847 
0848     return 0;
0849 }
0850 
0851 static int ov5645_enum_frame_size(struct v4l2_subdev *subdev,
0852                   struct v4l2_subdev_state *sd_state,
0853                   struct v4l2_subdev_frame_size_enum *fse)
0854 {
0855     if (fse->code != MEDIA_BUS_FMT_UYVY8_1X16)
0856         return -EINVAL;
0857 
0858     if (fse->index >= ARRAY_SIZE(ov5645_mode_info_data))
0859         return -EINVAL;
0860 
0861     fse->min_width = ov5645_mode_info_data[fse->index].width;
0862     fse->max_width = ov5645_mode_info_data[fse->index].width;
0863     fse->min_height = ov5645_mode_info_data[fse->index].height;
0864     fse->max_height = ov5645_mode_info_data[fse->index].height;
0865 
0866     return 0;
0867 }
0868 
0869 static struct v4l2_mbus_framefmt *
0870 __ov5645_get_pad_format(struct ov5645 *ov5645,
0871             struct v4l2_subdev_state *sd_state,
0872             unsigned int pad,
0873             enum v4l2_subdev_format_whence which)
0874 {
0875     switch (which) {
0876     case V4L2_SUBDEV_FORMAT_TRY:
0877         return v4l2_subdev_get_try_format(&ov5645->sd, sd_state, pad);
0878     case V4L2_SUBDEV_FORMAT_ACTIVE:
0879         return &ov5645->fmt;
0880     default:
0881         return NULL;
0882     }
0883 }
0884 
0885 static int ov5645_get_format(struct v4l2_subdev *sd,
0886                  struct v4l2_subdev_state *sd_state,
0887                  struct v4l2_subdev_format *format)
0888 {
0889     struct ov5645 *ov5645 = to_ov5645(sd);
0890 
0891     format->format = *__ov5645_get_pad_format(ov5645, sd_state,
0892                           format->pad,
0893                           format->which);
0894     return 0;
0895 }
0896 
0897 static struct v4l2_rect *
0898 __ov5645_get_pad_crop(struct ov5645 *ov5645,
0899               struct v4l2_subdev_state *sd_state,
0900               unsigned int pad, enum v4l2_subdev_format_whence which)
0901 {
0902     switch (which) {
0903     case V4L2_SUBDEV_FORMAT_TRY:
0904         return v4l2_subdev_get_try_crop(&ov5645->sd, sd_state, pad);
0905     case V4L2_SUBDEV_FORMAT_ACTIVE:
0906         return &ov5645->crop;
0907     default:
0908         return NULL;
0909     }
0910 }
0911 
0912 static int ov5645_set_format(struct v4l2_subdev *sd,
0913                  struct v4l2_subdev_state *sd_state,
0914                  struct v4l2_subdev_format *format)
0915 {
0916     struct ov5645 *ov5645 = to_ov5645(sd);
0917     struct v4l2_mbus_framefmt *__format;
0918     struct v4l2_rect *__crop;
0919     const struct ov5645_mode_info *new_mode;
0920     int ret;
0921 
0922     __crop = __ov5645_get_pad_crop(ov5645, sd_state, format->pad,
0923                        format->which);
0924 
0925     new_mode = v4l2_find_nearest_size(ov5645_mode_info_data,
0926                    ARRAY_SIZE(ov5645_mode_info_data),
0927                    width, height,
0928                    format->format.width, format->format.height);
0929 
0930     __crop->width = new_mode->width;
0931     __crop->height = new_mode->height;
0932 
0933     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
0934         ret = v4l2_ctrl_s_ctrl_int64(ov5645->pixel_clock,
0935                          new_mode->pixel_clock);
0936         if (ret < 0)
0937             return ret;
0938 
0939         ret = v4l2_ctrl_s_ctrl(ov5645->link_freq,
0940                        new_mode->link_freq);
0941         if (ret < 0)
0942             return ret;
0943 
0944         ov5645->current_mode = new_mode;
0945     }
0946 
0947     __format = __ov5645_get_pad_format(ov5645, sd_state, format->pad,
0948                        format->which);
0949     __format->width = __crop->width;
0950     __format->height = __crop->height;
0951     __format->code = MEDIA_BUS_FMT_UYVY8_1X16;
0952     __format->field = V4L2_FIELD_NONE;
0953     __format->colorspace = V4L2_COLORSPACE_SRGB;
0954 
0955     format->format = *__format;
0956 
0957     return 0;
0958 }
0959 
0960 static int ov5645_entity_init_cfg(struct v4l2_subdev *subdev,
0961                   struct v4l2_subdev_state *sd_state)
0962 {
0963     struct v4l2_subdev_format fmt = { 0 };
0964 
0965     fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
0966     fmt.format.width = 1920;
0967     fmt.format.height = 1080;
0968 
0969     ov5645_set_format(subdev, sd_state, &fmt);
0970 
0971     return 0;
0972 }
0973 
0974 static int ov5645_get_selection(struct v4l2_subdev *sd,
0975                struct v4l2_subdev_state *sd_state,
0976                struct v4l2_subdev_selection *sel)
0977 {
0978     struct ov5645 *ov5645 = to_ov5645(sd);
0979 
0980     if (sel->target != V4L2_SEL_TGT_CROP)
0981         return -EINVAL;
0982 
0983     sel->r = *__ov5645_get_pad_crop(ov5645, sd_state, sel->pad,
0984                     sel->which);
0985     return 0;
0986 }
0987 
0988 static int ov5645_s_stream(struct v4l2_subdev *subdev, int enable)
0989 {
0990     struct ov5645 *ov5645 = to_ov5645(subdev);
0991     int ret;
0992 
0993     if (enable) {
0994         ret = ov5645_set_register_array(ov5645,
0995                     ov5645->current_mode->data,
0996                     ov5645->current_mode->data_size);
0997         if (ret < 0) {
0998             dev_err(ov5645->dev, "could not set mode %dx%d\n",
0999                 ov5645->current_mode->width,
1000                 ov5645->current_mode->height);
1001             return ret;
1002         }
1003         ret = v4l2_ctrl_handler_setup(&ov5645->ctrls);
1004         if (ret < 0) {
1005             dev_err(ov5645->dev, "could not sync v4l2 controls\n");
1006             return ret;
1007         }
1008 
1009         ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x45);
1010         if (ret < 0)
1011             return ret;
1012 
1013         ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1014                        OV5645_SYSTEM_CTRL0_START);
1015         if (ret < 0)
1016             return ret;
1017     } else {
1018         ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x40);
1019         if (ret < 0)
1020             return ret;
1021 
1022         ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1023                        OV5645_SYSTEM_CTRL0_STOP);
1024         if (ret < 0)
1025             return ret;
1026     }
1027 
1028     return 0;
1029 }
1030 
1031 static const struct v4l2_subdev_core_ops ov5645_core_ops = {
1032     .s_power = ov5645_s_power,
1033 };
1034 
1035 static const struct v4l2_subdev_video_ops ov5645_video_ops = {
1036     .s_stream = ov5645_s_stream,
1037 };
1038 
1039 static const struct v4l2_subdev_pad_ops ov5645_subdev_pad_ops = {
1040     .init_cfg = ov5645_entity_init_cfg,
1041     .enum_mbus_code = ov5645_enum_mbus_code,
1042     .enum_frame_size = ov5645_enum_frame_size,
1043     .get_fmt = ov5645_get_format,
1044     .set_fmt = ov5645_set_format,
1045     .get_selection = ov5645_get_selection,
1046 };
1047 
1048 static const struct v4l2_subdev_ops ov5645_subdev_ops = {
1049     .core = &ov5645_core_ops,
1050     .video = &ov5645_video_ops,
1051     .pad = &ov5645_subdev_pad_ops,
1052 };
1053 
1054 static int ov5645_probe(struct i2c_client *client)
1055 {
1056     struct device *dev = &client->dev;
1057     struct device_node *endpoint;
1058     struct ov5645 *ov5645;
1059     u8 chip_id_high, chip_id_low;
1060     unsigned int i;
1061     u32 xclk_freq;
1062     int ret;
1063 
1064     ov5645 = devm_kzalloc(dev, sizeof(struct ov5645), GFP_KERNEL);
1065     if (!ov5645)
1066         return -ENOMEM;
1067 
1068     ov5645->i2c_client = client;
1069     ov5645->dev = dev;
1070 
1071     endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1072     if (!endpoint) {
1073         dev_err(dev, "endpoint node not found\n");
1074         return -EINVAL;
1075     }
1076 
1077     ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1078                      &ov5645->ep);
1079 
1080     of_node_put(endpoint);
1081 
1082     if (ret < 0) {
1083         dev_err(dev, "parsing endpoint node failed\n");
1084         return ret;
1085     }
1086 
1087     if (ov5645->ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1088         dev_err(dev, "invalid bus type, must be CSI2\n");
1089         return -EINVAL;
1090     }
1091 
1092     /* get system clock (xclk) */
1093     ov5645->xclk = devm_clk_get(dev, "xclk");
1094     if (IS_ERR(ov5645->xclk)) {
1095         dev_err(dev, "could not get xclk");
1096         return PTR_ERR(ov5645->xclk);
1097     }
1098 
1099     ret = of_property_read_u32(dev->of_node, "clock-frequency", &xclk_freq);
1100     if (ret) {
1101         dev_err(dev, "could not get xclk frequency\n");
1102         return ret;
1103     }
1104 
1105     /* external clock must be 24MHz, allow 1% tolerance */
1106     if (xclk_freq < 23760000 || xclk_freq > 24240000) {
1107         dev_err(dev, "external clock frequency %u is not supported\n",
1108             xclk_freq);
1109         return -EINVAL;
1110     }
1111 
1112     ret = clk_set_rate(ov5645->xclk, xclk_freq);
1113     if (ret) {
1114         dev_err(dev, "could not set xclk frequency\n");
1115         return ret;
1116     }
1117 
1118     for (i = 0; i < OV5645_NUM_SUPPLIES; i++)
1119         ov5645->supplies[i].supply = ov5645_supply_name[i];
1120 
1121     ret = devm_regulator_bulk_get(dev, OV5645_NUM_SUPPLIES,
1122                       ov5645->supplies);
1123     if (ret < 0)
1124         return ret;
1125 
1126     ov5645->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
1127     if (IS_ERR(ov5645->enable_gpio)) {
1128         dev_err(dev, "cannot get enable gpio\n");
1129         return PTR_ERR(ov5645->enable_gpio);
1130     }
1131 
1132     ov5645->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
1133     if (IS_ERR(ov5645->rst_gpio)) {
1134         dev_err(dev, "cannot get reset gpio\n");
1135         return PTR_ERR(ov5645->rst_gpio);
1136     }
1137 
1138     mutex_init(&ov5645->power_lock);
1139 
1140     v4l2_ctrl_handler_init(&ov5645->ctrls, 9);
1141     v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1142               V4L2_CID_SATURATION, -4, 4, 1, 0);
1143     v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1144               V4L2_CID_HFLIP, 0, 1, 1, 0);
1145     v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1146               V4L2_CID_VFLIP, 0, 1, 1, 0);
1147     v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1148               V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1149     v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1150               V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1151     v4l2_ctrl_new_std_menu(&ov5645->ctrls, &ov5645_ctrl_ops,
1152                    V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL,
1153                    0, V4L2_EXPOSURE_AUTO);
1154     v4l2_ctrl_new_std_menu_items(&ov5645->ctrls, &ov5645_ctrl_ops,
1155                      V4L2_CID_TEST_PATTERN,
1156                      ARRAY_SIZE(ov5645_test_pattern_menu) - 1,
1157                      0, 0, ov5645_test_pattern_menu);
1158     ov5645->pixel_clock = v4l2_ctrl_new_std(&ov5645->ctrls,
1159                         &ov5645_ctrl_ops,
1160                         V4L2_CID_PIXEL_RATE,
1161                         1, INT_MAX, 1, 1);
1162     ov5645->link_freq = v4l2_ctrl_new_int_menu(&ov5645->ctrls,
1163                            &ov5645_ctrl_ops,
1164                            V4L2_CID_LINK_FREQ,
1165                            ARRAY_SIZE(link_freq) - 1,
1166                            0, link_freq);
1167     if (ov5645->link_freq)
1168         ov5645->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1169 
1170     ov5645->sd.ctrl_handler = &ov5645->ctrls;
1171 
1172     if (ov5645->ctrls.error) {
1173         dev_err(dev, "%s: control initialization error %d\n",
1174                __func__, ov5645->ctrls.error);
1175         ret = ov5645->ctrls.error;
1176         goto free_ctrl;
1177     }
1178 
1179     v4l2_i2c_subdev_init(&ov5645->sd, client, &ov5645_subdev_ops);
1180     ov5645->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1181     ov5645->pad.flags = MEDIA_PAD_FL_SOURCE;
1182     ov5645->sd.dev = &client->dev;
1183     ov5645->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1184 
1185     ret = media_entity_pads_init(&ov5645->sd.entity, 1, &ov5645->pad);
1186     if (ret < 0) {
1187         dev_err(dev, "could not register media entity\n");
1188         goto free_ctrl;
1189     }
1190 
1191     ret = ov5645_s_power(&ov5645->sd, true);
1192     if (ret < 0) {
1193         dev_err(dev, "could not power up OV5645\n");
1194         goto free_entity;
1195     }
1196 
1197     ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_HIGH, &chip_id_high);
1198     if (ret < 0 || chip_id_high != OV5645_CHIP_ID_HIGH_BYTE) {
1199         dev_err(dev, "could not read ID high\n");
1200         ret = -ENODEV;
1201         goto power_down;
1202     }
1203     ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_LOW, &chip_id_low);
1204     if (ret < 0 || chip_id_low != OV5645_CHIP_ID_LOW_BYTE) {
1205         dev_err(dev, "could not read ID low\n");
1206         ret = -ENODEV;
1207         goto power_down;
1208     }
1209 
1210     dev_info(dev, "OV5645 detected at address 0x%02x\n", client->addr);
1211 
1212     ret = ov5645_read_reg(ov5645, OV5645_AEC_PK_MANUAL,
1213                   &ov5645->aec_pk_manual);
1214     if (ret < 0) {
1215         dev_err(dev, "could not read AEC/AGC mode\n");
1216         ret = -ENODEV;
1217         goto power_down;
1218     }
1219 
1220     ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG20,
1221                   &ov5645->timing_tc_reg20);
1222     if (ret < 0) {
1223         dev_err(dev, "could not read vflip value\n");
1224         ret = -ENODEV;
1225         goto power_down;
1226     }
1227 
1228     ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG21,
1229                   &ov5645->timing_tc_reg21);
1230     if (ret < 0) {
1231         dev_err(dev, "could not read hflip value\n");
1232         ret = -ENODEV;
1233         goto power_down;
1234     }
1235 
1236     ov5645_s_power(&ov5645->sd, false);
1237 
1238     ret = v4l2_async_register_subdev(&ov5645->sd);
1239     if (ret < 0) {
1240         dev_err(dev, "could not register v4l2 device\n");
1241         goto free_entity;
1242     }
1243 
1244     ov5645_entity_init_cfg(&ov5645->sd, NULL);
1245 
1246     return 0;
1247 
1248 power_down:
1249     ov5645_s_power(&ov5645->sd, false);
1250 free_entity:
1251     media_entity_cleanup(&ov5645->sd.entity);
1252 free_ctrl:
1253     v4l2_ctrl_handler_free(&ov5645->ctrls);
1254     mutex_destroy(&ov5645->power_lock);
1255 
1256     return ret;
1257 }
1258 
1259 static int ov5645_remove(struct i2c_client *client)
1260 {
1261     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1262     struct ov5645 *ov5645 = to_ov5645(sd);
1263 
1264     v4l2_async_unregister_subdev(&ov5645->sd);
1265     media_entity_cleanup(&ov5645->sd.entity);
1266     v4l2_ctrl_handler_free(&ov5645->ctrls);
1267     mutex_destroy(&ov5645->power_lock);
1268 
1269     return 0;
1270 }
1271 
1272 static const struct i2c_device_id ov5645_id[] = {
1273     { "ov5645", 0 },
1274     {}
1275 };
1276 MODULE_DEVICE_TABLE(i2c, ov5645_id);
1277 
1278 static const struct of_device_id ov5645_of_match[] = {
1279     { .compatible = "ovti,ov5645" },
1280     { /* sentinel */ }
1281 };
1282 MODULE_DEVICE_TABLE(of, ov5645_of_match);
1283 
1284 static struct i2c_driver ov5645_i2c_driver = {
1285     .driver = {
1286         .of_match_table = ov5645_of_match,
1287         .name  = "ov5645",
1288     },
1289     .probe_new = ov5645_probe,
1290     .remove = ov5645_remove,
1291     .id_table = ov5645_id,
1292 };
1293 
1294 module_i2c_driver(ov5645_i2c_driver);
1295 
1296 MODULE_DESCRIPTION("Omnivision OV5645 Camera Driver");
1297 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1298 MODULE_LICENSE("GPL v2");
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