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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2020 Intel Corporation.
0003 
0004 #include <asm/unaligned.h>
0005 #include <linux/acpi.h>
0006 #include <linux/delay.h>
0007 #include <linux/i2c.h>
0008 #include <linux/module.h>
0009 #include <linux/pm_runtime.h>
0010 #include <linux/nvmem-provider.h>
0011 #include <linux/regmap.h>
0012 #include <media/v4l2-ctrls.h>
0013 #include <media/v4l2-device.h>
0014 #include <media/v4l2-fwnode.h>
0015 
0016 #define OV2740_LINK_FREQ_360MHZ     360000000ULL
0017 #define OV2740_SCLK         72000000LL
0018 #define OV2740_MCLK         19200000
0019 #define OV2740_DATA_LANES       2
0020 #define OV2740_RGB_DEPTH        10
0021 
0022 #define OV2740_REG_CHIP_ID      0x300a
0023 #define OV2740_CHIP_ID          0x2740
0024 
0025 #define OV2740_REG_MODE_SELECT      0x0100
0026 #define OV2740_MODE_STANDBY     0x00
0027 #define OV2740_MODE_STREAMING       0x01
0028 
0029 /* vertical-timings from sensor */
0030 #define OV2740_REG_VTS          0x380e
0031 #define OV2740_VTS_DEF          0x088a
0032 #define OV2740_VTS_MIN          0x0460
0033 #define OV2740_VTS_MAX          0x7fff
0034 
0035 /* horizontal-timings from sensor */
0036 #define OV2740_REG_HTS          0x380c
0037 
0038 /* Exposure controls from sensor */
0039 #define OV2740_REG_EXPOSURE     0x3500
0040 #define OV2740_EXPOSURE_MIN     4
0041 #define OV2740_EXPOSURE_MAX_MARGIN  8
0042 #define OV2740_EXPOSURE_STEP        1
0043 
0044 /* Analog gain controls from sensor */
0045 #define OV2740_REG_ANALOG_GAIN      0x3508
0046 #define OV2740_ANAL_GAIN_MIN        128
0047 #define OV2740_ANAL_GAIN_MAX        1983
0048 #define OV2740_ANAL_GAIN_STEP       1
0049 
0050 /* Digital gain controls from sensor */
0051 #define OV2740_REG_MWB_R_GAIN       0x500a
0052 #define OV2740_REG_MWB_G_GAIN       0x500c
0053 #define OV2740_REG_MWB_B_GAIN       0x500e
0054 #define OV2740_DGTL_GAIN_MIN        1024
0055 #define OV2740_DGTL_GAIN_MAX        4095
0056 #define OV2740_DGTL_GAIN_STEP       1
0057 #define OV2740_DGTL_GAIN_DEFAULT    1024
0058 
0059 /* Test Pattern Control */
0060 #define OV2740_REG_TEST_PATTERN     0x5040
0061 #define OV2740_TEST_PATTERN_ENABLE  BIT(7)
0062 #define OV2740_TEST_PATTERN_BAR_SHIFT   2
0063 
0064 /* Group Access */
0065 #define OV2740_REG_GROUP_ACCESS     0x3208
0066 #define OV2740_GROUP_HOLD_START     0x0
0067 #define OV2740_GROUP_HOLD_END       0x10
0068 #define OV2740_GROUP_HOLD_LAUNCH    0xa0
0069 
0070 /* ISP CTRL00 */
0071 #define OV2740_REG_ISP_CTRL00       0x5000
0072 /* ISP CTRL01 */
0073 #define OV2740_REG_ISP_CTRL01       0x5001
0074 /* Customer Addresses: 0x7010 - 0x710F */
0075 #define CUSTOMER_USE_OTP_SIZE       0x100
0076 /* OTP registers from sensor */
0077 #define OV2740_REG_OTP_CUSTOMER     0x7010
0078 
0079 struct nvm_data {
0080     struct i2c_client *client;
0081     struct nvmem_device *nvmem;
0082     struct regmap *regmap;
0083     char *nvm_buffer;
0084 };
0085 
0086 enum {
0087     OV2740_LINK_FREQ_360MHZ_INDEX,
0088 };
0089 
0090 struct ov2740_reg {
0091     u16 address;
0092     u8 val;
0093 };
0094 
0095 struct ov2740_reg_list {
0096     u32 num_of_regs;
0097     const struct ov2740_reg *regs;
0098 };
0099 
0100 struct ov2740_link_freq_config {
0101     const struct ov2740_reg_list reg_list;
0102 };
0103 
0104 struct ov2740_mode {
0105     /* Frame width in pixels */
0106     u32 width;
0107 
0108     /* Frame height in pixels */
0109     u32 height;
0110 
0111     /* Horizontal timining size */
0112     u32 hts;
0113 
0114     /* Default vertical timining size */
0115     u32 vts_def;
0116 
0117     /* Min vertical timining size */
0118     u32 vts_min;
0119 
0120     /* Link frequency needed for this resolution */
0121     u32 link_freq_index;
0122 
0123     /* Sensor register settings for this resolution */
0124     const struct ov2740_reg_list reg_list;
0125 };
0126 
0127 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
0128     {0x0103, 0x01},
0129     {0x0302, 0x4b},
0130     {0x030d, 0x4b},
0131     {0x030e, 0x02},
0132     {0x030a, 0x01},
0133     {0x0312, 0x11},
0134 };
0135 
0136 static const struct ov2740_reg mode_1932x1092_regs[] = {
0137     {0x3000, 0x00},
0138     {0x3018, 0x32},
0139     {0x3031, 0x0a},
0140     {0x3080, 0x08},
0141     {0x3083, 0xB4},
0142     {0x3103, 0x00},
0143     {0x3104, 0x01},
0144     {0x3106, 0x01},
0145     {0x3500, 0x00},
0146     {0x3501, 0x44},
0147     {0x3502, 0x40},
0148     {0x3503, 0x88},
0149     {0x3507, 0x00},
0150     {0x3508, 0x00},
0151     {0x3509, 0x80},
0152     {0x350c, 0x00},
0153     {0x350d, 0x80},
0154     {0x3510, 0x00},
0155     {0x3511, 0x00},
0156     {0x3512, 0x20},
0157     {0x3632, 0x00},
0158     {0x3633, 0x10},
0159     {0x3634, 0x10},
0160     {0x3635, 0x10},
0161     {0x3645, 0x13},
0162     {0x3646, 0x81},
0163     {0x3636, 0x10},
0164     {0x3651, 0x0a},
0165     {0x3656, 0x02},
0166     {0x3659, 0x04},
0167     {0x365a, 0xda},
0168     {0x365b, 0xa2},
0169     {0x365c, 0x04},
0170     {0x365d, 0x1d},
0171     {0x365e, 0x1a},
0172     {0x3662, 0xd7},
0173     {0x3667, 0x78},
0174     {0x3669, 0x0a},
0175     {0x366a, 0x92},
0176     {0x3700, 0x54},
0177     {0x3702, 0x10},
0178     {0x3706, 0x42},
0179     {0x3709, 0x30},
0180     {0x370b, 0xc2},
0181     {0x3714, 0x63},
0182     {0x3715, 0x01},
0183     {0x3716, 0x00},
0184     {0x371a, 0x3e},
0185     {0x3732, 0x0e},
0186     {0x3733, 0x10},
0187     {0x375f, 0x0e},
0188     {0x3768, 0x30},
0189     {0x3769, 0x44},
0190     {0x376a, 0x22},
0191     {0x377b, 0x20},
0192     {0x377c, 0x00},
0193     {0x377d, 0x0c},
0194     {0x3798, 0x00},
0195     {0x37a1, 0x55},
0196     {0x37a8, 0x6d},
0197     {0x37c2, 0x04},
0198     {0x37c5, 0x00},
0199     {0x37c8, 0x00},
0200     {0x3800, 0x00},
0201     {0x3801, 0x00},
0202     {0x3802, 0x00},
0203     {0x3803, 0x00},
0204     {0x3804, 0x07},
0205     {0x3805, 0x8f},
0206     {0x3806, 0x04},
0207     {0x3807, 0x47},
0208     {0x3808, 0x07},
0209     {0x3809, 0x88},
0210     {0x380a, 0x04},
0211     {0x380b, 0x40},
0212     {0x380c, 0x04},
0213     {0x380d, 0x38},
0214     {0x380e, 0x04},
0215     {0x380f, 0x60},
0216     {0x3810, 0x00},
0217     {0x3811, 0x04},
0218     {0x3812, 0x00},
0219     {0x3813, 0x04},
0220     {0x3814, 0x01},
0221     {0x3815, 0x01},
0222     {0x3820, 0x80},
0223     {0x3821, 0x46},
0224     {0x3822, 0x84},
0225     {0x3829, 0x00},
0226     {0x382a, 0x01},
0227     {0x382b, 0x01},
0228     {0x3830, 0x04},
0229     {0x3836, 0x01},
0230     {0x3837, 0x08},
0231     {0x3839, 0x01},
0232     {0x383a, 0x00},
0233     {0x383b, 0x08},
0234     {0x383c, 0x00},
0235     {0x3f0b, 0x00},
0236     {0x4001, 0x20},
0237     {0x4009, 0x07},
0238     {0x4003, 0x10},
0239     {0x4010, 0xe0},
0240     {0x4016, 0x00},
0241     {0x4017, 0x10},
0242     {0x4044, 0x02},
0243     {0x4304, 0x08},
0244     {0x4307, 0x30},
0245     {0x4320, 0x80},
0246     {0x4322, 0x00},
0247     {0x4323, 0x00},
0248     {0x4324, 0x00},
0249     {0x4325, 0x00},
0250     {0x4326, 0x00},
0251     {0x4327, 0x00},
0252     {0x4328, 0x00},
0253     {0x4329, 0x00},
0254     {0x432c, 0x03},
0255     {0x432d, 0x81},
0256     {0x4501, 0x84},
0257     {0x4502, 0x40},
0258     {0x4503, 0x18},
0259     {0x4504, 0x04},
0260     {0x4508, 0x02},
0261     {0x4601, 0x10},
0262     {0x4800, 0x00},
0263     {0x4816, 0x52},
0264     {0x4837, 0x16},
0265     {0x5000, 0x7f},
0266     {0x5001, 0x00},
0267     {0x5005, 0x38},
0268     {0x501e, 0x0d},
0269     {0x5040, 0x00},
0270     {0x5901, 0x00},
0271     {0x3800, 0x00},
0272     {0x3801, 0x00},
0273     {0x3802, 0x00},
0274     {0x3803, 0x00},
0275     {0x3804, 0x07},
0276     {0x3805, 0x8f},
0277     {0x3806, 0x04},
0278     {0x3807, 0x47},
0279     {0x3808, 0x07},
0280     {0x3809, 0x8c},
0281     {0x380a, 0x04},
0282     {0x380b, 0x44},
0283     {0x3810, 0x00},
0284     {0x3811, 0x00},
0285     {0x3812, 0x00},
0286     {0x3813, 0x01},
0287 };
0288 
0289 static const char * const ov2740_test_pattern_menu[] = {
0290     "Disabled",
0291     "Color Bar",
0292     "Top-Bottom Darker Color Bar",
0293     "Right-Left Darker Color Bar",
0294     "Bottom-Top Darker Color Bar",
0295 };
0296 
0297 static const s64 link_freq_menu_items[] = {
0298     OV2740_LINK_FREQ_360MHZ,
0299 };
0300 
0301 static const struct ov2740_link_freq_config link_freq_configs[] = {
0302     [OV2740_LINK_FREQ_360MHZ_INDEX] = {
0303         .reg_list = {
0304             .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
0305             .regs = mipi_data_rate_720mbps,
0306         }
0307     },
0308 };
0309 
0310 static const struct ov2740_mode supported_modes[] = {
0311     {
0312         .width = 1932,
0313         .height = 1092,
0314         .hts = 1080,
0315         .vts_def = OV2740_VTS_DEF,
0316         .vts_min = OV2740_VTS_MIN,
0317         .reg_list = {
0318             .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
0319             .regs = mode_1932x1092_regs,
0320         },
0321         .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
0322     },
0323 };
0324 
0325 struct ov2740 {
0326     struct v4l2_subdev sd;
0327     struct media_pad pad;
0328     struct v4l2_ctrl_handler ctrl_handler;
0329 
0330     /* V4L2 Controls */
0331     struct v4l2_ctrl *link_freq;
0332     struct v4l2_ctrl *pixel_rate;
0333     struct v4l2_ctrl *vblank;
0334     struct v4l2_ctrl *hblank;
0335     struct v4l2_ctrl *exposure;
0336 
0337     /* Current mode */
0338     const struct ov2740_mode *cur_mode;
0339 
0340     /* To serialize asynchronus callbacks */
0341     struct mutex mutex;
0342 
0343     /* Streaming on/off */
0344     bool streaming;
0345 
0346     /* NVM data inforamtion */
0347     struct nvm_data *nvm;
0348 
0349     /* True if the device has been identified */
0350     bool identified;
0351 };
0352 
0353 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
0354 {
0355     return container_of(subdev, struct ov2740, sd);
0356 }
0357 
0358 static u64 to_pixel_rate(u32 f_index)
0359 {
0360     u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
0361 
0362     do_div(pixel_rate, OV2740_RGB_DEPTH);
0363 
0364     return pixel_rate;
0365 }
0366 
0367 static u64 to_pixels_per_line(u32 hts, u32 f_index)
0368 {
0369     u64 ppl = hts * to_pixel_rate(f_index);
0370 
0371     do_div(ppl, OV2740_SCLK);
0372 
0373     return ppl;
0374 }
0375 
0376 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
0377 {
0378     struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
0379     struct i2c_msg msgs[2];
0380     u8 addr_buf[2];
0381     u8 data_buf[4] = {0};
0382     int ret = 0;
0383 
0384     if (len > sizeof(data_buf))
0385         return -EINVAL;
0386 
0387     put_unaligned_be16(reg, addr_buf);
0388     msgs[0].addr = client->addr;
0389     msgs[0].flags = 0;
0390     msgs[0].len = sizeof(addr_buf);
0391     msgs[0].buf = addr_buf;
0392     msgs[1].addr = client->addr;
0393     msgs[1].flags = I2C_M_RD;
0394     msgs[1].len = len;
0395     msgs[1].buf = &data_buf[sizeof(data_buf) - len];
0396 
0397     ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0398     if (ret != ARRAY_SIZE(msgs))
0399         return ret < 0 ? ret : -EIO;
0400 
0401     *val = get_unaligned_be32(data_buf);
0402 
0403     return 0;
0404 }
0405 
0406 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
0407 {
0408     struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
0409     u8 buf[6];
0410     int ret = 0;
0411 
0412     if (len > 4)
0413         return -EINVAL;
0414 
0415     put_unaligned_be16(reg, buf);
0416     put_unaligned_be32(val << 8 * (4 - len), buf + 2);
0417 
0418     ret = i2c_master_send(client, buf, len + 2);
0419     if (ret != len + 2)
0420         return ret < 0 ? ret : -EIO;
0421 
0422     return 0;
0423 }
0424 
0425 static int ov2740_write_reg_list(struct ov2740 *ov2740,
0426                  const struct ov2740_reg_list *r_list)
0427 {
0428     struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
0429     unsigned int i;
0430     int ret = 0;
0431 
0432     for (i = 0; i < r_list->num_of_regs; i++) {
0433         ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
0434                        r_list->regs[i].val);
0435         if (ret) {
0436             dev_err_ratelimited(&client->dev,
0437                         "write reg 0x%4.4x return err = %d",
0438                         r_list->regs[i].address, ret);
0439             return ret;
0440         }
0441     }
0442 
0443     return 0;
0444 }
0445 
0446 static int ov2740_identify_module(struct ov2740 *ov2740)
0447 {
0448     struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
0449     int ret;
0450     u32 val;
0451 
0452     if (ov2740->identified)
0453         return 0;
0454 
0455     ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
0456     if (ret)
0457         return ret;
0458 
0459     if (val != OV2740_CHIP_ID) {
0460         dev_err(&client->dev, "chip id mismatch: %x!=%x",
0461             OV2740_CHIP_ID, val);
0462         return -ENXIO;
0463     }
0464 
0465     ov2740->identified = true;
0466 
0467     return 0;
0468 }
0469 
0470 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
0471 {
0472     int ret = 0;
0473 
0474     ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
0475                    OV2740_GROUP_HOLD_START);
0476     if (ret)
0477         return ret;
0478 
0479     ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
0480     if (ret)
0481         return ret;
0482 
0483     ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
0484     if (ret)
0485         return ret;
0486 
0487     ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
0488     if (ret)
0489         return ret;
0490 
0491     ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
0492                    OV2740_GROUP_HOLD_END);
0493     if (ret)
0494         return ret;
0495 
0496     ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
0497                    OV2740_GROUP_HOLD_LAUNCH);
0498     return ret;
0499 }
0500 
0501 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
0502 {
0503     if (pattern)
0504         pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
0505               OV2740_TEST_PATTERN_ENABLE;
0506 
0507     return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
0508 }
0509 
0510 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
0511 {
0512     struct ov2740 *ov2740 = container_of(ctrl->handler,
0513                          struct ov2740, ctrl_handler);
0514     struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
0515     s64 exposure_max;
0516     int ret = 0;
0517 
0518     /* Propagate change of current control to all related controls */
0519     if (ctrl->id == V4L2_CID_VBLANK) {
0520         /* Update max exposure while meeting expected vblanking */
0521         exposure_max = ov2740->cur_mode->height + ctrl->val -
0522                    OV2740_EXPOSURE_MAX_MARGIN;
0523         __v4l2_ctrl_modify_range(ov2740->exposure,
0524                      ov2740->exposure->minimum,
0525                      exposure_max, ov2740->exposure->step,
0526                      exposure_max);
0527     }
0528 
0529     /* V4L2 controls values will be applied only when power is already up */
0530     if (!pm_runtime_get_if_in_use(&client->dev))
0531         return 0;
0532 
0533     switch (ctrl->id) {
0534     case V4L2_CID_ANALOGUE_GAIN:
0535         ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
0536                        ctrl->val);
0537         break;
0538 
0539     case V4L2_CID_DIGITAL_GAIN:
0540         ret = ov2740_update_digital_gain(ov2740, ctrl->val);
0541         break;
0542 
0543     case V4L2_CID_EXPOSURE:
0544         /* 4 least significant bits of expsoure are fractional part */
0545         ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
0546                        ctrl->val << 4);
0547         break;
0548 
0549     case V4L2_CID_VBLANK:
0550         ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
0551                        ov2740->cur_mode->height + ctrl->val);
0552         break;
0553 
0554     case V4L2_CID_TEST_PATTERN:
0555         ret = ov2740_test_pattern(ov2740, ctrl->val);
0556         break;
0557 
0558     default:
0559         ret = -EINVAL;
0560         break;
0561     }
0562 
0563     pm_runtime_put(&client->dev);
0564 
0565     return ret;
0566 }
0567 
0568 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
0569     .s_ctrl = ov2740_set_ctrl,
0570 };
0571 
0572 static int ov2740_init_controls(struct ov2740 *ov2740)
0573 {
0574     struct v4l2_ctrl_handler *ctrl_hdlr;
0575     const struct ov2740_mode *cur_mode;
0576     s64 exposure_max, h_blank, pixel_rate;
0577     u32 vblank_min, vblank_max, vblank_default;
0578     int size;
0579     int ret = 0;
0580 
0581     ctrl_hdlr = &ov2740->ctrl_handler;
0582     ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
0583     if (ret)
0584         return ret;
0585 
0586     ctrl_hdlr->lock = &ov2740->mutex;
0587     cur_mode = ov2740->cur_mode;
0588     size = ARRAY_SIZE(link_freq_menu_items);
0589 
0590     ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
0591                            V4L2_CID_LINK_FREQ,
0592                            size - 1, 0,
0593                            link_freq_menu_items);
0594     if (ov2740->link_freq)
0595         ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0596 
0597     pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
0598     ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
0599                            V4L2_CID_PIXEL_RATE, 0,
0600                            pixel_rate, 1, pixel_rate);
0601 
0602     vblank_min = cur_mode->vts_min - cur_mode->height;
0603     vblank_max = OV2740_VTS_MAX - cur_mode->height;
0604     vblank_default = cur_mode->vts_def - cur_mode->height;
0605     ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
0606                        V4L2_CID_VBLANK, vblank_min,
0607                        vblank_max, 1, vblank_default);
0608 
0609     h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
0610     h_blank -= cur_mode->width;
0611     ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
0612                        V4L2_CID_HBLANK, h_blank, h_blank, 1,
0613                        h_blank);
0614     if (ov2740->hblank)
0615         ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0616 
0617     v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
0618               OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
0619               OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
0620     v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
0621               OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
0622               OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
0623     exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
0624     ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
0625                          V4L2_CID_EXPOSURE,
0626                          OV2740_EXPOSURE_MIN, exposure_max,
0627                          OV2740_EXPOSURE_STEP,
0628                          exposure_max);
0629     v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
0630                      V4L2_CID_TEST_PATTERN,
0631                      ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
0632                      0, 0, ov2740_test_pattern_menu);
0633     if (ctrl_hdlr->error)
0634         return ctrl_hdlr->error;
0635 
0636     ov2740->sd.ctrl_handler = ctrl_hdlr;
0637 
0638     return 0;
0639 }
0640 
0641 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
0642                      struct v4l2_mbus_framefmt *fmt)
0643 {
0644     fmt->width = mode->width;
0645     fmt->height = mode->height;
0646     fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
0647     fmt->field = V4L2_FIELD_NONE;
0648 }
0649 
0650 static int ov2740_load_otp_data(struct nvm_data *nvm)
0651 {
0652     struct i2c_client *client;
0653     struct ov2740 *ov2740;
0654     u32 isp_ctrl00 = 0;
0655     u32 isp_ctrl01 = 0;
0656     int ret;
0657 
0658     if (!nvm)
0659         return -EINVAL;
0660 
0661     if (nvm->nvm_buffer)
0662         return 0;
0663 
0664     client = nvm->client;
0665     ov2740 = to_ov2740(i2c_get_clientdata(client));
0666 
0667     nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
0668     if (!nvm->nvm_buffer)
0669         return -ENOMEM;
0670 
0671     ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
0672     if (ret) {
0673         dev_err(&client->dev, "failed to read ISP CTRL00\n");
0674         goto err;
0675     }
0676 
0677     ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
0678     if (ret) {
0679         dev_err(&client->dev, "failed to read ISP CTRL01\n");
0680         goto err;
0681     }
0682 
0683     /* Clear bit 5 of ISP CTRL00 */
0684     ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
0685                    isp_ctrl00 & ~BIT(5));
0686     if (ret) {
0687         dev_err(&client->dev, "failed to set ISP CTRL00\n");
0688         goto err;
0689     }
0690 
0691     /* Clear bit 7 of ISP CTRL01 */
0692     ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
0693                    isp_ctrl01 & ~BIT(7));
0694     if (ret) {
0695         dev_err(&client->dev, "failed to set ISP CTRL01\n");
0696         goto err;
0697     }
0698 
0699     ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
0700                    OV2740_MODE_STREAMING);
0701     if (ret) {
0702         dev_err(&client->dev, "failed to set streaming mode\n");
0703         goto err;
0704     }
0705 
0706     /*
0707      * Users are not allowed to access OTP-related registers and memory
0708      * during the 20 ms period after streaming starts (0x100 = 0x01).
0709      */
0710     msleep(20);
0711 
0712     ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
0713                    nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
0714     if (ret) {
0715         dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
0716         goto err;
0717     }
0718 
0719     ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
0720                    OV2740_MODE_STANDBY);
0721     if (ret) {
0722         dev_err(&client->dev, "failed to set streaming mode\n");
0723         goto err;
0724     }
0725 
0726     ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
0727     if (ret) {
0728         dev_err(&client->dev, "failed to set ISP CTRL01\n");
0729         goto err;
0730     }
0731 
0732     ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
0733     if (ret) {
0734         dev_err(&client->dev, "failed to set ISP CTRL00\n");
0735         goto err;
0736     }
0737 
0738     return 0;
0739 err:
0740     kfree(nvm->nvm_buffer);
0741     nvm->nvm_buffer = NULL;
0742 
0743     return ret;
0744 }
0745 
0746 static int ov2740_start_streaming(struct ov2740 *ov2740)
0747 {
0748     struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
0749     struct nvm_data *nvm = ov2740->nvm;
0750     const struct ov2740_reg_list *reg_list;
0751     int link_freq_index;
0752     int ret = 0;
0753 
0754     ret = ov2740_identify_module(ov2740);
0755     if (ret)
0756         return ret;
0757 
0758     ov2740_load_otp_data(nvm);
0759 
0760     link_freq_index = ov2740->cur_mode->link_freq_index;
0761     reg_list = &link_freq_configs[link_freq_index].reg_list;
0762     ret = ov2740_write_reg_list(ov2740, reg_list);
0763     if (ret) {
0764         dev_err(&client->dev, "failed to set plls");
0765         return ret;
0766     }
0767 
0768     reg_list = &ov2740->cur_mode->reg_list;
0769     ret = ov2740_write_reg_list(ov2740, reg_list);
0770     if (ret) {
0771         dev_err(&client->dev, "failed to set mode");
0772         return ret;
0773     }
0774 
0775     ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
0776     if (ret)
0777         return ret;
0778 
0779     ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
0780                    OV2740_MODE_STREAMING);
0781     if (ret)
0782         dev_err(&client->dev, "failed to start streaming");
0783 
0784     return ret;
0785 }
0786 
0787 static void ov2740_stop_streaming(struct ov2740 *ov2740)
0788 {
0789     struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
0790 
0791     if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
0792                  OV2740_MODE_STANDBY))
0793         dev_err(&client->dev, "failed to stop streaming");
0794 }
0795 
0796 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
0797 {
0798     struct ov2740 *ov2740 = to_ov2740(sd);
0799     struct i2c_client *client = v4l2_get_subdevdata(sd);
0800     int ret = 0;
0801 
0802     if (ov2740->streaming == enable)
0803         return 0;
0804 
0805     mutex_lock(&ov2740->mutex);
0806     if (enable) {
0807         ret = pm_runtime_resume_and_get(&client->dev);
0808         if (ret < 0) {
0809             mutex_unlock(&ov2740->mutex);
0810             return ret;
0811         }
0812 
0813         ret = ov2740_start_streaming(ov2740);
0814         if (ret) {
0815             enable = 0;
0816             ov2740_stop_streaming(ov2740);
0817             pm_runtime_put(&client->dev);
0818         }
0819     } else {
0820         ov2740_stop_streaming(ov2740);
0821         pm_runtime_put(&client->dev);
0822     }
0823 
0824     ov2740->streaming = enable;
0825     mutex_unlock(&ov2740->mutex);
0826 
0827     return ret;
0828 }
0829 
0830 static int __maybe_unused ov2740_suspend(struct device *dev)
0831 {
0832     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0833     struct ov2740 *ov2740 = to_ov2740(sd);
0834 
0835     mutex_lock(&ov2740->mutex);
0836     if (ov2740->streaming)
0837         ov2740_stop_streaming(ov2740);
0838 
0839     mutex_unlock(&ov2740->mutex);
0840 
0841     return 0;
0842 }
0843 
0844 static int __maybe_unused ov2740_resume(struct device *dev)
0845 {
0846     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0847     struct ov2740 *ov2740 = to_ov2740(sd);
0848     int ret = 0;
0849 
0850     mutex_lock(&ov2740->mutex);
0851     if (!ov2740->streaming)
0852         goto exit;
0853 
0854     ret = ov2740_start_streaming(ov2740);
0855     if (ret) {
0856         ov2740->streaming = false;
0857         ov2740_stop_streaming(ov2740);
0858     }
0859 
0860 exit:
0861     mutex_unlock(&ov2740->mutex);
0862     return ret;
0863 }
0864 
0865 static int ov2740_set_format(struct v4l2_subdev *sd,
0866                  struct v4l2_subdev_state *sd_state,
0867                  struct v4l2_subdev_format *fmt)
0868 {
0869     struct ov2740 *ov2740 = to_ov2740(sd);
0870     const struct ov2740_mode *mode;
0871     s32 vblank_def, h_blank;
0872 
0873     mode = v4l2_find_nearest_size(supported_modes,
0874                       ARRAY_SIZE(supported_modes), width,
0875                       height, fmt->format.width,
0876                       fmt->format.height);
0877 
0878     mutex_lock(&ov2740->mutex);
0879     ov2740_update_pad_format(mode, &fmt->format);
0880     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0881         *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
0882     } else {
0883         ov2740->cur_mode = mode;
0884         __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
0885         __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
0886                      to_pixel_rate(mode->link_freq_index));
0887 
0888         /* Update limits and set FPS to default */
0889         vblank_def = mode->vts_def - mode->height;
0890         __v4l2_ctrl_modify_range(ov2740->vblank,
0891                      mode->vts_min - mode->height,
0892                      OV2740_VTS_MAX - mode->height, 1,
0893                      vblank_def);
0894         __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
0895         h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
0896               mode->width;
0897         __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
0898                      h_blank);
0899     }
0900     mutex_unlock(&ov2740->mutex);
0901 
0902     return 0;
0903 }
0904 
0905 static int ov2740_get_format(struct v4l2_subdev *sd,
0906                  struct v4l2_subdev_state *sd_state,
0907                  struct v4l2_subdev_format *fmt)
0908 {
0909     struct ov2740 *ov2740 = to_ov2740(sd);
0910 
0911     mutex_lock(&ov2740->mutex);
0912     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
0913         fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd,
0914                               sd_state,
0915                               fmt->pad);
0916     else
0917         ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
0918 
0919     mutex_unlock(&ov2740->mutex);
0920 
0921     return 0;
0922 }
0923 
0924 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
0925                  struct v4l2_subdev_state *sd_state,
0926                  struct v4l2_subdev_mbus_code_enum *code)
0927 {
0928     if (code->index > 0)
0929         return -EINVAL;
0930 
0931     code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
0932 
0933     return 0;
0934 }
0935 
0936 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
0937                   struct v4l2_subdev_state *sd_state,
0938                   struct v4l2_subdev_frame_size_enum *fse)
0939 {
0940     if (fse->index >= ARRAY_SIZE(supported_modes))
0941         return -EINVAL;
0942 
0943     if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
0944         return -EINVAL;
0945 
0946     fse->min_width = supported_modes[fse->index].width;
0947     fse->max_width = fse->min_width;
0948     fse->min_height = supported_modes[fse->index].height;
0949     fse->max_height = fse->min_height;
0950 
0951     return 0;
0952 }
0953 
0954 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
0955 {
0956     struct ov2740 *ov2740 = to_ov2740(sd);
0957 
0958     mutex_lock(&ov2740->mutex);
0959     ov2740_update_pad_format(&supported_modes[0],
0960                  v4l2_subdev_get_try_format(sd, fh->state, 0));
0961     mutex_unlock(&ov2740->mutex);
0962 
0963     return 0;
0964 }
0965 
0966 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
0967     .s_stream = ov2740_set_stream,
0968 };
0969 
0970 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
0971     .set_fmt = ov2740_set_format,
0972     .get_fmt = ov2740_get_format,
0973     .enum_mbus_code = ov2740_enum_mbus_code,
0974     .enum_frame_size = ov2740_enum_frame_size,
0975 };
0976 
0977 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
0978     .video = &ov2740_video_ops,
0979     .pad = &ov2740_pad_ops,
0980 };
0981 
0982 static const struct media_entity_operations ov2740_subdev_entity_ops = {
0983     .link_validate = v4l2_subdev_link_validate,
0984 };
0985 
0986 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
0987     .open = ov2740_open,
0988 };
0989 
0990 static int ov2740_check_hwcfg(struct device *dev)
0991 {
0992     struct fwnode_handle *ep;
0993     struct fwnode_handle *fwnode = dev_fwnode(dev);
0994     struct v4l2_fwnode_endpoint bus_cfg = {
0995         .bus_type = V4L2_MBUS_CSI2_DPHY
0996     };
0997     u32 mclk;
0998     int ret;
0999     unsigned int i, j;
1000 
1001     if (!fwnode)
1002         return -ENXIO;
1003 
1004     ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
1005     if (ret)
1006         return ret;
1007 
1008     if (mclk != OV2740_MCLK) {
1009         dev_err(dev, "external clock %d is not supported", mclk);
1010         return -EINVAL;
1011     }
1012 
1013     ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1014     if (!ep)
1015         return -ENXIO;
1016 
1017     ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1018     fwnode_handle_put(ep);
1019     if (ret)
1020         return ret;
1021 
1022     if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
1023         dev_err(dev, "number of CSI2 data lanes %d is not supported",
1024             bus_cfg.bus.mipi_csi2.num_data_lanes);
1025         ret = -EINVAL;
1026         goto check_hwcfg_error;
1027     }
1028 
1029     if (!bus_cfg.nr_of_link_frequencies) {
1030         dev_err(dev, "no link frequencies defined");
1031         ret = -EINVAL;
1032         goto check_hwcfg_error;
1033     }
1034 
1035     for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1036         for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1037             if (link_freq_menu_items[i] ==
1038                 bus_cfg.link_frequencies[j])
1039                 break;
1040         }
1041 
1042         if (j == bus_cfg.nr_of_link_frequencies) {
1043             dev_err(dev, "no link frequency %lld supported",
1044                 link_freq_menu_items[i]);
1045             ret = -EINVAL;
1046             goto check_hwcfg_error;
1047         }
1048     }
1049 
1050 check_hwcfg_error:
1051     v4l2_fwnode_endpoint_free(&bus_cfg);
1052 
1053     return ret;
1054 }
1055 
1056 static int ov2740_remove(struct i2c_client *client)
1057 {
1058     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1059     struct ov2740 *ov2740 = to_ov2740(sd);
1060 
1061     v4l2_async_unregister_subdev(sd);
1062     media_entity_cleanup(&sd->entity);
1063     v4l2_ctrl_handler_free(sd->ctrl_handler);
1064     pm_runtime_disable(&client->dev);
1065     mutex_destroy(&ov2740->mutex);
1066 
1067     return 0;
1068 }
1069 
1070 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1071                  size_t count)
1072 {
1073     struct nvm_data *nvm = priv;
1074     struct v4l2_subdev *sd = i2c_get_clientdata(nvm->client);
1075     struct device *dev = &nvm->client->dev;
1076     struct ov2740 *ov2740 = to_ov2740(sd);
1077     int ret = 0;
1078 
1079     mutex_lock(&ov2740->mutex);
1080 
1081     if (nvm->nvm_buffer) {
1082         memcpy(val, nvm->nvm_buffer + off, count);
1083         goto exit;
1084     }
1085 
1086     ret = pm_runtime_resume_and_get(dev);
1087     if (ret < 0) {
1088         goto exit;
1089     }
1090 
1091     ret = ov2740_load_otp_data(nvm);
1092     if (!ret)
1093         memcpy(val, nvm->nvm_buffer + off, count);
1094 
1095     pm_runtime_put(dev);
1096 exit:
1097     mutex_unlock(&ov2740->mutex);
1098     return ret;
1099 }
1100 
1101 static int ov2740_register_nvmem(struct i2c_client *client,
1102                  struct ov2740 *ov2740)
1103 {
1104     struct nvm_data *nvm;
1105     struct regmap_config regmap_config = { };
1106     struct nvmem_config nvmem_config = { };
1107     struct regmap *regmap;
1108     struct device *dev = &client->dev;
1109     int ret;
1110 
1111     nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1112     if (!nvm)
1113         return -ENOMEM;
1114 
1115     regmap_config.val_bits = 8;
1116     regmap_config.reg_bits = 16;
1117     regmap_config.disable_locking = true;
1118     regmap = devm_regmap_init_i2c(client, &regmap_config);
1119     if (IS_ERR(regmap))
1120         return PTR_ERR(regmap);
1121 
1122     nvm->regmap = regmap;
1123     nvm->client = client;
1124 
1125     nvmem_config.name = dev_name(dev);
1126     nvmem_config.dev = dev;
1127     nvmem_config.read_only = true;
1128     nvmem_config.root_only = true;
1129     nvmem_config.owner = THIS_MODULE;
1130     nvmem_config.compat = true;
1131     nvmem_config.base_dev = dev;
1132     nvmem_config.reg_read = ov2740_nvmem_read;
1133     nvmem_config.reg_write = NULL;
1134     nvmem_config.priv = nvm;
1135     nvmem_config.stride = 1;
1136     nvmem_config.word_size = 1;
1137     nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1138 
1139     nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1140 
1141     ret = PTR_ERR_OR_ZERO(nvm->nvmem);
1142     if (!ret)
1143         ov2740->nvm = nvm;
1144 
1145     return ret;
1146 }
1147 
1148 static int ov2740_probe(struct i2c_client *client)
1149 {
1150     struct ov2740 *ov2740;
1151     int ret = 0;
1152     bool full_power;
1153 
1154     ret = ov2740_check_hwcfg(&client->dev);
1155     if (ret) {
1156         dev_err(&client->dev, "failed to check HW configuration: %d",
1157             ret);
1158         return ret;
1159     }
1160 
1161     ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1162     if (!ov2740)
1163         return -ENOMEM;
1164 
1165     v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1166     full_power = acpi_dev_state_d0(&client->dev);
1167     if (full_power) {
1168         ret = ov2740_identify_module(ov2740);
1169         if (ret) {
1170             dev_err(&client->dev, "failed to find sensor: %d", ret);
1171             return ret;
1172         }
1173     }
1174 
1175     mutex_init(&ov2740->mutex);
1176     ov2740->cur_mode = &supported_modes[0];
1177     ret = ov2740_init_controls(ov2740);
1178     if (ret) {
1179         dev_err(&client->dev, "failed to init controls: %d", ret);
1180         goto probe_error_v4l2_ctrl_handler_free;
1181     }
1182 
1183     ov2740->sd.internal_ops = &ov2740_internal_ops;
1184     ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1185     ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1186     ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1187     ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1188     ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1189     if (ret) {
1190         dev_err(&client->dev, "failed to init entity pads: %d", ret);
1191         goto probe_error_v4l2_ctrl_handler_free;
1192     }
1193 
1194     ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1195     if (ret < 0) {
1196         dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1197             ret);
1198         goto probe_error_media_entity_cleanup;
1199     }
1200 
1201     ret = ov2740_register_nvmem(client, ov2740);
1202     if (ret)
1203         dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1204 
1205     /* Set the device's state to active if it's in D0 state. */
1206     if (full_power)
1207         pm_runtime_set_active(&client->dev);
1208     pm_runtime_enable(&client->dev);
1209     pm_runtime_idle(&client->dev);
1210 
1211     return 0;
1212 
1213 probe_error_media_entity_cleanup:
1214     media_entity_cleanup(&ov2740->sd.entity);
1215 
1216 probe_error_v4l2_ctrl_handler_free:
1217     v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1218     mutex_destroy(&ov2740->mutex);
1219 
1220     return ret;
1221 }
1222 
1223 static const struct dev_pm_ops ov2740_pm_ops = {
1224     SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume)
1225 };
1226 
1227 static const struct acpi_device_id ov2740_acpi_ids[] = {
1228     {"INT3474"},
1229     {}
1230 };
1231 
1232 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1233 
1234 static struct i2c_driver ov2740_i2c_driver = {
1235     .driver = {
1236         .name = "ov2740",
1237         .pm = &ov2740_pm_ops,
1238         .acpi_match_table = ov2740_acpi_ids,
1239     },
1240     .probe_new = ov2740_probe,
1241     .remove = ov2740_remove,
1242     .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1243 };
1244 
1245 module_i2c_driver(ov2740_i2c_driver);
1246 
1247 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1248 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1249 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1250 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1251 MODULE_LICENSE("GPL v2");
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