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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ov2685 driver
0004  *
0005  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/delay.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/i2c.h>
0013 #include <linux/module.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/sysfs.h>
0017 #include <media/media-entity.h>
0018 #include <media/v4l2-async.h>
0019 #include <media/v4l2-ctrls.h>
0020 #include <media/v4l2-subdev.h>
0021 
0022 #define CHIP_ID             0x2685
0023 #define OV2685_REG_CHIP_ID      0x300a
0024 
0025 #define OV2685_XVCLK_FREQ       24000000
0026 
0027 #define REG_SC_CTRL_MODE        0x0100
0028 #define     SC_CTRL_MODE_STANDBY    0x0
0029 #define     SC_CTRL_MODE_STREAMING  BIT(0)
0030 
0031 #define OV2685_REG_EXPOSURE     0x3500
0032 #define OV2685_EXPOSURE_MIN     4
0033 #define OV2685_EXPOSURE_STEP        1
0034 
0035 #define OV2685_REG_VTS          0x380e
0036 #define OV2685_VTS_MAX          0x7fff
0037 
0038 #define OV2685_REG_GAIN         0x350a
0039 #define OV2685_GAIN_MIN         0
0040 #define OV2685_GAIN_MAX         0x07ff
0041 #define OV2685_GAIN_STEP        0x1
0042 #define OV2685_GAIN_DEFAULT     0x0036
0043 
0044 #define OV2685_REG_TEST_PATTERN     0x5080
0045 #define OV2685_TEST_PATTERN_DISABLED        0x00
0046 #define OV2685_TEST_PATTERN_COLOR_BAR       0x80
0047 #define OV2685_TEST_PATTERN_RANDOM      0x81
0048 #define OV2685_TEST_PATTERN_COLOR_BAR_FADE  0x88
0049 #define OV2685_TEST_PATTERN_BW_SQUARE       0x92
0050 #define OV2685_TEST_PATTERN_COLOR_SQUARE    0x82
0051 
0052 #define REG_NULL            0xFFFF
0053 
0054 #define OV2685_REG_VALUE_08BIT      1
0055 #define OV2685_REG_VALUE_16BIT      2
0056 #define OV2685_REG_VALUE_24BIT      3
0057 
0058 #define OV2685_LANES            1
0059 #define OV2685_BITS_PER_SAMPLE      10
0060 
0061 static const char * const ov2685_supply_names[] = {
0062     "avdd",     /* Analog power */
0063     "dovdd",    /* Digital I/O power */
0064     "dvdd",     /* Digital core power */
0065 };
0066 
0067 #define OV2685_NUM_SUPPLIES ARRAY_SIZE(ov2685_supply_names)
0068 
0069 struct regval {
0070     u16 addr;
0071     u8 val;
0072 };
0073 
0074 struct ov2685_mode {
0075     u32 width;
0076     u32 height;
0077     u32 exp_def;
0078     u32 hts_def;
0079     u32 vts_def;
0080     const struct regval *reg_list;
0081 };
0082 
0083 struct ov2685 {
0084     struct i2c_client   *client;
0085     struct clk      *xvclk;
0086     struct gpio_desc    *reset_gpio;
0087     struct regulator_bulk_data supplies[OV2685_NUM_SUPPLIES];
0088 
0089     bool            streaming;
0090     struct mutex        mutex;
0091     struct v4l2_subdev  subdev;
0092     struct media_pad    pad;
0093     struct v4l2_ctrl    *anal_gain;
0094     struct v4l2_ctrl    *exposure;
0095     struct v4l2_ctrl    *hblank;
0096     struct v4l2_ctrl    *vblank;
0097     struct v4l2_ctrl    *test_pattern;
0098     struct v4l2_ctrl_handler ctrl_handler;
0099 
0100     const struct ov2685_mode *cur_mode;
0101 };
0102 
0103 #define to_ov2685(sd) container_of(sd, struct ov2685, subdev)
0104 
0105 /* PLL settings bases on 24M xvclk */
0106 static struct regval ov2685_1600x1200_regs[] = {
0107     {0x0103, 0x01},
0108     {0x0100, 0x00},
0109     {0x3002, 0x00},
0110     {0x3016, 0x1c},
0111     {0x3018, 0x44},
0112     {0x301d, 0xf0},
0113     {0x3020, 0x00},
0114     {0x3082, 0x37},
0115     {0x3083, 0x03},
0116     {0x3084, 0x09},
0117     {0x3085, 0x04},
0118     {0x3086, 0x00},
0119     {0x3087, 0x00},
0120     {0x3501, 0x4e},
0121     {0x3502, 0xe0},
0122     {0x3503, 0x27},
0123     {0x350b, 0x36},
0124     {0x3600, 0xb4},
0125     {0x3603, 0x35},
0126     {0x3604, 0x24},
0127     {0x3605, 0x00},
0128     {0x3620, 0x24},
0129     {0x3621, 0x34},
0130     {0x3622, 0x03},
0131     {0x3628, 0x10},
0132     {0x3705, 0x3c},
0133     {0x370a, 0x21},
0134     {0x370c, 0x50},
0135     {0x370d, 0xc0},
0136     {0x3717, 0x58},
0137     {0x3718, 0x80},
0138     {0x3720, 0x00},
0139     {0x3721, 0x09},
0140     {0x3722, 0x06},
0141     {0x3723, 0x59},
0142     {0x3738, 0x99},
0143     {0x3781, 0x80},
0144     {0x3784, 0x0c},
0145     {0x3789, 0x60},
0146     {0x3800, 0x00},
0147     {0x3801, 0x00},
0148     {0x3802, 0x00},
0149     {0x3803, 0x00},
0150     {0x3804, 0x06},
0151     {0x3805, 0x4f},
0152     {0x3806, 0x04},
0153     {0x3807, 0xbf},
0154     {0x3808, 0x06},
0155     {0x3809, 0x40},
0156     {0x380a, 0x04},
0157     {0x380b, 0xb0},
0158     {0x380c, 0x06},
0159     {0x380d, 0xa4},
0160     {0x380e, 0x05},
0161     {0x380f, 0x0e},
0162     {0x3810, 0x00},
0163     {0x3811, 0x08},
0164     {0x3812, 0x00},
0165     {0x3813, 0x08},
0166     {0x3814, 0x11},
0167     {0x3815, 0x11},
0168     {0x3819, 0x04},
0169     {0x3820, 0xc0},
0170     {0x3821, 0x00},
0171     {0x3a06, 0x01},
0172     {0x3a07, 0x84},
0173     {0x3a08, 0x01},
0174     {0x3a09, 0x43},
0175     {0x3a0a, 0x24},
0176     {0x3a0b, 0x60},
0177     {0x3a0c, 0x28},
0178     {0x3a0d, 0x60},
0179     {0x3a0e, 0x04},
0180     {0x3a0f, 0x8c},
0181     {0x3a10, 0x05},
0182     {0x3a11, 0x0c},
0183     {0x4000, 0x81},
0184     {0x4001, 0x40},
0185     {0x4008, 0x02},
0186     {0x4009, 0x09},
0187     {0x4300, 0x00},
0188     {0x430e, 0x00},
0189     {0x4602, 0x02},
0190     {0x481b, 0x40},
0191     {0x481f, 0x40},
0192     {0x4837, 0x18},
0193     {0x5000, 0x1f},
0194     {0x5001, 0x05},
0195     {0x5002, 0x30},
0196     {0x5003, 0x04},
0197     {0x5004, 0x00},
0198     {0x5005, 0x0c},
0199     {0x5280, 0x15},
0200     {0x5281, 0x06},
0201     {0x5282, 0x06},
0202     {0x5283, 0x08},
0203     {0x5284, 0x1c},
0204     {0x5285, 0x1c},
0205     {0x5286, 0x20},
0206     {0x5287, 0x10},
0207     {REG_NULL, 0x00}
0208 };
0209 
0210 #define OV2685_LINK_FREQ_330MHZ     330000000
0211 static const s64 link_freq_menu_items[] = {
0212     OV2685_LINK_FREQ_330MHZ
0213 };
0214 
0215 static const char * const ov2685_test_pattern_menu[] = {
0216     "Disabled",
0217     "Color Bar",
0218     "Color Bar FADE",
0219     "Random Data",
0220     "Black White Square",
0221     "Color Square"
0222 };
0223 
0224 static const int ov2685_test_pattern_val[] = {
0225     OV2685_TEST_PATTERN_DISABLED,
0226     OV2685_TEST_PATTERN_COLOR_BAR,
0227     OV2685_TEST_PATTERN_COLOR_BAR_FADE,
0228     OV2685_TEST_PATTERN_RANDOM,
0229     OV2685_TEST_PATTERN_BW_SQUARE,
0230     OV2685_TEST_PATTERN_COLOR_SQUARE,
0231 };
0232 
0233 static const struct ov2685_mode supported_modes[] = {
0234     {
0235         .width = 1600,
0236         .height = 1200,
0237         .exp_def = 0x04ee,
0238         .hts_def = 0x06a4,
0239         .vts_def = 0x050e,
0240         .reg_list = ov2685_1600x1200_regs,
0241     },
0242 };
0243 
0244 /* Write registers up to 4 at a time */
0245 static int ov2685_write_reg(struct i2c_client *client, u16 reg,
0246                 u32 len, u32 val)
0247 {
0248     u32 val_i, buf_i;
0249     u8 buf[6];
0250     u8 *val_p;
0251     __be32 val_be;
0252 
0253     if (len > 4)
0254         return -EINVAL;
0255 
0256     buf[0] = reg >> 8;
0257     buf[1] = reg & 0xff;
0258 
0259     val_be = cpu_to_be32(val);
0260     val_p = (u8 *)&val_be;
0261     buf_i = 2;
0262     val_i = 4 - len;
0263 
0264     while (val_i < 4)
0265         buf[buf_i++] = val_p[val_i++];
0266 
0267     if (i2c_master_send(client, buf, len + 2) != len + 2)
0268         return -EIO;
0269 
0270     return 0;
0271 }
0272 
0273 static int ov2685_write_array(struct i2c_client *client,
0274                   const struct regval *regs)
0275 {
0276     int ret = 0;
0277     u32 i;
0278 
0279     for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
0280         ret = ov2685_write_reg(client, regs[i].addr,
0281                        OV2685_REG_VALUE_08BIT, regs[i].val);
0282 
0283     return ret;
0284 }
0285 
0286 /* Read registers up to 4 at a time */
0287 static int ov2685_read_reg(struct i2c_client *client, u16 reg,
0288                u32 len, u32 *val)
0289 {
0290     struct i2c_msg msgs[2];
0291     u8 *data_be_p;
0292     __be32 data_be = 0;
0293     __be16 reg_addr_be = cpu_to_be16(reg);
0294     int ret;
0295 
0296     if (len > 4)
0297         return -EINVAL;
0298 
0299     data_be_p = (u8 *)&data_be;
0300     /* Write register address */
0301     msgs[0].addr = client->addr;
0302     msgs[0].flags = 0;
0303     msgs[0].len = 2;
0304     msgs[0].buf = (u8 *)&reg_addr_be;
0305 
0306     /* Read data from register */
0307     msgs[1].addr = client->addr;
0308     msgs[1].flags = I2C_M_RD;
0309     msgs[1].len = len;
0310     msgs[1].buf = &data_be_p[4 - len];
0311 
0312     ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0313     if (ret != ARRAY_SIZE(msgs))
0314         return -EIO;
0315 
0316     *val = be32_to_cpu(data_be);
0317 
0318     return 0;
0319 }
0320 
0321 static void ov2685_fill_fmt(const struct ov2685_mode *mode,
0322                 struct v4l2_mbus_framefmt *fmt)
0323 {
0324     fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
0325     fmt->width = mode->width;
0326     fmt->height = mode->height;
0327     fmt->field = V4L2_FIELD_NONE;
0328 }
0329 
0330 static int ov2685_set_fmt(struct v4l2_subdev *sd,
0331               struct v4l2_subdev_state *sd_state,
0332               struct v4l2_subdev_format *fmt)
0333 {
0334     struct ov2685 *ov2685 = to_ov2685(sd);
0335     struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
0336 
0337     /* only one mode supported for now */
0338     ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
0339 
0340     return 0;
0341 }
0342 
0343 static int ov2685_get_fmt(struct v4l2_subdev *sd,
0344               struct v4l2_subdev_state *sd_state,
0345               struct v4l2_subdev_format *fmt)
0346 {
0347     struct ov2685 *ov2685 = to_ov2685(sd);
0348     struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
0349 
0350     ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
0351 
0352     return 0;
0353 }
0354 
0355 static int ov2685_enum_mbus_code(struct v4l2_subdev *sd,
0356                  struct v4l2_subdev_state *sd_state,
0357                  struct v4l2_subdev_mbus_code_enum *code)
0358 {
0359     if (code->index >= ARRAY_SIZE(supported_modes))
0360         return -EINVAL;
0361 
0362     code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
0363 
0364     return 0;
0365 }
0366 
0367 static int ov2685_enum_frame_sizes(struct v4l2_subdev *sd,
0368                    struct v4l2_subdev_state *sd_state,
0369                    struct v4l2_subdev_frame_size_enum *fse)
0370 {
0371     int index = fse->index;
0372 
0373     if (index >= ARRAY_SIZE(supported_modes))
0374         return -EINVAL;
0375 
0376     fse->code = MEDIA_BUS_FMT_SBGGR10_1X10;
0377 
0378     fse->min_width  = supported_modes[index].width;
0379     fse->max_width  = supported_modes[index].width;
0380     fse->max_height = supported_modes[index].height;
0381     fse->min_height = supported_modes[index].height;
0382 
0383     return 0;
0384 }
0385 
0386 /* Calculate the delay in us by clock rate and clock cycles */
0387 static inline u32 ov2685_cal_delay(u32 cycles)
0388 {
0389     return DIV_ROUND_UP(cycles, OV2685_XVCLK_FREQ / 1000 / 1000);
0390 }
0391 
0392 static int __ov2685_power_on(struct ov2685 *ov2685)
0393 {
0394     int ret;
0395     u32 delay_us;
0396     struct device *dev = &ov2685->client->dev;
0397 
0398     ret = clk_prepare_enable(ov2685->xvclk);
0399     if (ret < 0) {
0400         dev_err(dev, "Failed to enable xvclk\n");
0401         return ret;
0402     }
0403 
0404     gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
0405 
0406     ret = regulator_bulk_enable(OV2685_NUM_SUPPLIES, ov2685->supplies);
0407     if (ret < 0) {
0408         dev_err(dev, "Failed to enable regulators\n");
0409         goto disable_clk;
0410     }
0411 
0412     /* The minimum delay between power supplies and reset rising can be 0 */
0413     gpiod_set_value_cansleep(ov2685->reset_gpio, 0);
0414     /* 8192 xvclk cycles prior to the first SCCB transaction */
0415     delay_us = ov2685_cal_delay(8192);
0416     usleep_range(delay_us, delay_us * 2);
0417 
0418     /* HACK: ov2685 would output messy data after reset(R0103),
0419      * writing register before .s_stream() as a workaround
0420      */
0421     ret = ov2685_write_array(ov2685->client, ov2685->cur_mode->reg_list);
0422     if (ret)
0423         goto disable_supplies;
0424 
0425     return 0;
0426 
0427 disable_supplies:
0428     regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
0429 disable_clk:
0430     clk_disable_unprepare(ov2685->xvclk);
0431 
0432     return ret;
0433 }
0434 
0435 static void __ov2685_power_off(struct ov2685 *ov2685)
0436 {
0437     /* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */
0438     u32 delay_us = ov2685_cal_delay(512);
0439 
0440     usleep_range(delay_us, delay_us * 2);
0441     clk_disable_unprepare(ov2685->xvclk);
0442     gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
0443     regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
0444 }
0445 
0446 static int ov2685_s_stream(struct v4l2_subdev *sd, int on)
0447 {
0448     struct ov2685 *ov2685 = to_ov2685(sd);
0449     struct i2c_client *client = ov2685->client;
0450     int ret = 0;
0451 
0452     mutex_lock(&ov2685->mutex);
0453 
0454     on = !!on;
0455     if (on == ov2685->streaming)
0456         goto unlock_and_return;
0457 
0458     if (on) {
0459         ret = pm_runtime_resume_and_get(&ov2685->client->dev);
0460         if (ret < 0)
0461             goto unlock_and_return;
0462 
0463         ret = __v4l2_ctrl_handler_setup(&ov2685->ctrl_handler);
0464         if (ret) {
0465             pm_runtime_put(&client->dev);
0466             goto unlock_and_return;
0467         }
0468         ret = ov2685_write_reg(client, REG_SC_CTRL_MODE,
0469                 OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STREAMING);
0470         if (ret) {
0471             pm_runtime_put(&client->dev);
0472             goto unlock_and_return;
0473         }
0474     } else {
0475         ov2685_write_reg(client, REG_SC_CTRL_MODE,
0476                 OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STANDBY);
0477         pm_runtime_put(&ov2685->client->dev);
0478     }
0479 
0480     ov2685->streaming = on;
0481 
0482 unlock_and_return:
0483     mutex_unlock(&ov2685->mutex);
0484 
0485     return ret;
0486 }
0487 
0488 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
0489 static int ov2685_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
0490 {
0491     struct ov2685 *ov2685 = to_ov2685(sd);
0492     struct v4l2_mbus_framefmt *try_fmt;
0493 
0494     mutex_lock(&ov2685->mutex);
0495 
0496     try_fmt = v4l2_subdev_get_try_format(sd, fh->state, 0);
0497     /* Initialize try_fmt */
0498     ov2685_fill_fmt(&supported_modes[0], try_fmt);
0499 
0500     mutex_unlock(&ov2685->mutex);
0501 
0502     return 0;
0503 }
0504 #endif
0505 
0506 static int __maybe_unused ov2685_runtime_resume(struct device *dev)
0507 {
0508     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0509     struct ov2685 *ov2685 = to_ov2685(sd);
0510 
0511     return __ov2685_power_on(ov2685);
0512 }
0513 
0514 static int __maybe_unused ov2685_runtime_suspend(struct device *dev)
0515 {
0516     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0517     struct ov2685 *ov2685 = to_ov2685(sd);
0518 
0519     __ov2685_power_off(ov2685);
0520 
0521     return 0;
0522 }
0523 
0524 static const struct dev_pm_ops ov2685_pm_ops = {
0525     SET_RUNTIME_PM_OPS(ov2685_runtime_suspend,
0526                ov2685_runtime_resume, NULL)
0527 };
0528 
0529 static int ov2685_set_ctrl(struct v4l2_ctrl *ctrl)
0530 {
0531     struct ov2685 *ov2685 = container_of(ctrl->handler,
0532                          struct ov2685, ctrl_handler);
0533     struct i2c_client *client = ov2685->client;
0534     s64 max_expo;
0535     int ret;
0536 
0537     /* Propagate change of current control to all related controls */
0538     switch (ctrl->id) {
0539     case V4L2_CID_VBLANK:
0540         /* Update max exposure while meeting expected vblanking */
0541         max_expo = ov2685->cur_mode->height + ctrl->val - 4;
0542         __v4l2_ctrl_modify_range(ov2685->exposure,
0543                      ov2685->exposure->minimum, max_expo,
0544                      ov2685->exposure->step,
0545                      ov2685->exposure->default_value);
0546         break;
0547     }
0548 
0549     if (!pm_runtime_get_if_in_use(&client->dev))
0550         return 0;
0551 
0552     switch (ctrl->id) {
0553     case V4L2_CID_EXPOSURE:
0554         ret = ov2685_write_reg(ov2685->client, OV2685_REG_EXPOSURE,
0555                        OV2685_REG_VALUE_24BIT, ctrl->val << 4);
0556         break;
0557     case V4L2_CID_ANALOGUE_GAIN:
0558         ret = ov2685_write_reg(ov2685->client, OV2685_REG_GAIN,
0559                        OV2685_REG_VALUE_16BIT, ctrl->val);
0560         break;
0561     case V4L2_CID_VBLANK:
0562         ret = ov2685_write_reg(ov2685->client, OV2685_REG_VTS,
0563                        OV2685_REG_VALUE_16BIT,
0564                        ctrl->val + ov2685->cur_mode->height);
0565         break;
0566     case V4L2_CID_TEST_PATTERN:
0567         ret = ov2685_write_reg(ov2685->client, OV2685_REG_TEST_PATTERN,
0568                        OV2685_REG_VALUE_08BIT,
0569                        ov2685_test_pattern_val[ctrl->val]);
0570         break;
0571     default:
0572         dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
0573              __func__, ctrl->id, ctrl->val);
0574         ret = -EINVAL;
0575         break;
0576     }
0577 
0578     pm_runtime_put(&client->dev);
0579 
0580     return ret;
0581 }
0582 
0583 static const struct v4l2_subdev_video_ops ov2685_video_ops = {
0584     .s_stream = ov2685_s_stream,
0585 };
0586 
0587 static const struct v4l2_subdev_pad_ops ov2685_pad_ops = {
0588     .enum_mbus_code = ov2685_enum_mbus_code,
0589     .enum_frame_size = ov2685_enum_frame_sizes,
0590     .get_fmt = ov2685_get_fmt,
0591     .set_fmt = ov2685_set_fmt,
0592 };
0593 
0594 static const struct v4l2_subdev_ops ov2685_subdev_ops = {
0595     .video  = &ov2685_video_ops,
0596     .pad    = &ov2685_pad_ops,
0597 };
0598 
0599 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
0600 static const struct v4l2_subdev_internal_ops ov2685_internal_ops = {
0601     .open = ov2685_open,
0602 };
0603 #endif
0604 
0605 static const struct v4l2_ctrl_ops ov2685_ctrl_ops = {
0606     .s_ctrl = ov2685_set_ctrl,
0607 };
0608 
0609 static int ov2685_initialize_controls(struct ov2685 *ov2685)
0610 {
0611     const struct ov2685_mode *mode;
0612     struct v4l2_ctrl_handler *handler;
0613     struct v4l2_ctrl *ctrl;
0614     u64 exposure_max;
0615     u32 pixel_rate, h_blank;
0616     int ret;
0617 
0618     handler = &ov2685->ctrl_handler;
0619     mode = ov2685->cur_mode;
0620     ret = v4l2_ctrl_handler_init(handler, 8);
0621     if (ret)
0622         return ret;
0623     handler->lock = &ov2685->mutex;
0624 
0625     ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
0626                       0, 0, link_freq_menu_items);
0627     if (ctrl)
0628         ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0629 
0630     pixel_rate = (link_freq_menu_items[0] * 2 * OV2685_LANES) /
0631              OV2685_BITS_PER_SAMPLE;
0632     v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
0633               0, pixel_rate, 1, pixel_rate);
0634 
0635     h_blank = mode->hts_def - mode->width;
0636     ov2685->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
0637                 h_blank, h_blank, 1, h_blank);
0638     if (ov2685->hblank)
0639         ov2685->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0640 
0641     ov2685->vblank = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
0642                 V4L2_CID_VBLANK, mode->vts_def - mode->height,
0643                 OV2685_VTS_MAX - mode->height, 1,
0644                 mode->vts_def - mode->height);
0645 
0646     exposure_max = mode->vts_def - 4;
0647     ov2685->exposure = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
0648                 V4L2_CID_EXPOSURE, OV2685_EXPOSURE_MIN,
0649                 exposure_max, OV2685_EXPOSURE_STEP,
0650                 mode->exp_def);
0651 
0652     ov2685->anal_gain = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
0653                 V4L2_CID_ANALOGUE_GAIN, OV2685_GAIN_MIN,
0654                 OV2685_GAIN_MAX, OV2685_GAIN_STEP,
0655                 OV2685_GAIN_DEFAULT);
0656 
0657     ov2685->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
0658                 &ov2685_ctrl_ops, V4L2_CID_TEST_PATTERN,
0659                 ARRAY_SIZE(ov2685_test_pattern_menu) - 1,
0660                 0, 0, ov2685_test_pattern_menu);
0661 
0662     if (handler->error) {
0663         ret = handler->error;
0664         dev_err(&ov2685->client->dev,
0665             "Failed to init controls(%d)\n", ret);
0666         goto err_free_handler;
0667     }
0668 
0669     ov2685->subdev.ctrl_handler = handler;
0670 
0671     return 0;
0672 
0673 err_free_handler:
0674     v4l2_ctrl_handler_free(handler);
0675 
0676     return ret;
0677 }
0678 
0679 static int ov2685_check_sensor_id(struct ov2685 *ov2685,
0680                   struct i2c_client *client)
0681 {
0682     struct device *dev = &ov2685->client->dev;
0683     int ret;
0684     u32 id = 0;
0685 
0686     ret = ov2685_read_reg(client, OV2685_REG_CHIP_ID,
0687                   OV2685_REG_VALUE_16BIT, &id);
0688     if (id != CHIP_ID) {
0689         dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
0690         return ret;
0691     }
0692 
0693     dev_info(dev, "Detected OV%04x sensor\n", CHIP_ID);
0694 
0695     return 0;
0696 }
0697 
0698 static int ov2685_configure_regulators(struct ov2685 *ov2685)
0699 {
0700     int i;
0701 
0702     for (i = 0; i < OV2685_NUM_SUPPLIES; i++)
0703         ov2685->supplies[i].supply = ov2685_supply_names[i];
0704 
0705     return devm_regulator_bulk_get(&ov2685->client->dev,
0706                        OV2685_NUM_SUPPLIES,
0707                        ov2685->supplies);
0708 }
0709 
0710 static int ov2685_probe(struct i2c_client *client,
0711             const struct i2c_device_id *id)
0712 {
0713     struct device *dev = &client->dev;
0714     struct ov2685 *ov2685;
0715     int ret;
0716 
0717     ov2685 = devm_kzalloc(dev, sizeof(*ov2685), GFP_KERNEL);
0718     if (!ov2685)
0719         return -ENOMEM;
0720 
0721     ov2685->client = client;
0722     ov2685->cur_mode = &supported_modes[0];
0723 
0724     ov2685->xvclk = devm_clk_get(dev, "xvclk");
0725     if (IS_ERR(ov2685->xvclk)) {
0726         dev_err(dev, "Failed to get xvclk\n");
0727         return -EINVAL;
0728     }
0729     ret = clk_set_rate(ov2685->xvclk, OV2685_XVCLK_FREQ);
0730     if (ret < 0) {
0731         dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
0732         return ret;
0733     }
0734     if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ)
0735         dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
0736 
0737     ov2685->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
0738     if (IS_ERR(ov2685->reset_gpio)) {
0739         dev_err(dev, "Failed to get reset-gpios\n");
0740         return -EINVAL;
0741     }
0742 
0743     ret = ov2685_configure_regulators(ov2685);
0744     if (ret) {
0745         dev_err(dev, "Failed to get power regulators\n");
0746         return ret;
0747     }
0748 
0749     mutex_init(&ov2685->mutex);
0750     v4l2_i2c_subdev_init(&ov2685->subdev, client, &ov2685_subdev_ops);
0751     ret = ov2685_initialize_controls(ov2685);
0752     if (ret)
0753         goto err_destroy_mutex;
0754 
0755     ret = __ov2685_power_on(ov2685);
0756     if (ret)
0757         goto err_free_handler;
0758 
0759     ret = ov2685_check_sensor_id(ov2685, client);
0760     if (ret)
0761         goto err_power_off;
0762 
0763 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
0764     ov2685->subdev.internal_ops = &ov2685_internal_ops;
0765     ov2685->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
0766 #endif
0767 #if defined(CONFIG_MEDIA_CONTROLLER)
0768     ov2685->pad.flags = MEDIA_PAD_FL_SOURCE;
0769     ov2685->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
0770     ret = media_entity_pads_init(&ov2685->subdev.entity, 1, &ov2685->pad);
0771     if (ret < 0)
0772         goto err_power_off;
0773 #endif
0774 
0775     ret = v4l2_async_register_subdev(&ov2685->subdev);
0776     if (ret) {
0777         dev_err(dev, "v4l2 async register subdev failed\n");
0778         goto err_clean_entity;
0779     }
0780 
0781     pm_runtime_set_active(dev);
0782     pm_runtime_enable(dev);
0783     pm_runtime_idle(dev);
0784 
0785     return 0;
0786 
0787 err_clean_entity:
0788 #if defined(CONFIG_MEDIA_CONTROLLER)
0789     media_entity_cleanup(&ov2685->subdev.entity);
0790 #endif
0791 err_power_off:
0792     __ov2685_power_off(ov2685);
0793 err_free_handler:
0794     v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
0795 err_destroy_mutex:
0796     mutex_destroy(&ov2685->mutex);
0797 
0798     return ret;
0799 }
0800 
0801 static int ov2685_remove(struct i2c_client *client)
0802 {
0803     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0804     struct ov2685 *ov2685 = to_ov2685(sd);
0805 
0806     v4l2_async_unregister_subdev(sd);
0807 #if defined(CONFIG_MEDIA_CONTROLLER)
0808     media_entity_cleanup(&sd->entity);
0809 #endif
0810     v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
0811     mutex_destroy(&ov2685->mutex);
0812 
0813     pm_runtime_disable(&client->dev);
0814     if (!pm_runtime_status_suspended(&client->dev))
0815         __ov2685_power_off(ov2685);
0816     pm_runtime_set_suspended(&client->dev);
0817 
0818     return 0;
0819 }
0820 
0821 #if IS_ENABLED(CONFIG_OF)
0822 static const struct of_device_id ov2685_of_match[] = {
0823     { .compatible = "ovti,ov2685" },
0824     {},
0825 };
0826 MODULE_DEVICE_TABLE(of, ov2685_of_match);
0827 #endif
0828 
0829 static struct i2c_driver ov2685_i2c_driver = {
0830     .driver = {
0831         .name = "ov2685",
0832         .pm = &ov2685_pm_ops,
0833         .of_match_table = of_match_ptr(ov2685_of_match),
0834     },
0835     .probe      = &ov2685_probe,
0836     .remove     = &ov2685_remove,
0837 };
0838 
0839 module_i2c_driver(ov2685_i2c_driver);
0840 
0841 MODULE_DESCRIPTION("OmniVision ov2685 sensor driver");
0842 MODULE_LICENSE("GPL v2");
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