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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ov2640 Camera Driver
0004  *
0005  * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
0006  *
0007  * Based on ov772x, ov9640 drivers and previous non merged implementations.
0008  *
0009  * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
0010  * Copyright (C) 2006, OmniVision
0011  */
0012 
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/i2c.h>
0016 #include <linux/clk.h>
0017 #include <linux/slab.h>
0018 #include <linux/delay.h>
0019 #include <linux/gpio.h>
0020 #include <linux/gpio/consumer.h>
0021 #include <linux/of_gpio.h>
0022 #include <linux/v4l2-mediabus.h>
0023 #include <linux/videodev2.h>
0024 
0025 #include <media/v4l2-device.h>
0026 #include <media/v4l2-event.h>
0027 #include <media/v4l2-subdev.h>
0028 #include <media/v4l2-ctrls.h>
0029 #include <media/v4l2-image-sizes.h>
0030 
0031 #define VAL_SET(x, mask, rshift, lshift)  \
0032         ((((x) >> rshift) & mask) << lshift)
0033 /*
0034  * DSP registers
0035  * register offset for BANK_SEL == BANK_SEL_DSP
0036  */
0037 #define R_BYPASS    0x05 /* Bypass DSP */
0038 #define   R_BYPASS_DSP_BYPAS    0x01 /* Bypass DSP, sensor out directly */
0039 #define   R_BYPASS_USE_DSP      0x00 /* Use the internal DSP */
0040 #define QS          0x44 /* Quantization Scale Factor */
0041 #define CTRLI       0x50
0042 #define   CTRLI_LP_DP           0x80
0043 #define   CTRLI_ROUND           0x40
0044 #define   CTRLI_V_DIV_SET(x)    VAL_SET(x, 0x3, 0, 3)
0045 #define   CTRLI_H_DIV_SET(x)    VAL_SET(x, 0x3, 0, 0)
0046 #define HSIZE       0x51 /* H_SIZE[7:0] (real/4) */
0047 #define   HSIZE_SET(x)          VAL_SET(x, 0xFF, 2, 0)
0048 #define VSIZE       0x52 /* V_SIZE[7:0] (real/4) */
0049 #define   VSIZE_SET(x)          VAL_SET(x, 0xFF, 2, 0)
0050 #define XOFFL       0x53 /* OFFSET_X[7:0] */
0051 #define   XOFFL_SET(x)          VAL_SET(x, 0xFF, 0, 0)
0052 #define YOFFL       0x54 /* OFFSET_Y[7:0] */
0053 #define   YOFFL_SET(x)          VAL_SET(x, 0xFF, 0, 0)
0054 #define VHYX        0x55 /* Offset and size completion */
0055 #define   VHYX_VSIZE_SET(x)     VAL_SET(x, 0x1, (8+2), 7)
0056 #define   VHYX_HSIZE_SET(x)     VAL_SET(x, 0x1, (8+2), 3)
0057 #define   VHYX_YOFF_SET(x)      VAL_SET(x, 0x3, 8, 4)
0058 #define   VHYX_XOFF_SET(x)      VAL_SET(x, 0x3, 8, 0)
0059 #define DPRP        0x56
0060 #define TEST        0x57 /* Horizontal size completion */
0061 #define   TEST_HSIZE_SET(x)     VAL_SET(x, 0x1, (9+2), 7)
0062 #define ZMOW        0x5A /* Zoom: Out Width  OUTW[7:0] (real/4) */
0063 #define   ZMOW_OUTW_SET(x)      VAL_SET(x, 0xFF, 2, 0)
0064 #define ZMOH        0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
0065 #define   ZMOH_OUTH_SET(x)      VAL_SET(x, 0xFF, 2, 0)
0066 #define ZMHH        0x5C /* Zoom: Speed and H&W completion */
0067 #define   ZMHH_ZSPEED_SET(x)    VAL_SET(x, 0x0F, 0, 4)
0068 #define   ZMHH_OUTH_SET(x)      VAL_SET(x, 0x1, (8+2), 2)
0069 #define   ZMHH_OUTW_SET(x)      VAL_SET(x, 0x3, (8+2), 0)
0070 #define BPADDR      0x7C /* SDE Indirect Register Access: Address */
0071 #define BPDATA      0x7D /* SDE Indirect Register Access: Data */
0072 #define CTRL2       0x86 /* DSP Module enable 2 */
0073 #define   CTRL2_DCW_EN          0x20
0074 #define   CTRL2_SDE_EN          0x10
0075 #define   CTRL2_UV_ADJ_EN       0x08
0076 #define   CTRL2_UV_AVG_EN       0x04
0077 #define   CTRL2_CMX_EN          0x01
0078 #define CTRL3       0x87 /* DSP Module enable 3 */
0079 #define   CTRL3_BPC_EN          0x80
0080 #define   CTRL3_WPC_EN          0x40
0081 #define SIZEL       0x8C /* Image Size Completion */
0082 #define   SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
0083 #define   SIZEL_HSIZE8_SET(x)    VAL_SET(x, 0x7, 0, 3)
0084 #define   SIZEL_VSIZE8_SET(x)    VAL_SET(x, 0x7, 0, 0)
0085 #define HSIZE8      0xC0 /* Image Horizontal Size HSIZE[10:3] */
0086 #define   HSIZE8_SET(x)         VAL_SET(x, 0xFF, 3, 0)
0087 #define VSIZE8      0xC1 /* Image Vertical Size VSIZE[10:3] */
0088 #define   VSIZE8_SET(x)         VAL_SET(x, 0xFF, 3, 0)
0089 #define CTRL0       0xC2 /* DSP Module enable 0 */
0090 #define   CTRL0_AEC_EN       0x80
0091 #define   CTRL0_AEC_SEL      0x40
0092 #define   CTRL0_STAT_SEL     0x20
0093 #define   CTRL0_VFIRST       0x10
0094 #define   CTRL0_YUV422       0x08
0095 #define   CTRL0_YUV_EN       0x04
0096 #define   CTRL0_RGB_EN       0x02
0097 #define   CTRL0_RAW_EN       0x01
0098 #define CTRL1       0xC3 /* DSP Module enable 1 */
0099 #define   CTRL1_CIP          0x80
0100 #define   CTRL1_DMY          0x40
0101 #define   CTRL1_RAW_GMA      0x20
0102 #define   CTRL1_DG           0x10
0103 #define   CTRL1_AWB          0x08
0104 #define   CTRL1_AWB_GAIN     0x04
0105 #define   CTRL1_LENC         0x02
0106 #define   CTRL1_PRE          0x01
0107 /*      REG 0xC7 (unknown name): affects Auto White Balance (AWB)
0108  *    AWB_OFF            0x40
0109  *    AWB_SIMPLE         0x10
0110  *    AWB_ON             0x00   (Advanced AWB ?) */
0111 #define R_DVP_SP    0xD3 /* DVP output speed control */
0112 #define   R_DVP_SP_AUTO_MODE 0x80
0113 #define   R_DVP_SP_DVP_MASK  0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
0114                    *          = sysclk (48)/(2*[6:0]) (RAW);*/
0115 #define IMAGE_MODE  0xDA /* Image Output Format Select */
0116 #define   IMAGE_MODE_Y8_DVP_EN   0x40
0117 #define   IMAGE_MODE_JPEG_EN     0x10
0118 #define   IMAGE_MODE_YUV422      0x00
0119 #define   IMAGE_MODE_RAW10       0x04 /* (DVP) */
0120 #define   IMAGE_MODE_RGB565      0x08
0121 #define   IMAGE_MODE_HREF_VSYNC  0x02 /* HREF timing select in DVP JPEG output
0122                        * mode (0 for HREF is same as sensor) */
0123 #define   IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
0124                        *    1: Low byte first UYVY (C2[4] =0)
0125                        *        VYUY (C2[4] =1)
0126                        *    0: High byte first YUYV (C2[4]=0)
0127                        *        YVYU (C2[4] = 1) */
0128 #define RESET       0xE0 /* Reset */
0129 #define   RESET_MICROC       0x40
0130 #define   RESET_SCCB         0x20
0131 #define   RESET_JPEG         0x10
0132 #define   RESET_DVP          0x04
0133 #define   RESET_IPU          0x02
0134 #define   RESET_CIF          0x01
0135 #define REGED       0xED /* Register ED */
0136 #define   REGED_CLK_OUT_DIS  0x10
0137 #define MS_SP       0xF0 /* SCCB Master Speed */
0138 #define SS_ID       0xF7 /* SCCB Slave ID */
0139 #define SS_CTRL     0xF8 /* SCCB Slave Control */
0140 #define   SS_CTRL_ADD_AUTO_INC  0x20
0141 #define   SS_CTRL_EN            0x08
0142 #define   SS_CTRL_DELAY_CLK     0x04
0143 #define   SS_CTRL_ACC_EN        0x02
0144 #define   SS_CTRL_SEN_PASS_THR  0x01
0145 #define MC_BIST     0xF9 /* Microcontroller misc register */
0146 #define   MC_BIST_RESET           0x80 /* Microcontroller Reset */
0147 #define   MC_BIST_BOOT_ROM_SEL    0x40
0148 #define   MC_BIST_12KB_SEL        0x20
0149 #define   MC_BIST_12KB_MASK       0x30
0150 #define   MC_BIST_512KB_SEL       0x08
0151 #define   MC_BIST_512KB_MASK      0x0C
0152 #define   MC_BIST_BUSY_BIT_R      0x02
0153 #define   MC_BIST_MC_RES_ONE_SH_W 0x02
0154 #define   MC_BIST_LAUNCH          0x01
0155 #define BANK_SEL    0xFF /* Register Bank Select */
0156 #define   BANK_SEL_DSP     0x00
0157 #define   BANK_SEL_SENS    0x01
0158 
0159 /*
0160  * Sensor registers
0161  * register offset for BANK_SEL == BANK_SEL_SENS
0162  */
0163 #define GAIN        0x00 /* AGC - Gain control gain setting */
0164 #define COM1        0x03 /* Common control 1 */
0165 #define   COM1_1_DUMMY_FR          0x40
0166 #define   COM1_3_DUMMY_FR          0x80
0167 #define   COM1_7_DUMMY_FR          0xC0
0168 #define   COM1_VWIN_LSB_UXGA       0x0F
0169 #define   COM1_VWIN_LSB_SVGA       0x0A
0170 #define   COM1_VWIN_LSB_CIF        0x06
0171 #define REG04       0x04 /* Register 04 */
0172 #define   REG04_DEF             0x20 /* Always set */
0173 #define   REG04_HFLIP_IMG       0x80 /* Horizontal mirror image ON/OFF */
0174 #define   REG04_VFLIP_IMG       0x40 /* Vertical flip image ON/OFF */
0175 #define   REG04_VREF_EN         0x10
0176 #define   REG04_HREF_EN         0x08
0177 #define   REG04_AEC_SET(x)      VAL_SET(x, 0x3, 0, 0)
0178 #define REG08       0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
0179 #define COM2        0x09 /* Common control 2 */
0180 #define   COM2_SOFT_SLEEP_MODE  0x10 /* Soft sleep mode */
0181                      /* Output drive capability */
0182 #define   COM2_OCAP_Nx_SET(N)   (((N) - 1) & 0x03) /* N = [1x .. 4x] */
0183 #define PID         0x0A /* Product ID Number MSB */
0184 #define VER         0x0B /* Product ID Number LSB */
0185 #define COM3        0x0C /* Common control 3 */
0186 #define   COM3_BAND_50H        0x04 /* 0 For Banding at 60H */
0187 #define   COM3_BAND_AUTO       0x02 /* Auto Banding */
0188 #define   COM3_SING_FR_SNAPSH  0x01 /* 0 For enable live video output after the
0189                      * snapshot sequence*/
0190 #define AEC         0x10 /* AEC[9:2] Exposure Value */
0191 #define CLKRC       0x11 /* Internal clock */
0192 #define   CLKRC_EN             0x80
0193 #define   CLKRC_DIV_SET(x)     (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
0194 #define COM7        0x12 /* Common control 7 */
0195 #define   COM7_SRST            0x80 /* Initiates system reset. All registers are
0196                      * set to factory default values after which
0197                      * the chip resumes normal operation */
0198 #define   COM7_RES_UXGA        0x00 /* Resolution selectors for UXGA */
0199 #define   COM7_RES_SVGA        0x40 /* SVGA */
0200 #define   COM7_RES_CIF         0x20 /* CIF */
0201 #define   COM7_ZOOM_EN         0x04 /* Enable Zoom mode */
0202 #define   COM7_COLOR_BAR_TEST  0x02 /* Enable Color Bar Test Pattern */
0203 #define COM8        0x13 /* Common control 8 */
0204 #define   COM8_DEF             0xC0
0205 #define   COM8_BNDF_EN         0x20 /* Banding filter ON/OFF */
0206 #define   COM8_AGC_EN          0x04 /* AGC Auto/Manual control selection */
0207 #define   COM8_AEC_EN          0x01 /* Auto/Manual Exposure control */
0208 #define COM9        0x14 /* Common control 9
0209               * Automatic gain ceiling - maximum AGC value [7:5]*/
0210 #define   COM9_AGC_GAIN_2x     0x00 /* 000 :   2x */
0211 #define   COM9_AGC_GAIN_4x     0x20 /* 001 :   4x */
0212 #define   COM9_AGC_GAIN_8x     0x40 /* 010 :   8x */
0213 #define   COM9_AGC_GAIN_16x    0x60 /* 011 :  16x */
0214 #define   COM9_AGC_GAIN_32x    0x80 /* 100 :  32x */
0215 #define   COM9_AGC_GAIN_64x    0xA0 /* 101 :  64x */
0216 #define   COM9_AGC_GAIN_128x   0xC0 /* 110 : 128x */
0217 #define COM10       0x15 /* Common control 10 */
0218 #define   COM10_PCLK_HREF      0x20 /* PCLK output qualified by HREF */
0219 #define   COM10_PCLK_RISE      0x10 /* Data is updated at the rising edge of
0220                      * PCLK (user can latch data at the next
0221                      * falling edge of PCLK).
0222                      * 0 otherwise. */
0223 #define   COM10_HREF_INV       0x08 /* Invert HREF polarity:
0224                      * HREF negative for valid data*/
0225 #define   COM10_VSINC_INV      0x02 /* Invert VSYNC polarity */
0226 #define HSTART      0x17 /* Horizontal Window start MSB 8 bit */
0227 #define HEND        0x18 /* Horizontal Window end MSB 8 bit */
0228 #define VSTART      0x19 /* Vertical Window start MSB 8 bit */
0229 #define VEND        0x1A /* Vertical Window end MSB 8 bit */
0230 #define MIDH        0x1C /* Manufacturer ID byte - high */
0231 #define MIDL        0x1D /* Manufacturer ID byte - low  */
0232 #define AEW         0x24 /* AGC/AEC - Stable operating region (upper limit) */
0233 #define AEB         0x25 /* AGC/AEC - Stable operating region (lower limit) */
0234 #define VV          0x26 /* AGC/AEC Fast mode operating region */
0235 #define   VV_HIGH_TH_SET(x)      VAL_SET(x, 0xF, 0, 4)
0236 #define   VV_LOW_TH_SET(x)       VAL_SET(x, 0xF, 0, 0)
0237 #define REG2A       0x2A /* Dummy pixel insert MSB */
0238 #define FRARL       0x2B /* Dummy pixel insert LSB */
0239 #define ADDVFL      0x2D /* LSB of insert dummy lines in Vertical direction */
0240 #define ADDVFH      0x2E /* MSB of insert dummy lines in Vertical direction */
0241 #define YAVG        0x2F /* Y/G Channel Average value */
0242 #define REG32       0x32 /* Common Control 32 */
0243 #define   REG32_PCLK_DIV_2    0x80 /* PCLK freq divided by 2 */
0244 #define   REG32_PCLK_DIV_4    0xC0 /* PCLK freq divided by 4 */
0245 #define ARCOM2      0x34 /* Zoom: Horizontal start point */
0246 #define REG45       0x45 /* Register 45 */
0247 #define FLL         0x46 /* Frame Length Adjustment LSBs */
0248 #define FLH         0x47 /* Frame Length Adjustment MSBs */
0249 #define COM19       0x48 /* Zoom: Vertical start point */
0250 #define ZOOMS       0x49 /* Zoom: Vertical start point */
0251 #define COM22       0x4B /* Flash light control */
0252 #define COM25       0x4E /* For Banding operations */
0253 #define   COM25_50HZ_BANDING_AEC_MSBS_MASK      0xC0 /* 50Hz Bd. AEC 2 MSBs */
0254 #define   COM25_60HZ_BANDING_AEC_MSBS_MASK      0x30 /* 60Hz Bd. AEC 2 MSBs */
0255 #define   COM25_50HZ_BANDING_AEC_MSBS_SET(x)    VAL_SET(x, 0x3, 8, 6)
0256 #define   COM25_60HZ_BANDING_AEC_MSBS_SET(x)    VAL_SET(x, 0x3, 8, 4)
0257 #define BD50        0x4F /* 50Hz Banding AEC 8 LSBs */
0258 #define   BD50_50HZ_BANDING_AEC_LSBS_SET(x)     VAL_SET(x, 0xFF, 0, 0)
0259 #define BD60        0x50 /* 60Hz Banding AEC 8 LSBs */
0260 #define   BD60_60HZ_BANDING_AEC_LSBS_SET(x)     VAL_SET(x, 0xFF, 0, 0)
0261 #define REG5A       0x5A /* 50/60Hz Banding Maximum AEC Step */
0262 #define   BD50_MAX_AEC_STEP_MASK         0xF0 /* 50Hz Banding Max. AEC Step */
0263 #define   BD60_MAX_AEC_STEP_MASK         0x0F /* 60Hz Banding Max. AEC Step */
0264 #define   BD50_MAX_AEC_STEP_SET(x)       VAL_SET((x - 1), 0x0F, 0, 4)
0265 #define   BD60_MAX_AEC_STEP_SET(x)       VAL_SET((x - 1), 0x0F, 0, 0)
0266 #define REG5D       0x5D /* AVGsel[7:0],   16-zone average weight option */
0267 #define REG5E       0x5E /* AVGsel[15:8],  16-zone average weight option */
0268 #define REG5F       0x5F /* AVGsel[23:16], 16-zone average weight option */
0269 #define REG60       0x60 /* AVGsel[31:24], 16-zone average weight option */
0270 #define HISTO_LOW   0x61 /* Histogram Algorithm Low Level */
0271 #define HISTO_HIGH  0x62 /* Histogram Algorithm High Level */
0272 
0273 /*
0274  * ID
0275  */
0276 #define MANUFACTURER_ID 0x7FA2
0277 #define PID_OV2640  0x2642
0278 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
0279 
0280 /*
0281  * Struct
0282  */
0283 struct regval_list {
0284     u8 reg_num;
0285     u8 value;
0286 };
0287 
0288 struct ov2640_win_size {
0289     char                *name;
0290     u32             width;
0291     u32             height;
0292     const struct regval_list    *regs;
0293 };
0294 
0295 
0296 struct ov2640_priv {
0297     struct v4l2_subdev      subdev;
0298 #if defined(CONFIG_MEDIA_CONTROLLER)
0299     struct media_pad pad;
0300 #endif
0301     struct v4l2_ctrl_handler    hdl;
0302     u32 cfmt_code;
0303     struct clk          *clk;
0304     const struct ov2640_win_size    *win;
0305 
0306     struct gpio_desc *resetb_gpio;
0307     struct gpio_desc *pwdn_gpio;
0308 
0309     struct mutex lock; /* lock to protect streaming and power_count */
0310     bool streaming;
0311     int power_count;
0312 };
0313 
0314 /*
0315  * Registers settings
0316  */
0317 
0318 #define ENDMARKER { 0xff, 0xff }
0319 
0320 static const struct regval_list ov2640_init_regs[] = {
0321     { BANK_SEL, BANK_SEL_DSP },
0322     { 0x2c,   0xff },
0323     { 0x2e,   0xdf },
0324     { BANK_SEL, BANK_SEL_SENS },
0325     { 0x3c,   0x32 },
0326     { CLKRC,  CLKRC_DIV_SET(1) },
0327     { COM2,   COM2_OCAP_Nx_SET(3) },
0328     { REG04,  REG04_DEF | REG04_HREF_EN },
0329     { COM8,   COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
0330     { COM9,   COM9_AGC_GAIN_8x | 0x08},
0331     { 0x2c,   0x0c },
0332     { 0x33,   0x78 },
0333     { 0x3a,   0x33 },
0334     { 0x3b,   0xfb },
0335     { 0x3e,   0x00 },
0336     { 0x43,   0x11 },
0337     { 0x16,   0x10 },
0338     { 0x39,   0x02 },
0339     { 0x35,   0x88 },
0340     { 0x22,   0x0a },
0341     { 0x37,   0x40 },
0342     { 0x23,   0x00 },
0343     { ARCOM2, 0xa0 },
0344     { 0x06,   0x02 },
0345     { 0x06,   0x88 },
0346     { 0x07,   0xc0 },
0347     { 0x0d,   0xb7 },
0348     { 0x0e,   0x01 },
0349     { 0x4c,   0x00 },
0350     { 0x4a,   0x81 },
0351     { 0x21,   0x99 },
0352     { AEW,    0x40 },
0353     { AEB,    0x38 },
0354     { VV,     VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
0355     { 0x5c,   0x00 },
0356     { 0x63,   0x00 },
0357     { FLL,    0x22 },
0358     { COM3,   0x38 | COM3_BAND_AUTO },
0359     { REG5D,  0x55 },
0360     { REG5E,  0x7d },
0361     { REG5F,  0x7d },
0362     { REG60,  0x55 },
0363     { HISTO_LOW,   0x70 },
0364     { HISTO_HIGH,  0x80 },
0365     { 0x7c,   0x05 },
0366     { 0x20,   0x80 },
0367     { 0x28,   0x30 },
0368     { 0x6c,   0x00 },
0369     { 0x6d,   0x80 },
0370     { 0x6e,   0x00 },
0371     { 0x70,   0x02 },
0372     { 0x71,   0x94 },
0373     { 0x73,   0xc1 },
0374     { 0x3d,   0x34 },
0375     { COM7,   COM7_RES_UXGA | COM7_ZOOM_EN },
0376     { REG5A,  BD50_MAX_AEC_STEP_SET(6)
0377            | BD60_MAX_AEC_STEP_SET(8) },        /* 0x57 */
0378     { COM25,  COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb)
0379            | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) },  /* 0x00 */
0380     { BD50,   BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) },  /* 0xbb */
0381     { BD60,   BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) },  /* 0x9c */
0382     { BANK_SEL,  BANK_SEL_DSP },
0383     { 0xe5,   0x7f },
0384     { MC_BIST,  MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
0385     { 0x41,   0x24 },
0386     { RESET,  RESET_JPEG | RESET_DVP },
0387     { 0x76,   0xff },
0388     { 0x33,   0xa0 },
0389     { 0x42,   0x20 },
0390     { 0x43,   0x18 },
0391     { 0x4c,   0x00 },
0392     { CTRL3,  CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
0393     { 0x88,   0x3f },
0394     { 0xd7,   0x03 },
0395     { 0xd9,   0x10 },
0396     { R_DVP_SP,  R_DVP_SP_AUTO_MODE | 0x2 },
0397     { 0xc8,   0x08 },
0398     { 0xc9,   0x80 },
0399     { BPADDR, 0x00 },
0400     { BPDATA, 0x00 },
0401     { BPADDR, 0x03 },
0402     { BPDATA, 0x48 },
0403     { BPDATA, 0x48 },
0404     { BPADDR, 0x08 },
0405     { BPDATA, 0x20 },
0406     { BPDATA, 0x10 },
0407     { BPDATA, 0x0e },
0408     { 0x90,   0x00 },
0409     { 0x91,   0x0e },
0410     { 0x91,   0x1a },
0411     { 0x91,   0x31 },
0412     { 0x91,   0x5a },
0413     { 0x91,   0x69 },
0414     { 0x91,   0x75 },
0415     { 0x91,   0x7e },
0416     { 0x91,   0x88 },
0417     { 0x91,   0x8f },
0418     { 0x91,   0x96 },
0419     { 0x91,   0xa3 },
0420     { 0x91,   0xaf },
0421     { 0x91,   0xc4 },
0422     { 0x91,   0xd7 },
0423     { 0x91,   0xe8 },
0424     { 0x91,   0x20 },
0425     { 0x92,   0x00 },
0426     { 0x93,   0x06 },
0427     { 0x93,   0xe3 },
0428     { 0x93,   0x03 },
0429     { 0x93,   0x03 },
0430     { 0x93,   0x00 },
0431     { 0x93,   0x02 },
0432     { 0x93,   0x00 },
0433     { 0x93,   0x00 },
0434     { 0x93,   0x00 },
0435     { 0x93,   0x00 },
0436     { 0x93,   0x00 },
0437     { 0x93,   0x00 },
0438     { 0x93,   0x00 },
0439     { 0x96,   0x00 },
0440     { 0x97,   0x08 },
0441     { 0x97,   0x19 },
0442     { 0x97,   0x02 },
0443     { 0x97,   0x0c },
0444     { 0x97,   0x24 },
0445     { 0x97,   0x30 },
0446     { 0x97,   0x28 },
0447     { 0x97,   0x26 },
0448     { 0x97,   0x02 },
0449     { 0x97,   0x98 },
0450     { 0x97,   0x80 },
0451     { 0x97,   0x00 },
0452     { 0x97,   0x00 },
0453     { 0xa4,   0x00 },
0454     { 0xa8,   0x00 },
0455     { 0xc5,   0x11 },
0456     { 0xc6,   0x51 },
0457     { 0xbf,   0x80 },
0458     { 0xc7,   0x10 },   /* simple AWB */
0459     { 0xb6,   0x66 },
0460     { 0xb8,   0xA5 },
0461     { 0xb7,   0x64 },
0462     { 0xb9,   0x7C },
0463     { 0xb3,   0xaf },
0464     { 0xb4,   0x97 },
0465     { 0xb5,   0xFF },
0466     { 0xb0,   0xC5 },
0467     { 0xb1,   0x94 },
0468     { 0xb2,   0x0f },
0469     { 0xc4,   0x5c },
0470     { 0xa6,   0x00 },
0471     { 0xa7,   0x20 },
0472     { 0xa7,   0xd8 },
0473     { 0xa7,   0x1b },
0474     { 0xa7,   0x31 },
0475     { 0xa7,   0x00 },
0476     { 0xa7,   0x18 },
0477     { 0xa7,   0x20 },
0478     { 0xa7,   0xd8 },
0479     { 0xa7,   0x19 },
0480     { 0xa7,   0x31 },
0481     { 0xa7,   0x00 },
0482     { 0xa7,   0x18 },
0483     { 0xa7,   0x20 },
0484     { 0xa7,   0xd8 },
0485     { 0xa7,   0x19 },
0486     { 0xa7,   0x31 },
0487     { 0xa7,   0x00 },
0488     { 0xa7,   0x18 },
0489     { 0x7f,   0x00 },
0490     { 0xe5,   0x1f },
0491     { 0xe1,   0x77 },
0492     { 0xdd,   0x7f },
0493     { CTRL0,  CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
0494     ENDMARKER,
0495 };
0496 
0497 /*
0498  * Register settings for window size
0499  * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
0500  * Then the different zooming configurations will setup the output image size.
0501  */
0502 static const struct regval_list ov2640_size_change_preamble_regs[] = {
0503     { BANK_SEL, BANK_SEL_DSP },
0504     { RESET, RESET_DVP },
0505     { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) |
0506          SIZEL_HSIZE8_SET(UXGA_WIDTH) |
0507          SIZEL_VSIZE8_SET(UXGA_HEIGHT) },
0508     { HSIZE8, HSIZE8_SET(UXGA_WIDTH) },
0509     { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) },
0510     { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
0511          CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
0512     { HSIZE, HSIZE_SET(UXGA_WIDTH) },
0513     { VSIZE, VSIZE_SET(UXGA_HEIGHT) },
0514     { XOFFL, XOFFL_SET(0) },
0515     { YOFFL, YOFFL_SET(0) },
0516     { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) |
0517         VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
0518     { TEST, TEST_HSIZE_SET(UXGA_WIDTH) },
0519     ENDMARKER,
0520 };
0521 
0522 #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div)  \
0523     { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
0524          CTRLI_H_DIV_SET(h_div)},       \
0525     { ZMOW, ZMOW_OUTW_SET(x) },         \
0526     { ZMOH, ZMOH_OUTH_SET(y) },         \
0527     { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) },  \
0528     { R_DVP_SP, pclk_div },             \
0529     { RESET, 0x00}
0530 
0531 static const struct regval_list ov2640_qcif_regs[] = {
0532     PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
0533     ENDMARKER,
0534 };
0535 
0536 static const struct regval_list ov2640_qvga_regs[] = {
0537     PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
0538     ENDMARKER,
0539 };
0540 
0541 static const struct regval_list ov2640_cif_regs[] = {
0542     PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
0543     ENDMARKER,
0544 };
0545 
0546 static const struct regval_list ov2640_vga_regs[] = {
0547     PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
0548     ENDMARKER,
0549 };
0550 
0551 static const struct regval_list ov2640_svga_regs[] = {
0552     PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
0553     ENDMARKER,
0554 };
0555 
0556 static const struct regval_list ov2640_xga_regs[] = {
0557     PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
0558     { CTRLI,    0x00},
0559     ENDMARKER,
0560 };
0561 
0562 static const struct regval_list ov2640_sxga_regs[] = {
0563     PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
0564     { CTRLI,    0x00},
0565     { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
0566     ENDMARKER,
0567 };
0568 
0569 static const struct regval_list ov2640_uxga_regs[] = {
0570     PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
0571     { CTRLI,    0x00},
0572     { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
0573     ENDMARKER,
0574 };
0575 
0576 #define OV2640_SIZE(n, w, h, r) \
0577     {.name = n, .width = w , .height = h, .regs = r }
0578 
0579 static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
0580     OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs),
0581     OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs),
0582     OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs),
0583     OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs),
0584     OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs),
0585     OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs),
0586     OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs),
0587     OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs),
0588 };
0589 
0590 /*
0591  * Register settings for pixel formats
0592  */
0593 static const struct regval_list ov2640_format_change_preamble_regs[] = {
0594     { BANK_SEL, BANK_SEL_DSP },
0595     { R_BYPASS, R_BYPASS_USE_DSP },
0596     ENDMARKER,
0597 };
0598 
0599 static const struct regval_list ov2640_yuyv_regs[] = {
0600     { IMAGE_MODE, IMAGE_MODE_YUV422 },
0601     { 0xd7, 0x03 },
0602     { 0x33, 0xa0 },
0603     { 0xe5, 0x1f },
0604     { 0xe1, 0x67 },
0605     { RESET,  0x00 },
0606     { R_BYPASS, R_BYPASS_USE_DSP },
0607     ENDMARKER,
0608 };
0609 
0610 static const struct regval_list ov2640_uyvy_regs[] = {
0611     { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
0612     { 0xd7, 0x01 },
0613     { 0x33, 0xa0 },
0614     { 0xe1, 0x67 },
0615     { RESET,  0x00 },
0616     { R_BYPASS, R_BYPASS_USE_DSP },
0617     ENDMARKER,
0618 };
0619 
0620 static const struct regval_list ov2640_rgb565_be_regs[] = {
0621     { IMAGE_MODE, IMAGE_MODE_RGB565 },
0622     { 0xd7, 0x03 },
0623     { RESET,  0x00 },
0624     { R_BYPASS, R_BYPASS_USE_DSP },
0625     ENDMARKER,
0626 };
0627 
0628 static const struct regval_list ov2640_rgb565_le_regs[] = {
0629     { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
0630     { 0xd7, 0x03 },
0631     { RESET,  0x00 },
0632     { R_BYPASS, R_BYPASS_USE_DSP },
0633     ENDMARKER,
0634 };
0635 
0636 static u32 ov2640_codes[] = {
0637     MEDIA_BUS_FMT_YUYV8_2X8,
0638     MEDIA_BUS_FMT_UYVY8_2X8,
0639     MEDIA_BUS_FMT_YVYU8_2X8,
0640     MEDIA_BUS_FMT_VYUY8_2X8,
0641     MEDIA_BUS_FMT_RGB565_2X8_BE,
0642     MEDIA_BUS_FMT_RGB565_2X8_LE,
0643 };
0644 
0645 /*
0646  * General functions
0647  */
0648 static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
0649 {
0650     return container_of(i2c_get_clientdata(client), struct ov2640_priv,
0651                 subdev);
0652 }
0653 
0654 static int ov2640_write_array(struct i2c_client *client,
0655                   const struct regval_list *vals)
0656 {
0657     int ret;
0658 
0659     while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
0660         ret = i2c_smbus_write_byte_data(client,
0661                         vals->reg_num, vals->value);
0662         dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
0663              vals->reg_num, vals->value);
0664 
0665         if (ret < 0)
0666             return ret;
0667         vals++;
0668     }
0669     return 0;
0670 }
0671 
0672 static int ov2640_mask_set(struct i2c_client *client,
0673                u8  reg, u8  mask, u8  set)
0674 {
0675     s32 val = i2c_smbus_read_byte_data(client, reg);
0676     if (val < 0)
0677         return val;
0678 
0679     val &= ~mask;
0680     val |= set & mask;
0681 
0682     dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
0683 
0684     return i2c_smbus_write_byte_data(client, reg, val);
0685 }
0686 
0687 static int ov2640_reset(struct i2c_client *client)
0688 {
0689     int ret;
0690     static const struct regval_list reset_seq[] = {
0691         {BANK_SEL, BANK_SEL_SENS},
0692         {COM7, COM7_SRST},
0693         ENDMARKER,
0694     };
0695 
0696     ret = ov2640_write_array(client, reset_seq);
0697     if (ret)
0698         goto err;
0699 
0700     msleep(5);
0701 err:
0702     dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
0703     return ret;
0704 }
0705 
0706 static const char * const ov2640_test_pattern_menu[] = {
0707     "Disabled",
0708     "Eight Vertical Colour Bars",
0709 };
0710 
0711 /*
0712  * functions
0713  */
0714 static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
0715 {
0716     struct v4l2_subdev *sd =
0717         &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
0718     struct i2c_client  *client = v4l2_get_subdevdata(sd);
0719     struct ov2640_priv *priv = to_ov2640(client);
0720     u8 val;
0721     int ret;
0722 
0723     /* v4l2_ctrl_lock() locks our own mutex */
0724 
0725     /*
0726      * If the device is not powered up by the host driver, do not apply any
0727      * controls to H/W at this time. Instead the controls will be restored
0728      * when the streaming is started.
0729      */
0730     if (!priv->power_count)
0731         return 0;
0732 
0733     ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
0734     if (ret < 0)
0735         return ret;
0736 
0737     switch (ctrl->id) {
0738     case V4L2_CID_VFLIP:
0739         val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00;
0740         return ov2640_mask_set(client, REG04,
0741                        REG04_VFLIP_IMG | REG04_VREF_EN, val);
0742         /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */
0743     case V4L2_CID_HFLIP:
0744         val = ctrl->val ? REG04_HFLIP_IMG : 0x00;
0745         return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
0746     case V4L2_CID_TEST_PATTERN:
0747         val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00;
0748         return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val);
0749     }
0750 
0751     return -EINVAL;
0752 }
0753 
0754 #ifdef CONFIG_VIDEO_ADV_DEBUG
0755 static int ov2640_g_register(struct v4l2_subdev *sd,
0756                  struct v4l2_dbg_register *reg)
0757 {
0758     struct i2c_client *client = v4l2_get_subdevdata(sd);
0759     int ret;
0760 
0761     reg->size = 1;
0762     if (reg->reg > 0xff)
0763         return -EINVAL;
0764 
0765     ret = i2c_smbus_read_byte_data(client, reg->reg);
0766     if (ret < 0)
0767         return ret;
0768 
0769     reg->val = ret;
0770 
0771     return 0;
0772 }
0773 
0774 static int ov2640_s_register(struct v4l2_subdev *sd,
0775                  const struct v4l2_dbg_register *reg)
0776 {
0777     struct i2c_client *client = v4l2_get_subdevdata(sd);
0778 
0779     if (reg->reg > 0xff ||
0780         reg->val > 0xff)
0781         return -EINVAL;
0782 
0783     return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
0784 }
0785 #endif
0786 
0787 static void ov2640_set_power(struct ov2640_priv *priv, int on)
0788 {
0789 #ifdef CONFIG_GPIOLIB
0790     if (priv->pwdn_gpio)
0791         gpiod_direction_output(priv->pwdn_gpio, !on);
0792     if (on && priv->resetb_gpio) {
0793         /* Active the resetb pin to perform a reset pulse */
0794         gpiod_direction_output(priv->resetb_gpio, 1);
0795         usleep_range(3000, 5000);
0796         gpiod_set_value(priv->resetb_gpio, 0);
0797     }
0798 #endif
0799 }
0800 
0801 static int ov2640_s_power(struct v4l2_subdev *sd, int on)
0802 {
0803     struct i2c_client *client = v4l2_get_subdevdata(sd);
0804     struct ov2640_priv *priv = to_ov2640(client);
0805 
0806     mutex_lock(&priv->lock);
0807 
0808     /*
0809      * If the power count is modified from 0 to != 0 or from != 0 to 0,
0810      * update the power state.
0811      */
0812     if (priv->power_count == !on)
0813         ov2640_set_power(priv, on);
0814     priv->power_count += on ? 1 : -1;
0815     WARN_ON(priv->power_count < 0);
0816     mutex_unlock(&priv->lock);
0817 
0818     return 0;
0819 }
0820 
0821 /* Select the nearest higher resolution for capture */
0822 static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height)
0823 {
0824     int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
0825 
0826     for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
0827         if (ov2640_supported_win_sizes[i].width  >= width &&
0828             ov2640_supported_win_sizes[i].height >= height)
0829             return &ov2640_supported_win_sizes[i];
0830     }
0831 
0832     return &ov2640_supported_win_sizes[default_size];
0833 }
0834 
0835 static int ov2640_set_params(struct i2c_client *client,
0836                  const struct ov2640_win_size *win, u32 code)
0837 {
0838     const struct regval_list *selected_cfmt_regs;
0839     u8 val;
0840     int ret;
0841 
0842     switch (code) {
0843     case MEDIA_BUS_FMT_RGB565_2X8_BE:
0844         dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__);
0845         selected_cfmt_regs = ov2640_rgb565_be_regs;
0846         break;
0847     case MEDIA_BUS_FMT_RGB565_2X8_LE:
0848         dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__);
0849         selected_cfmt_regs = ov2640_rgb565_le_regs;
0850         break;
0851     case MEDIA_BUS_FMT_YUYV8_2X8:
0852         dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__);
0853         selected_cfmt_regs = ov2640_yuyv_regs;
0854         break;
0855     case MEDIA_BUS_FMT_UYVY8_2X8:
0856     default:
0857         dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__);
0858         selected_cfmt_regs = ov2640_uyvy_regs;
0859         break;
0860     case MEDIA_BUS_FMT_YVYU8_2X8:
0861         dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__);
0862         selected_cfmt_regs = ov2640_yuyv_regs;
0863         break;
0864     case MEDIA_BUS_FMT_VYUY8_2X8:
0865         dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__);
0866         selected_cfmt_regs = ov2640_uyvy_regs;
0867         break;
0868     }
0869 
0870     /* reset hardware */
0871     ov2640_reset(client);
0872 
0873     /* initialize the sensor with default data */
0874     dev_dbg(&client->dev, "%s: Init default", __func__);
0875     ret = ov2640_write_array(client, ov2640_init_regs);
0876     if (ret < 0)
0877         goto err;
0878 
0879     /* select preamble */
0880     dev_dbg(&client->dev, "%s: Set size to %s", __func__, win->name);
0881     ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
0882     if (ret < 0)
0883         goto err;
0884 
0885     /* set size win */
0886     ret = ov2640_write_array(client, win->regs);
0887     if (ret < 0)
0888         goto err;
0889 
0890     /* cfmt preamble */
0891     dev_dbg(&client->dev, "%s: Set cfmt", __func__);
0892     ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
0893     if (ret < 0)
0894         goto err;
0895 
0896     /* set cfmt */
0897     ret = ov2640_write_array(client, selected_cfmt_regs);
0898     if (ret < 0)
0899         goto err;
0900     val = (code == MEDIA_BUS_FMT_YVYU8_2X8)
0901           || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00;
0902     ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val);
0903     if (ret < 0)
0904         goto err;
0905 
0906     return 0;
0907 
0908 err:
0909     dev_err(&client->dev, "%s: Error %d", __func__, ret);
0910     ov2640_reset(client);
0911 
0912     return ret;
0913 }
0914 
0915 static int ov2640_get_fmt(struct v4l2_subdev *sd,
0916         struct v4l2_subdev_state *sd_state,
0917         struct v4l2_subdev_format *format)
0918 {
0919     struct v4l2_mbus_framefmt *mf = &format->format;
0920     struct i2c_client  *client = v4l2_get_subdevdata(sd);
0921     struct ov2640_priv *priv = to_ov2640(client);
0922 
0923     if (format->pad)
0924         return -EINVAL;
0925 
0926     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
0927 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
0928         mf = v4l2_subdev_get_try_format(sd, sd_state, 0);
0929         format->format = *mf;
0930         return 0;
0931 #else
0932         return -EINVAL;
0933 #endif
0934     }
0935 
0936     mf->width   = priv->win->width;
0937     mf->height  = priv->win->height;
0938     mf->code    = priv->cfmt_code;
0939     mf->colorspace  = V4L2_COLORSPACE_SRGB;
0940     mf->field   = V4L2_FIELD_NONE;
0941     mf->ycbcr_enc   = V4L2_YCBCR_ENC_DEFAULT;
0942     mf->quantization = V4L2_QUANTIZATION_DEFAULT;
0943     mf->xfer_func   = V4L2_XFER_FUNC_DEFAULT;
0944 
0945     return 0;
0946 }
0947 
0948 static int ov2640_set_fmt(struct v4l2_subdev *sd,
0949         struct v4l2_subdev_state *sd_state,
0950         struct v4l2_subdev_format *format)
0951 {
0952     struct v4l2_mbus_framefmt *mf = &format->format;
0953     struct i2c_client *client = v4l2_get_subdevdata(sd);
0954     struct ov2640_priv *priv = to_ov2640(client);
0955     const struct ov2640_win_size *win;
0956     int ret = 0;
0957 
0958     if (format->pad)
0959         return -EINVAL;
0960 
0961     mutex_lock(&priv->lock);
0962 
0963     /* select suitable win */
0964     win = ov2640_select_win(mf->width, mf->height);
0965     mf->width   = win->width;
0966     mf->height  = win->height;
0967 
0968     mf->field   = V4L2_FIELD_NONE;
0969     mf->colorspace  = V4L2_COLORSPACE_SRGB;
0970     mf->ycbcr_enc   = V4L2_YCBCR_ENC_DEFAULT;
0971     mf->quantization = V4L2_QUANTIZATION_DEFAULT;
0972     mf->xfer_func   = V4L2_XFER_FUNC_DEFAULT;
0973 
0974     switch (mf->code) {
0975     case MEDIA_BUS_FMT_RGB565_2X8_BE:
0976     case MEDIA_BUS_FMT_RGB565_2X8_LE:
0977     case MEDIA_BUS_FMT_YUYV8_2X8:
0978     case MEDIA_BUS_FMT_UYVY8_2X8:
0979     case MEDIA_BUS_FMT_YVYU8_2X8:
0980     case MEDIA_BUS_FMT_VYUY8_2X8:
0981         break;
0982     default:
0983         mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
0984         break;
0985     }
0986 
0987     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
0988         struct ov2640_priv *priv = to_ov2640(client);
0989 
0990         if (priv->streaming) {
0991             ret = -EBUSY;
0992             goto out;
0993         }
0994         /* select win */
0995         priv->win = win;
0996         /* select format */
0997         priv->cfmt_code = mf->code;
0998     } else {
0999         sd_state->pads->try_fmt = *mf;
1000     }
1001 out:
1002     mutex_unlock(&priv->lock);
1003 
1004     return ret;
1005 }
1006 
1007 static int ov2640_init_cfg(struct v4l2_subdev *sd,
1008                struct v4l2_subdev_state *sd_state)
1009 {
1010 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1011     struct v4l2_mbus_framefmt *try_fmt =
1012         v4l2_subdev_get_try_format(sd, sd_state, 0);
1013     const struct ov2640_win_size *win =
1014         ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);
1015 
1016     try_fmt->width = win->width;
1017     try_fmt->height = win->height;
1018     try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
1019     try_fmt->colorspace = V4L2_COLORSPACE_SRGB;
1020     try_fmt->field = V4L2_FIELD_NONE;
1021     try_fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1022     try_fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
1023     try_fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
1024 #endif
1025     return 0;
1026 }
1027 
1028 static int ov2640_enum_mbus_code(struct v4l2_subdev *sd,
1029         struct v4l2_subdev_state *sd_state,
1030         struct v4l2_subdev_mbus_code_enum *code)
1031 {
1032     if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes))
1033         return -EINVAL;
1034 
1035     code->code = ov2640_codes[code->index];
1036     return 0;
1037 }
1038 
1039 static int ov2640_get_selection(struct v4l2_subdev *sd,
1040         struct v4l2_subdev_state *sd_state,
1041         struct v4l2_subdev_selection *sel)
1042 {
1043     if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1044         return -EINVAL;
1045 
1046     switch (sel->target) {
1047     case V4L2_SEL_TGT_CROP_BOUNDS:
1048     case V4L2_SEL_TGT_CROP:
1049         sel->r.left = 0;
1050         sel->r.top = 0;
1051         sel->r.width = UXGA_WIDTH;
1052         sel->r.height = UXGA_HEIGHT;
1053         return 0;
1054     default:
1055         return -EINVAL;
1056     }
1057 }
1058 
1059 static int ov2640_s_stream(struct v4l2_subdev *sd, int on)
1060 {
1061     struct i2c_client *client = v4l2_get_subdevdata(sd);
1062     struct ov2640_priv *priv = to_ov2640(client);
1063     int ret = 0;
1064 
1065     mutex_lock(&priv->lock);
1066     if (priv->streaming == !on) {
1067         if (on) {
1068             ret = ov2640_set_params(client, priv->win,
1069                         priv->cfmt_code);
1070             if (!ret)
1071                 ret = __v4l2_ctrl_handler_setup(&priv->hdl);
1072         }
1073     }
1074     if (!ret)
1075         priv->streaming = on;
1076     mutex_unlock(&priv->lock);
1077 
1078     return ret;
1079 }
1080 
1081 static int ov2640_video_probe(struct i2c_client *client)
1082 {
1083     struct ov2640_priv *priv = to_ov2640(client);
1084     u8 pid, ver, midh, midl;
1085     const char *devname;
1086     int ret;
1087 
1088     ret = ov2640_s_power(&priv->subdev, 1);
1089     if (ret < 0)
1090         return ret;
1091 
1092     /*
1093      * check and show product ID and manufacturer ID
1094      */
1095     i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
1096     pid  = i2c_smbus_read_byte_data(client, PID);
1097     ver  = i2c_smbus_read_byte_data(client, VER);
1098     midh = i2c_smbus_read_byte_data(client, MIDH);
1099     midl = i2c_smbus_read_byte_data(client, MIDL);
1100 
1101     switch (VERSION(pid, ver)) {
1102     case PID_OV2640:
1103         devname     = "ov2640";
1104         break;
1105     default:
1106         dev_err(&client->dev,
1107             "Product ID error %x:%x\n", pid, ver);
1108         ret = -ENODEV;
1109         goto done;
1110     }
1111 
1112     dev_info(&client->dev,
1113          "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1114          devname, pid, ver, midh, midl);
1115 
1116 done:
1117     ov2640_s_power(&priv->subdev, 0);
1118     return ret;
1119 }
1120 
1121 static const struct v4l2_ctrl_ops ov2640_ctrl_ops = {
1122     .s_ctrl = ov2640_s_ctrl,
1123 };
1124 
1125 static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
1126     .log_status = v4l2_ctrl_subdev_log_status,
1127     .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1128     .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1129 #ifdef CONFIG_VIDEO_ADV_DEBUG
1130     .g_register = ov2640_g_register,
1131     .s_register = ov2640_s_register,
1132 #endif
1133     .s_power    = ov2640_s_power,
1134 };
1135 
1136 static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = {
1137     .init_cfg   = ov2640_init_cfg,
1138     .enum_mbus_code = ov2640_enum_mbus_code,
1139     .get_selection  = ov2640_get_selection,
1140     .get_fmt    = ov2640_get_fmt,
1141     .set_fmt    = ov2640_set_fmt,
1142 };
1143 
1144 static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = {
1145     .s_stream = ov2640_s_stream,
1146 };
1147 
1148 static const struct v4l2_subdev_ops ov2640_subdev_ops = {
1149     .core   = &ov2640_subdev_core_ops,
1150     .pad    = &ov2640_subdev_pad_ops,
1151     .video  = &ov2640_subdev_video_ops,
1152 };
1153 
1154 static int ov2640_probe_dt(struct i2c_client *client,
1155         struct ov2640_priv *priv)
1156 {
1157     int ret;
1158 
1159     /* Request the reset GPIO deasserted */
1160     priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
1161             GPIOD_OUT_LOW);
1162 
1163     if (!priv->resetb_gpio)
1164         dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
1165 
1166     ret = PTR_ERR_OR_ZERO(priv->resetb_gpio);
1167     if (ret && ret != -ENOSYS) {
1168         dev_dbg(&client->dev,
1169             "Error %d while getting resetb gpio\n", ret);
1170         return ret;
1171     }
1172 
1173     /* Request the power down GPIO asserted */
1174     priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
1175             GPIOD_OUT_HIGH);
1176 
1177     if (!priv->pwdn_gpio)
1178         dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
1179 
1180     ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio);
1181     if (ret && ret != -ENOSYS) {
1182         dev_dbg(&client->dev,
1183             "Error %d while getting pwdn gpio\n", ret);
1184         return ret;
1185     }
1186 
1187     return 0;
1188 }
1189 
1190 /*
1191  * i2c_driver functions
1192  */
1193 static int ov2640_probe(struct i2c_client *client)
1194 {
1195     struct ov2640_priv  *priv;
1196     struct i2c_adapter  *adapter = client->adapter;
1197     int         ret;
1198 
1199     if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1200         dev_err(&adapter->dev,
1201             "OV2640: I2C-Adapter doesn't support SMBUS\n");
1202         return -EIO;
1203     }
1204 
1205     priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1206     if (!priv)
1207         return -ENOMEM;
1208 
1209     if (client->dev.of_node) {
1210         priv->clk = devm_clk_get(&client->dev, "xvclk");
1211         if (IS_ERR(priv->clk))
1212             return PTR_ERR(priv->clk);
1213         ret = clk_prepare_enable(priv->clk);
1214         if (ret)
1215             return ret;
1216     }
1217 
1218     ret = ov2640_probe_dt(client, priv);
1219     if (ret)
1220         goto err_clk;
1221 
1222     priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);
1223     priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
1224 
1225     v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
1226     priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1227                   V4L2_SUBDEV_FL_HAS_EVENTS;
1228     mutex_init(&priv->lock);
1229     v4l2_ctrl_handler_init(&priv->hdl, 3);
1230     priv->hdl.lock = &priv->lock;
1231     v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1232             V4L2_CID_VFLIP, 0, 1, 1, 0);
1233     v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1234             V4L2_CID_HFLIP, 0, 1, 1, 0);
1235     v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov2640_ctrl_ops,
1236             V4L2_CID_TEST_PATTERN,
1237             ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0,
1238             ov2640_test_pattern_menu);
1239     priv->subdev.ctrl_handler = &priv->hdl;
1240     if (priv->hdl.error) {
1241         ret = priv->hdl.error;
1242         goto err_hdl;
1243     }
1244 #if defined(CONFIG_MEDIA_CONTROLLER)
1245     priv->pad.flags = MEDIA_PAD_FL_SOURCE;
1246     priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1247     ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
1248     if (ret < 0)
1249         goto err_hdl;
1250 #endif
1251 
1252     ret = ov2640_video_probe(client);
1253     if (ret < 0)
1254         goto err_videoprobe;
1255 
1256     ret = v4l2_async_register_subdev(&priv->subdev);
1257     if (ret < 0)
1258         goto err_videoprobe;
1259 
1260     dev_info(&adapter->dev, "OV2640 Probed\n");
1261 
1262     return 0;
1263 
1264 err_videoprobe:
1265     media_entity_cleanup(&priv->subdev.entity);
1266 err_hdl:
1267     v4l2_ctrl_handler_free(&priv->hdl);
1268     mutex_destroy(&priv->lock);
1269 err_clk:
1270     clk_disable_unprepare(priv->clk);
1271     return ret;
1272 }
1273 
1274 static int ov2640_remove(struct i2c_client *client)
1275 {
1276     struct ov2640_priv       *priv = to_ov2640(client);
1277 
1278     v4l2_async_unregister_subdev(&priv->subdev);
1279     v4l2_ctrl_handler_free(&priv->hdl);
1280     mutex_destroy(&priv->lock);
1281     media_entity_cleanup(&priv->subdev.entity);
1282     v4l2_device_unregister_subdev(&priv->subdev);
1283     clk_disable_unprepare(priv->clk);
1284     return 0;
1285 }
1286 
1287 static const struct i2c_device_id ov2640_id[] = {
1288     { "ov2640", 0 },
1289     { }
1290 };
1291 MODULE_DEVICE_TABLE(i2c, ov2640_id);
1292 
1293 static const struct of_device_id ov2640_of_match[] = {
1294     {.compatible = "ovti,ov2640", },
1295     {},
1296 };
1297 MODULE_DEVICE_TABLE(of, ov2640_of_match);
1298 
1299 static struct i2c_driver ov2640_i2c_driver = {
1300     .driver = {
1301         .name = "ov2640",
1302         .of_match_table = of_match_ptr(ov2640_of_match),
1303     },
1304     .probe_new = ov2640_probe,
1305     .remove   = ov2640_remove,
1306     .id_table = ov2640_id,
1307 };
1308 
1309 module_i2c_driver(ov2640_i2c_driver);
1310 
1311 MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor");
1312 MODULE_AUTHOR("Alberto Panizzo");
1313 MODULE_LICENSE("GPL v2");
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