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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2021 Intel Corporation.
0003 
0004 #include <linux/acpi.h>
0005 #include <linux/i2c.h>
0006 #include <linux/module.h>
0007 #include <linux/pm_runtime.h>
0008 #include <media/v4l2-ctrls.h>
0009 #include <media/v4l2-device.h>
0010 #include <media/v4l2-fwnode.h>
0011 
0012 #define OV13B10_REG_VALUE_08BIT     1
0013 #define OV13B10_REG_VALUE_16BIT     2
0014 #define OV13B10_REG_VALUE_24BIT     3
0015 
0016 #define OV13B10_REG_MODE_SELECT     0x0100
0017 #define OV13B10_MODE_STANDBY        0x00
0018 #define OV13B10_MODE_STREAMING      0x01
0019 
0020 #define OV13B10_REG_SOFTWARE_RST    0x0103
0021 #define OV13B10_SOFTWARE_RST        0x01
0022 
0023 /* Chip ID */
0024 #define OV13B10_REG_CHIP_ID     0x300a
0025 #define OV13B10_CHIP_ID         0x560d42
0026 
0027 /* V_TIMING internal */
0028 #define OV13B10_REG_VTS         0x380e
0029 #define OV13B10_VTS_30FPS       0x0c7c
0030 #define OV13B10_VTS_60FPS       0x063e
0031 #define OV13B10_VTS_MAX         0x7fff
0032 
0033 /* HBLANK control - read only */
0034 #define OV13B10_PPL_560MHZ      4704
0035 
0036 /* Exposure control */
0037 #define OV13B10_REG_EXPOSURE        0x3500
0038 #define OV13B10_EXPOSURE_MIN        4
0039 #define OV13B10_EXPOSURE_STEP       1
0040 #define OV13B10_EXPOSURE_DEFAULT    0x40
0041 
0042 /* Analog gain control */
0043 #define OV13B10_REG_ANALOG_GAIN     0x3508
0044 #define OV13B10_ANA_GAIN_MIN        0x80
0045 #define OV13B10_ANA_GAIN_MAX        0x07c0
0046 #define OV13B10_ANA_GAIN_STEP       1
0047 #define OV13B10_ANA_GAIN_DEFAULT    0x80
0048 
0049 /* Digital gain control */
0050 #define OV13B10_REG_DGTL_GAIN_H     0x350a
0051 #define OV13B10_REG_DGTL_GAIN_M     0x350b
0052 #define OV13B10_REG_DGTL_GAIN_L     0x350c
0053 
0054 #define OV13B10_DGTL_GAIN_MIN       1024         /* Min = 1 X */
0055 #define OV13B10_DGTL_GAIN_MAX       (4096 - 1)   /* Max = 4 X */
0056 #define OV13B10_DGTL_GAIN_DEFAULT   2560         /* Default gain = 2.5 X */
0057 #define OV13B10_DGTL_GAIN_STEP      1        /* Each step = 1/1024 */
0058 
0059 #define OV13B10_DGTL_GAIN_L_SHIFT   6
0060 #define OV13B10_DGTL_GAIN_L_MASK    0x3
0061 #define OV13B10_DGTL_GAIN_M_SHIFT   2
0062 #define OV13B10_DGTL_GAIN_M_MASK    0xff
0063 #define OV13B10_DGTL_GAIN_H_SHIFT   10
0064 #define OV13B10_DGTL_GAIN_H_MASK    0x3
0065 
0066 /* Test Pattern Control */
0067 #define OV13B10_REG_TEST_PATTERN    0x5080
0068 #define OV13B10_TEST_PATTERN_ENABLE BIT(7)
0069 #define OV13B10_TEST_PATTERN_MASK   0xf3
0070 #define OV13B10_TEST_PATTERN_BAR_SHIFT  2
0071 
0072 /* Flip Control */
0073 #define OV13B10_REG_FORMAT1     0x3820
0074 #define OV13B10_REG_FORMAT2     0x3821
0075 
0076 /* Horizontal Window Offset */
0077 #define OV13B10_REG_H_WIN_OFFSET    0x3811
0078 
0079 /* Vertical Window Offset */
0080 #define OV13B10_REG_V_WIN_OFFSET    0x3813
0081 
0082 struct ov13b10_reg {
0083     u16 address;
0084     u8 val;
0085 };
0086 
0087 struct ov13b10_reg_list {
0088     u32 num_of_regs;
0089     const struct ov13b10_reg *regs;
0090 };
0091 
0092 /* Link frequency config */
0093 struct ov13b10_link_freq_config {
0094     u32 pixels_per_line;
0095 
0096     /* registers for this link frequency */
0097     struct ov13b10_reg_list reg_list;
0098 };
0099 
0100 /* Mode : resolution and related config&values */
0101 struct ov13b10_mode {
0102     /* Frame width */
0103     u32 width;
0104     /* Frame height */
0105     u32 height;
0106 
0107     /* V-timing */
0108     u32 vts_def;
0109     u32 vts_min;
0110 
0111     /* Index of Link frequency config to be used */
0112     u32 link_freq_index;
0113     /* Default register values */
0114     struct ov13b10_reg_list reg_list;
0115 };
0116 
0117 /* 4208x3120 needs 1120Mbps/lane, 4 lanes */
0118 static const struct ov13b10_reg mipi_data_rate_1120mbps[] = {
0119     {0x0103, 0x01},
0120     {0x0303, 0x04},
0121     {0x0305, 0xaf},
0122     {0x0321, 0x00},
0123     {0x0323, 0x04},
0124     {0x0324, 0x01},
0125     {0x0325, 0xa4},
0126     {0x0326, 0x81},
0127     {0x0327, 0x04},
0128     {0x3012, 0x07},
0129     {0x3013, 0x32},
0130     {0x3107, 0x23},
0131     {0x3501, 0x0c},
0132     {0x3502, 0x10},
0133     {0x3504, 0x08},
0134     {0x3508, 0x07},
0135     {0x3509, 0xc0},
0136     {0x3600, 0x16},
0137     {0x3601, 0x54},
0138     {0x3612, 0x4e},
0139     {0x3620, 0x00},
0140     {0x3621, 0x68},
0141     {0x3622, 0x66},
0142     {0x3623, 0x03},
0143     {0x3662, 0x92},
0144     {0x3666, 0xbb},
0145     {0x3667, 0x44},
0146     {0x366e, 0xff},
0147     {0x366f, 0xf3},
0148     {0x3675, 0x44},
0149     {0x3676, 0x00},
0150     {0x367f, 0xe9},
0151     {0x3681, 0x32},
0152     {0x3682, 0x1f},
0153     {0x3683, 0x0b},
0154     {0x3684, 0x0b},
0155     {0x3704, 0x0f},
0156     {0x3706, 0x40},
0157     {0x3708, 0x3b},
0158     {0x3709, 0x72},
0159     {0x370b, 0xa2},
0160     {0x3714, 0x24},
0161     {0x371a, 0x3e},
0162     {0x3725, 0x42},
0163     {0x3739, 0x12},
0164     {0x3767, 0x00},
0165     {0x377a, 0x0d},
0166     {0x3789, 0x18},
0167     {0x3790, 0x40},
0168     {0x3791, 0xa2},
0169     {0x37c2, 0x04},
0170     {0x37c3, 0xf1},
0171     {0x37d9, 0x0c},
0172     {0x37da, 0x02},
0173     {0x37dc, 0x02},
0174     {0x37e1, 0x04},
0175     {0x37e2, 0x0a},
0176     {0x3800, 0x00},
0177     {0x3801, 0x00},
0178     {0x3802, 0x00},
0179     {0x3803, 0x08},
0180     {0x3804, 0x10},
0181     {0x3805, 0x8f},
0182     {0x3806, 0x0c},
0183     {0x3807, 0x47},
0184     {0x3808, 0x10},
0185     {0x3809, 0x70},
0186     {0x380a, 0x0c},
0187     {0x380b, 0x30},
0188     {0x380c, 0x04},
0189     {0x380d, 0x98},
0190     {0x380e, 0x0c},
0191     {0x380f, 0x7c},
0192     {0x3811, 0x0f},
0193     {0x3813, 0x09},
0194     {0x3814, 0x01},
0195     {0x3815, 0x01},
0196     {0x3816, 0x01},
0197     {0x3817, 0x01},
0198     {0x381f, 0x08},
0199     {0x3820, 0x88},
0200     {0x3821, 0x00},
0201     {0x3822, 0x14},
0202     {0x382e, 0xe6},
0203     {0x3c80, 0x00},
0204     {0x3c87, 0x01},
0205     {0x3c8c, 0x19},
0206     {0x3c8d, 0x1c},
0207     {0x3ca0, 0x00},
0208     {0x3ca1, 0x00},
0209     {0x3ca2, 0x00},
0210     {0x3ca3, 0x00},
0211     {0x3ca4, 0x50},
0212     {0x3ca5, 0x11},
0213     {0x3ca6, 0x01},
0214     {0x3ca7, 0x00},
0215     {0x3ca8, 0x00},
0216     {0x4008, 0x02},
0217     {0x4009, 0x0f},
0218     {0x400a, 0x01},
0219     {0x400b, 0x19},
0220     {0x4011, 0x21},
0221     {0x4017, 0x08},
0222     {0x4019, 0x04},
0223     {0x401a, 0x58},
0224     {0x4032, 0x1e},
0225     {0x4050, 0x02},
0226     {0x4051, 0x09},
0227     {0x405e, 0x00},
0228     {0x4066, 0x02},
0229     {0x4501, 0x00},
0230     {0x4502, 0x10},
0231     {0x4505, 0x00},
0232     {0x4800, 0x64},
0233     {0x481b, 0x3e},
0234     {0x481f, 0x30},
0235     {0x4825, 0x34},
0236     {0x4837, 0x0e},
0237     {0x484b, 0x01},
0238     {0x4883, 0x02},
0239     {0x5000, 0xff},
0240     {0x5001, 0x0f},
0241     {0x5045, 0x20},
0242     {0x5046, 0x20},
0243     {0x5047, 0xa4},
0244     {0x5048, 0x20},
0245     {0x5049, 0xa4},
0246     {0x0100, 0x01},
0247 };
0248 
0249 static const struct ov13b10_reg mode_4208x3120_regs[] = {
0250     {0x0305, 0xaf},
0251     {0x3501, 0x0c},
0252     {0x3662, 0x92},
0253     {0x3714, 0x24},
0254     {0x3739, 0x12},
0255     {0x37c2, 0x04},
0256     {0x37d9, 0x0c},
0257     {0x37e2, 0x0a},
0258     {0x3800, 0x00},
0259     {0x3801, 0x00},
0260     {0x3802, 0x00},
0261     {0x3803, 0x08},
0262     {0x3804, 0x10},
0263     {0x3805, 0x8f},
0264     {0x3806, 0x0c},
0265     {0x3807, 0x47},
0266     {0x3808, 0x10},
0267     {0x3809, 0x70},
0268     {0x380a, 0x0c},
0269     {0x380b, 0x30},
0270     {0x380c, 0x04},
0271     {0x380d, 0x98},
0272     {0x380e, 0x0c},
0273     {0x380f, 0x7c},
0274     {0x3810, 0x00},
0275     {0x3811, 0x0f},
0276     {0x3812, 0x00},
0277     {0x3813, 0x09},
0278     {0x3814, 0x01},
0279     {0x3816, 0x01},
0280     {0x3820, 0x88},
0281     {0x3c8c, 0x19},
0282     {0x4008, 0x02},
0283     {0x4009, 0x0f},
0284     {0x4050, 0x02},
0285     {0x4051, 0x09},
0286     {0x4501, 0x00},
0287     {0x4505, 0x00},
0288     {0x4837, 0x0e},
0289     {0x5000, 0xff},
0290     {0x5001, 0x0f},
0291 };
0292 
0293 static const struct ov13b10_reg mode_4160x3120_regs[] = {
0294     {0x0305, 0xaf},
0295     {0x3501, 0x0c},
0296     {0x3662, 0x92},
0297     {0x3714, 0x24},
0298     {0x3739, 0x12},
0299     {0x37c2, 0x04},
0300     {0x37d9, 0x0c},
0301     {0x37e2, 0x0a},
0302     {0x3800, 0x00},
0303     {0x3801, 0x00},
0304     {0x3802, 0x00},
0305     {0x3803, 0x08},
0306     {0x3804, 0x10},
0307     {0x3805, 0x8f},
0308     {0x3806, 0x0c},
0309     {0x3807, 0x47},
0310     {0x3808, 0x10},
0311     {0x3809, 0x40},
0312     {0x380a, 0x0c},
0313     {0x380b, 0x30},
0314     {0x380c, 0x04},
0315     {0x380d, 0x98},
0316     {0x380e, 0x0c},
0317     {0x380f, 0x7c},
0318     {0x3810, 0x00},
0319     {0x3811, 0x27},
0320     {0x3812, 0x00},
0321     {0x3813, 0x09},
0322     {0x3814, 0x01},
0323     {0x3816, 0x01},
0324     {0x3820, 0x88},
0325     {0x3c8c, 0x19},
0326     {0x4008, 0x02},
0327     {0x4009, 0x0f},
0328     {0x4050, 0x02},
0329     {0x4051, 0x09},
0330     {0x4501, 0x00},
0331     {0x4505, 0x00},
0332     {0x4837, 0x0e},
0333     {0x5000, 0xff},
0334     {0x5001, 0x0f},
0335 };
0336 
0337 static const struct ov13b10_reg mode_4160x2340_regs[] = {
0338     {0x0305, 0xaf},
0339     {0x3501, 0x0c},
0340     {0x3662, 0x92},
0341     {0x3714, 0x24},
0342     {0x3739, 0x12},
0343     {0x37c2, 0x04},
0344     {0x37d9, 0x0c},
0345     {0x37e2, 0x0a},
0346     {0x3800, 0x00},
0347     {0x3801, 0x00},
0348     {0x3802, 0x00},
0349     {0x3803, 0x08},
0350     {0x3804, 0x10},
0351     {0x3805, 0x8f},
0352     {0x3806, 0x0c},
0353     {0x3807, 0x47},
0354     {0x3808, 0x10},
0355     {0x3809, 0x40},
0356     {0x380a, 0x09},
0357     {0x380b, 0x24},
0358     {0x380c, 0x04},
0359     {0x380d, 0x98},
0360     {0x380e, 0x0c},
0361     {0x380f, 0x7c},
0362     {0x3810, 0x00},
0363     {0x3811, 0x27},
0364     {0x3812, 0x01},
0365     {0x3813, 0x8f},
0366     {0x3814, 0x01},
0367     {0x3816, 0x01},
0368     {0x3820, 0x88},
0369     {0x3c8c, 0x19},
0370     {0x4008, 0x02},
0371     {0x4009, 0x0f},
0372     {0x4050, 0x02},
0373     {0x4051, 0x09},
0374     {0x4501, 0x00},
0375     {0x4505, 0x00},
0376     {0x4837, 0x0e},
0377     {0x5000, 0xff},
0378     {0x5001, 0x0f},
0379 };
0380 
0381 static const struct ov13b10_reg mode_2104x1560_regs[] = {
0382     {0x0305, 0xaf},
0383     {0x3501, 0x06},
0384     {0x3662, 0x88},
0385     {0x3714, 0x28},
0386     {0x3739, 0x10},
0387     {0x37c2, 0x14},
0388     {0x37d9, 0x06},
0389     {0x37e2, 0x0c},
0390     {0x3800, 0x00},
0391     {0x3801, 0x00},
0392     {0x3802, 0x00},
0393     {0x3803, 0x08},
0394     {0x3804, 0x10},
0395     {0x3805, 0x8f},
0396     {0x3806, 0x0c},
0397     {0x3807, 0x47},
0398     {0x3808, 0x08},
0399     {0x3809, 0x38},
0400     {0x380a, 0x06},
0401     {0x380b, 0x18},
0402     {0x380c, 0x04},
0403     {0x380d, 0x98},
0404     {0x380e, 0x06},
0405     {0x380f, 0x3e},
0406     {0x3810, 0x00},
0407     {0x3811, 0x07},
0408     {0x3812, 0x00},
0409     {0x3813, 0x05},
0410     {0x3814, 0x03},
0411     {0x3816, 0x03},
0412     {0x3820, 0x8b},
0413     {0x3c8c, 0x18},
0414     {0x4008, 0x00},
0415     {0x4009, 0x05},
0416     {0x4050, 0x00},
0417     {0x4051, 0x05},
0418     {0x4501, 0x08},
0419     {0x4505, 0x00},
0420     {0x4837, 0x0e},
0421     {0x5000, 0xfd},
0422     {0x5001, 0x0d},
0423 };
0424 
0425 static const struct ov13b10_reg mode_2080x1170_regs[] = {
0426     {0x0305, 0xaf},
0427     {0x3501, 0x06},
0428     {0x3662, 0x88},
0429     {0x3714, 0x28},
0430     {0x3739, 0x10},
0431     {0x37c2, 0x14},
0432     {0x37d9, 0x06},
0433     {0x37e2, 0x0c},
0434     {0x3800, 0x00},
0435     {0x3801, 0x00},
0436     {0x3802, 0x00},
0437     {0x3803, 0x08},
0438     {0x3804, 0x10},
0439     {0x3805, 0x8f},
0440     {0x3806, 0x0c},
0441     {0x3807, 0x47},
0442     {0x3808, 0x08},
0443     {0x3809, 0x20},
0444     {0x380a, 0x04},
0445     {0x380b, 0x92},
0446     {0x380c, 0x04},
0447     {0x380d, 0x98},
0448     {0x380e, 0x06},
0449     {0x380f, 0x3e},
0450     {0x3810, 0x00},
0451     {0x3811, 0x13},
0452     {0x3812, 0x00},
0453     {0x3813, 0xc9},
0454     {0x3814, 0x03},
0455     {0x3816, 0x03},
0456     {0x3820, 0x8b},
0457     {0x3c8c, 0x18},
0458     {0x4008, 0x00},
0459     {0x4009, 0x05},
0460     {0x4050, 0x00},
0461     {0x4051, 0x05},
0462     {0x4501, 0x08},
0463     {0x4505, 0x00},
0464     {0x4837, 0x0e},
0465     {0x5000, 0xfd},
0466     {0x5001, 0x0d},
0467 };
0468 
0469 static const char * const ov13b10_test_pattern_menu[] = {
0470     "Disabled",
0471     "Vertical Color Bar Type 1",
0472     "Vertical Color Bar Type 2",
0473     "Vertical Color Bar Type 3",
0474     "Vertical Color Bar Type 4"
0475 };
0476 
0477 /* Configurations for supported link frequencies */
0478 #define OV13B10_LINK_FREQ_560MHZ    560000000ULL
0479 #define OV13B10_LINK_FREQ_INDEX_0   0
0480 
0481 #define OV13B10_EXT_CLK         19200000
0482 #define OV13B10_DATA_LANES      4
0483 
0484 /*
0485  * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
0486  * data rate => double data rate; number of lanes => 4; bits per pixel => 10
0487  */
0488 static u64 link_freq_to_pixel_rate(u64 f)
0489 {
0490     f *= 2 * OV13B10_DATA_LANES;
0491     do_div(f, 10);
0492 
0493     return f;
0494 }
0495 
0496 /* Menu items for LINK_FREQ V4L2 control */
0497 static const s64 link_freq_menu_items[] = {
0498     OV13B10_LINK_FREQ_560MHZ
0499 };
0500 
0501 /* Link frequency configs */
0502 static const struct ov13b10_link_freq_config
0503             link_freq_configs[] = {
0504     {
0505         .pixels_per_line = OV13B10_PPL_560MHZ,
0506         .reg_list = {
0507             .num_of_regs = ARRAY_SIZE(mipi_data_rate_1120mbps),
0508             .regs = mipi_data_rate_1120mbps,
0509         }
0510     }
0511 };
0512 
0513 /* Mode configs */
0514 static const struct ov13b10_mode supported_modes[] = {
0515     {
0516         .width = 4208,
0517         .height = 3120,
0518         .vts_def = OV13B10_VTS_30FPS,
0519         .vts_min = OV13B10_VTS_30FPS,
0520         .reg_list = {
0521             .num_of_regs = ARRAY_SIZE(mode_4208x3120_regs),
0522             .regs = mode_4208x3120_regs,
0523         },
0524         .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
0525     },
0526     {
0527         .width = 4160,
0528         .height = 3120,
0529         .vts_def = OV13B10_VTS_30FPS,
0530         .vts_min = OV13B10_VTS_30FPS,
0531         .reg_list = {
0532             .num_of_regs = ARRAY_SIZE(mode_4160x3120_regs),
0533             .regs = mode_4160x3120_regs,
0534         },
0535         .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
0536     },
0537     {
0538         .width = 4160,
0539         .height = 2340,
0540         .vts_def = OV13B10_VTS_30FPS,
0541         .vts_min = OV13B10_VTS_30FPS,
0542         .reg_list = {
0543             .num_of_regs = ARRAY_SIZE(mode_4160x2340_regs),
0544             .regs = mode_4160x2340_regs,
0545         },
0546         .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
0547     },
0548     {
0549         .width = 2104,
0550         .height = 1560,
0551         .vts_def = OV13B10_VTS_60FPS,
0552         .vts_min = OV13B10_VTS_60FPS,
0553         .reg_list = {
0554             .num_of_regs = ARRAY_SIZE(mode_2104x1560_regs),
0555             .regs = mode_2104x1560_regs,
0556         },
0557         .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
0558     },
0559     {
0560         .width = 2080,
0561         .height = 1170,
0562         .vts_def = OV13B10_VTS_60FPS,
0563         .vts_min = OV13B10_VTS_60FPS,
0564         .reg_list = {
0565             .num_of_regs = ARRAY_SIZE(mode_2080x1170_regs),
0566             .regs = mode_2080x1170_regs,
0567         },
0568         .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
0569     }
0570 };
0571 
0572 struct ov13b10 {
0573     struct v4l2_subdev sd;
0574     struct media_pad pad;
0575 
0576     struct v4l2_ctrl_handler ctrl_handler;
0577     /* V4L2 Controls */
0578     struct v4l2_ctrl *link_freq;
0579     struct v4l2_ctrl *pixel_rate;
0580     struct v4l2_ctrl *vblank;
0581     struct v4l2_ctrl *hblank;
0582     struct v4l2_ctrl *exposure;
0583 
0584     /* Current mode */
0585     const struct ov13b10_mode *cur_mode;
0586 
0587     /* Mutex for serialized access */
0588     struct mutex mutex;
0589 
0590     /* Streaming on/off */
0591     bool streaming;
0592 };
0593 
0594 #define to_ov13b10(_sd) container_of(_sd, struct ov13b10, sd)
0595 
0596 /* Read registers up to 4 at a time */
0597 static int ov13b10_read_reg(struct ov13b10 *ov13b,
0598                 u16 reg, u32 len, u32 *val)
0599 {
0600     struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
0601     struct i2c_msg msgs[2];
0602     u8 *data_be_p;
0603     int ret;
0604     __be32 data_be = 0;
0605     __be16 reg_addr_be = cpu_to_be16(reg);
0606 
0607     if (len > 4)
0608         return -EINVAL;
0609 
0610     data_be_p = (u8 *)&data_be;
0611     /* Write register address */
0612     msgs[0].addr = client->addr;
0613     msgs[0].flags = 0;
0614     msgs[0].len = 2;
0615     msgs[0].buf = (u8 *)&reg_addr_be;
0616 
0617     /* Read data from register */
0618     msgs[1].addr = client->addr;
0619     msgs[1].flags = I2C_M_RD;
0620     msgs[1].len = len;
0621     msgs[1].buf = &data_be_p[4 - len];
0622 
0623     ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0624     if (ret != ARRAY_SIZE(msgs))
0625         return -EIO;
0626 
0627     *val = be32_to_cpu(data_be);
0628 
0629     return 0;
0630 }
0631 
0632 /* Write registers up to 4 at a time */
0633 static int ov13b10_write_reg(struct ov13b10 *ov13b,
0634                  u16 reg, u32 len, u32 __val)
0635 {
0636     struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
0637     int buf_i, val_i;
0638     u8 buf[6], *val_p;
0639     __be32 val;
0640 
0641     if (len > 4)
0642         return -EINVAL;
0643 
0644     buf[0] = reg >> 8;
0645     buf[1] = reg & 0xff;
0646 
0647     val = cpu_to_be32(__val);
0648     val_p = (u8 *)&val;
0649     buf_i = 2;
0650     val_i = 4 - len;
0651 
0652     while (val_i < 4)
0653         buf[buf_i++] = val_p[val_i++];
0654 
0655     if (i2c_master_send(client, buf, len + 2) != len + 2)
0656         return -EIO;
0657 
0658     return 0;
0659 }
0660 
0661 /* Write a list of registers */
0662 static int ov13b10_write_regs(struct ov13b10 *ov13b,
0663                   const struct ov13b10_reg *regs, u32 len)
0664 {
0665     struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
0666     int ret;
0667     u32 i;
0668 
0669     for (i = 0; i < len; i++) {
0670         ret = ov13b10_write_reg(ov13b, regs[i].address, 1,
0671                     regs[i].val);
0672         if (ret) {
0673             dev_err_ratelimited(&client->dev,
0674                         "Failed to write reg 0x%4.4x. error = %d\n",
0675                         regs[i].address, ret);
0676 
0677             return ret;
0678         }
0679     }
0680 
0681     return 0;
0682 }
0683 
0684 static int ov13b10_write_reg_list(struct ov13b10 *ov13b,
0685                   const struct ov13b10_reg_list *r_list)
0686 {
0687     return ov13b10_write_regs(ov13b, r_list->regs, r_list->num_of_regs);
0688 }
0689 
0690 /* Open sub-device */
0691 static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
0692 {
0693     const struct ov13b10_mode *default_mode = &supported_modes[0];
0694     struct ov13b10 *ov13b = to_ov13b10(sd);
0695     struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
0696                                     fh->state,
0697                                     0);
0698 
0699     mutex_lock(&ov13b->mutex);
0700 
0701     /* Initialize try_fmt */
0702     try_fmt->width = default_mode->width;
0703     try_fmt->height = default_mode->height;
0704     try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
0705     try_fmt->field = V4L2_FIELD_NONE;
0706 
0707     /* No crop or compose */
0708     mutex_unlock(&ov13b->mutex);
0709 
0710     return 0;
0711 }
0712 
0713 static int ov13b10_update_digital_gain(struct ov13b10 *ov13b, u32 d_gain)
0714 {
0715     int ret;
0716     u32 val;
0717 
0718     /*
0719      * 0x350C[7:6], 0x350B[7:0], 0x350A[1:0]
0720      */
0721 
0722     val = (d_gain & OV13B10_DGTL_GAIN_L_MASK) << OV13B10_DGTL_GAIN_L_SHIFT;
0723     ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_L,
0724                 OV13B10_REG_VALUE_08BIT, val);
0725     if (ret)
0726         return ret;
0727 
0728     val = (d_gain >> OV13B10_DGTL_GAIN_M_SHIFT) & OV13B10_DGTL_GAIN_M_MASK;
0729     ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_M,
0730                 OV13B10_REG_VALUE_08BIT, val);
0731     if (ret)
0732         return ret;
0733 
0734     val = (d_gain >> OV13B10_DGTL_GAIN_H_SHIFT) & OV13B10_DGTL_GAIN_H_MASK;
0735     ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_H,
0736                 OV13B10_REG_VALUE_08BIT, val);
0737 
0738     return ret;
0739 }
0740 
0741 static int ov13b10_enable_test_pattern(struct ov13b10 *ov13b, u32 pattern)
0742 {
0743     int ret;
0744     u32 val;
0745 
0746     ret = ov13b10_read_reg(ov13b, OV13B10_REG_TEST_PATTERN,
0747                    OV13B10_REG_VALUE_08BIT, &val);
0748     if (ret)
0749         return ret;
0750 
0751     if (pattern) {
0752         val &= OV13B10_TEST_PATTERN_MASK;
0753         val |= ((pattern - 1) << OV13B10_TEST_PATTERN_BAR_SHIFT) |
0754              OV13B10_TEST_PATTERN_ENABLE;
0755     } else {
0756         val &= ~OV13B10_TEST_PATTERN_ENABLE;
0757     }
0758 
0759     return ov13b10_write_reg(ov13b, OV13B10_REG_TEST_PATTERN,
0760                  OV13B10_REG_VALUE_08BIT, val);
0761 }
0762 
0763 static int ov13b10_set_ctrl_hflip(struct ov13b10 *ov13b, u32 ctrl_val)
0764 {
0765     int ret;
0766     u32 val;
0767 
0768     ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
0769                    OV13B10_REG_VALUE_08BIT, &val);
0770     if (ret)
0771         return ret;
0772 
0773     ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
0774                 OV13B10_REG_VALUE_08BIT,
0775                 ctrl_val ? val & ~BIT(3) : val);
0776 
0777     if (ret)
0778         return ret;
0779 
0780     ret = ov13b10_read_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
0781                    OV13B10_REG_VALUE_08BIT, &val);
0782     if (ret)
0783         return ret;
0784 
0785     /*
0786      * Applying cropping offset to reverse the change of Bayer order
0787      * after mirroring image
0788      */
0789     return ov13b10_write_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
0790                  OV13B10_REG_VALUE_08BIT,
0791                  ctrl_val ? ++val : val);
0792 }
0793 
0794 static int ov13b10_set_ctrl_vflip(struct ov13b10 *ov13b, u32 ctrl_val)
0795 {
0796     int ret;
0797     u32 val;
0798 
0799     ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
0800                    OV13B10_REG_VALUE_08BIT, &val);
0801     if (ret)
0802         return ret;
0803 
0804     ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
0805                 OV13B10_REG_VALUE_08BIT,
0806                 ctrl_val ? val | BIT(4) | BIT(5)  : val);
0807 
0808     if (ret)
0809         return ret;
0810 
0811     ret = ov13b10_read_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
0812                    OV13B10_REG_VALUE_08BIT, &val);
0813     if (ret)
0814         return ret;
0815 
0816     /*
0817      * Applying cropping offset to reverse the change of Bayer order
0818      * after flipping image
0819      */
0820     return ov13b10_write_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
0821                  OV13B10_REG_VALUE_08BIT,
0822                  ctrl_val ? --val : val);
0823 }
0824 
0825 static int ov13b10_set_ctrl(struct v4l2_ctrl *ctrl)
0826 {
0827     struct ov13b10 *ov13b = container_of(ctrl->handler,
0828                          struct ov13b10, ctrl_handler);
0829     struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
0830     s64 max;
0831     int ret;
0832 
0833     /* Propagate change of current control to all related controls */
0834     switch (ctrl->id) {
0835     case V4L2_CID_VBLANK:
0836         /* Update max exposure while meeting expected vblanking */
0837         max = ov13b->cur_mode->height + ctrl->val - 8;
0838         __v4l2_ctrl_modify_range(ov13b->exposure,
0839                      ov13b->exposure->minimum,
0840                      max, ov13b->exposure->step, max);
0841         break;
0842     }
0843 
0844     /*
0845      * Applying V4L2 control value only happens
0846      * when power is up for streaming
0847      */
0848     if (!pm_runtime_get_if_in_use(&client->dev))
0849         return 0;
0850 
0851     ret = 0;
0852     switch (ctrl->id) {
0853     case V4L2_CID_ANALOGUE_GAIN:
0854         ret = ov13b10_write_reg(ov13b, OV13B10_REG_ANALOG_GAIN,
0855                     OV13B10_REG_VALUE_16BIT,
0856                     ctrl->val << 1);
0857         break;
0858     case V4L2_CID_DIGITAL_GAIN:
0859         ret = ov13b10_update_digital_gain(ov13b, ctrl->val);
0860         break;
0861     case V4L2_CID_EXPOSURE:
0862         ret = ov13b10_write_reg(ov13b, OV13B10_REG_EXPOSURE,
0863                     OV13B10_REG_VALUE_24BIT,
0864                     ctrl->val);
0865         break;
0866     case V4L2_CID_VBLANK:
0867         ret = ov13b10_write_reg(ov13b, OV13B10_REG_VTS,
0868                     OV13B10_REG_VALUE_16BIT,
0869                     ov13b->cur_mode->height
0870                     + ctrl->val);
0871         break;
0872     case V4L2_CID_TEST_PATTERN:
0873         ret = ov13b10_enable_test_pattern(ov13b, ctrl->val);
0874         break;
0875     case V4L2_CID_HFLIP:
0876         ov13b10_set_ctrl_hflip(ov13b, ctrl->val);
0877         break;
0878     case V4L2_CID_VFLIP:
0879         ov13b10_set_ctrl_vflip(ov13b, ctrl->val);
0880         break;
0881     default:
0882         dev_info(&client->dev,
0883              "ctrl(id:0x%x,val:0x%x) is not handled\n",
0884              ctrl->id, ctrl->val);
0885         break;
0886     }
0887 
0888     pm_runtime_put(&client->dev);
0889 
0890     return ret;
0891 }
0892 
0893 static const struct v4l2_ctrl_ops ov13b10_ctrl_ops = {
0894     .s_ctrl = ov13b10_set_ctrl,
0895 };
0896 
0897 static int ov13b10_enum_mbus_code(struct v4l2_subdev *sd,
0898                   struct v4l2_subdev_state *sd_state,
0899                   struct v4l2_subdev_mbus_code_enum *code)
0900 {
0901     /* Only one bayer order(GRBG) is supported */
0902     if (code->index > 0)
0903         return -EINVAL;
0904 
0905     code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
0906 
0907     return 0;
0908 }
0909 
0910 static int ov13b10_enum_frame_size(struct v4l2_subdev *sd,
0911                    struct v4l2_subdev_state *sd_state,
0912                    struct v4l2_subdev_frame_size_enum *fse)
0913 {
0914     if (fse->index >= ARRAY_SIZE(supported_modes))
0915         return -EINVAL;
0916 
0917     if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
0918         return -EINVAL;
0919 
0920     fse->min_width = supported_modes[fse->index].width;
0921     fse->max_width = fse->min_width;
0922     fse->min_height = supported_modes[fse->index].height;
0923     fse->max_height = fse->min_height;
0924 
0925     return 0;
0926 }
0927 
0928 static void ov13b10_update_pad_format(const struct ov13b10_mode *mode,
0929                       struct v4l2_subdev_format *fmt)
0930 {
0931     fmt->format.width = mode->width;
0932     fmt->format.height = mode->height;
0933     fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
0934     fmt->format.field = V4L2_FIELD_NONE;
0935 }
0936 
0937 static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b,
0938                      struct v4l2_subdev_state *sd_state,
0939                      struct v4l2_subdev_format *fmt)
0940 {
0941     struct v4l2_mbus_framefmt *framefmt;
0942     struct v4l2_subdev *sd = &ov13b->sd;
0943 
0944     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0945         framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0946         fmt->format = *framefmt;
0947     } else {
0948         ov13b10_update_pad_format(ov13b->cur_mode, fmt);
0949     }
0950 
0951     return 0;
0952 }
0953 
0954 static int ov13b10_get_pad_format(struct v4l2_subdev *sd,
0955                   struct v4l2_subdev_state *sd_state,
0956                   struct v4l2_subdev_format *fmt)
0957 {
0958     struct ov13b10 *ov13b = to_ov13b10(sd);
0959     int ret;
0960 
0961     mutex_lock(&ov13b->mutex);
0962     ret = ov13b10_do_get_pad_format(ov13b, sd_state, fmt);
0963     mutex_unlock(&ov13b->mutex);
0964 
0965     return ret;
0966 }
0967 
0968 static int
0969 ov13b10_set_pad_format(struct v4l2_subdev *sd,
0970                struct v4l2_subdev_state *sd_state,
0971                struct v4l2_subdev_format *fmt)
0972 {
0973     struct ov13b10 *ov13b = to_ov13b10(sd);
0974     const struct ov13b10_mode *mode;
0975     struct v4l2_mbus_framefmt *framefmt;
0976     s32 vblank_def;
0977     s32 vblank_min;
0978     s64 h_blank;
0979     s64 pixel_rate;
0980     s64 link_freq;
0981 
0982     mutex_lock(&ov13b->mutex);
0983 
0984     /* Only one raw bayer(GRBG) order is supported */
0985     if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
0986         fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
0987 
0988     mode = v4l2_find_nearest_size(supported_modes,
0989                       ARRAY_SIZE(supported_modes),
0990                       width, height,
0991                       fmt->format.width, fmt->format.height);
0992     ov13b10_update_pad_format(mode, fmt);
0993     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0994         framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0995         *framefmt = fmt->format;
0996     } else {
0997         ov13b->cur_mode = mode;
0998         __v4l2_ctrl_s_ctrl(ov13b->link_freq, mode->link_freq_index);
0999         link_freq = link_freq_menu_items[mode->link_freq_index];
1000         pixel_rate = link_freq_to_pixel_rate(link_freq);
1001         __v4l2_ctrl_s_ctrl_int64(ov13b->pixel_rate, pixel_rate);
1002 
1003         /* Update limits and set FPS to default */
1004         vblank_def = ov13b->cur_mode->vts_def -
1005                  ov13b->cur_mode->height;
1006         vblank_min = ov13b->cur_mode->vts_min -
1007                  ov13b->cur_mode->height;
1008         __v4l2_ctrl_modify_range(ov13b->vblank, vblank_min,
1009                      OV13B10_VTS_MAX
1010                      - ov13b->cur_mode->height,
1011                      1,
1012                      vblank_def);
1013         __v4l2_ctrl_s_ctrl(ov13b->vblank, vblank_def);
1014         h_blank =
1015             link_freq_configs[mode->link_freq_index].pixels_per_line
1016              - ov13b->cur_mode->width;
1017         __v4l2_ctrl_modify_range(ov13b->hblank, h_blank,
1018                      h_blank, 1, h_blank);
1019     }
1020 
1021     mutex_unlock(&ov13b->mutex);
1022 
1023     return 0;
1024 }
1025 
1026 static int ov13b10_start_streaming(struct ov13b10 *ov13b)
1027 {
1028     struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1029     const struct ov13b10_reg_list *reg_list;
1030     int ret, link_freq_index;
1031 
1032     /* Get out of from software reset */
1033     ret = ov13b10_write_reg(ov13b, OV13B10_REG_SOFTWARE_RST,
1034                 OV13B10_REG_VALUE_08BIT, OV13B10_SOFTWARE_RST);
1035     if (ret) {
1036         dev_err(&client->dev, "%s failed to set powerup registers\n",
1037             __func__);
1038         return ret;
1039     }
1040 
1041     link_freq_index = ov13b->cur_mode->link_freq_index;
1042     reg_list = &link_freq_configs[link_freq_index].reg_list;
1043     ret = ov13b10_write_reg_list(ov13b, reg_list);
1044     if (ret) {
1045         dev_err(&client->dev, "%s failed to set plls\n", __func__);
1046         return ret;
1047     }
1048 
1049     /* Apply default values of current mode */
1050     reg_list = &ov13b->cur_mode->reg_list;
1051     ret = ov13b10_write_reg_list(ov13b, reg_list);
1052     if (ret) {
1053         dev_err(&client->dev, "%s failed to set mode\n", __func__);
1054         return ret;
1055     }
1056 
1057     /* Apply customized values from user */
1058     ret =  __v4l2_ctrl_handler_setup(ov13b->sd.ctrl_handler);
1059     if (ret)
1060         return ret;
1061 
1062     return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1063                  OV13B10_REG_VALUE_08BIT,
1064                  OV13B10_MODE_STREAMING);
1065 }
1066 
1067 /* Stop streaming */
1068 static int ov13b10_stop_streaming(struct ov13b10 *ov13b)
1069 {
1070     return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1071                  OV13B10_REG_VALUE_08BIT, OV13B10_MODE_STANDBY);
1072 }
1073 
1074 static int ov13b10_set_stream(struct v4l2_subdev *sd, int enable)
1075 {
1076     struct ov13b10 *ov13b = to_ov13b10(sd);
1077     struct i2c_client *client = v4l2_get_subdevdata(sd);
1078     int ret = 0;
1079 
1080     mutex_lock(&ov13b->mutex);
1081     if (ov13b->streaming == enable) {
1082         mutex_unlock(&ov13b->mutex);
1083         return 0;
1084     }
1085 
1086     if (enable) {
1087         ret = pm_runtime_resume_and_get(&client->dev);
1088         if (ret < 0)
1089             goto err_unlock;
1090 
1091         /*
1092          * Apply default & customized values
1093          * and then start streaming.
1094          */
1095         ret = ov13b10_start_streaming(ov13b);
1096         if (ret)
1097             goto err_rpm_put;
1098     } else {
1099         ov13b10_stop_streaming(ov13b);
1100         pm_runtime_put(&client->dev);
1101     }
1102 
1103     ov13b->streaming = enable;
1104     mutex_unlock(&ov13b->mutex);
1105 
1106     return ret;
1107 
1108 err_rpm_put:
1109     pm_runtime_put(&client->dev);
1110 err_unlock:
1111     mutex_unlock(&ov13b->mutex);
1112 
1113     return ret;
1114 }
1115 
1116 static int __maybe_unused ov13b10_suspend(struct device *dev)
1117 {
1118     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1119     struct ov13b10 *ov13b = to_ov13b10(sd);
1120 
1121     if (ov13b->streaming)
1122         ov13b10_stop_streaming(ov13b);
1123 
1124     return 0;
1125 }
1126 
1127 static int __maybe_unused ov13b10_resume(struct device *dev)
1128 {
1129     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1130     struct ov13b10 *ov13b = to_ov13b10(sd);
1131     int ret;
1132 
1133     if (ov13b->streaming) {
1134         ret = ov13b10_start_streaming(ov13b);
1135         if (ret)
1136             goto error;
1137     }
1138 
1139     return 0;
1140 
1141 error:
1142     ov13b10_stop_streaming(ov13b);
1143     ov13b->streaming = false;
1144     return ret;
1145 }
1146 
1147 /* Verify chip ID */
1148 static int ov13b10_identify_module(struct ov13b10 *ov13b)
1149 {
1150     struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1151     int ret;
1152     u32 val;
1153 
1154     ret = ov13b10_read_reg(ov13b, OV13B10_REG_CHIP_ID,
1155                    OV13B10_REG_VALUE_24BIT, &val);
1156     if (ret)
1157         return ret;
1158 
1159     if (val != OV13B10_CHIP_ID) {
1160         dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1161             OV13B10_CHIP_ID, val);
1162         return -EIO;
1163     }
1164 
1165     return 0;
1166 }
1167 
1168 static const struct v4l2_subdev_video_ops ov13b10_video_ops = {
1169     .s_stream = ov13b10_set_stream,
1170 };
1171 
1172 static const struct v4l2_subdev_pad_ops ov13b10_pad_ops = {
1173     .enum_mbus_code = ov13b10_enum_mbus_code,
1174     .get_fmt = ov13b10_get_pad_format,
1175     .set_fmt = ov13b10_set_pad_format,
1176     .enum_frame_size = ov13b10_enum_frame_size,
1177 };
1178 
1179 static const struct v4l2_subdev_ops ov13b10_subdev_ops = {
1180     .video = &ov13b10_video_ops,
1181     .pad = &ov13b10_pad_ops,
1182 };
1183 
1184 static const struct media_entity_operations ov13b10_subdev_entity_ops = {
1185     .link_validate = v4l2_subdev_link_validate,
1186 };
1187 
1188 static const struct v4l2_subdev_internal_ops ov13b10_internal_ops = {
1189     .open = ov13b10_open,
1190 };
1191 
1192 /* Initialize control handlers */
1193 static int ov13b10_init_controls(struct ov13b10 *ov13b)
1194 {
1195     struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1196     struct v4l2_fwnode_device_properties props;
1197     struct v4l2_ctrl_handler *ctrl_hdlr;
1198     s64 exposure_max;
1199     s64 vblank_def;
1200     s64 vblank_min;
1201     s64 hblank;
1202     s64 pixel_rate_min;
1203     s64 pixel_rate_max;
1204     const struct ov13b10_mode *mode;
1205     u32 max;
1206     int ret;
1207 
1208     ctrl_hdlr = &ov13b->ctrl_handler;
1209     ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1210     if (ret)
1211         return ret;
1212 
1213     mutex_init(&ov13b->mutex);
1214     ctrl_hdlr->lock = &ov13b->mutex;
1215     max = ARRAY_SIZE(link_freq_menu_items) - 1;
1216     ov13b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1217                           &ov13b10_ctrl_ops,
1218                           V4L2_CID_LINK_FREQ,
1219                           max,
1220                           0,
1221                           link_freq_menu_items);
1222     if (ov13b->link_freq)
1223         ov13b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1224 
1225     pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1226     pixel_rate_min = 0;
1227     /* By default, PIXEL_RATE is read only */
1228     ov13b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1229                           V4L2_CID_PIXEL_RATE,
1230                           pixel_rate_min, pixel_rate_max,
1231                           1, pixel_rate_max);
1232 
1233     mode = ov13b->cur_mode;
1234     vblank_def = mode->vts_def - mode->height;
1235     vblank_min = mode->vts_min - mode->height;
1236     ov13b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1237                       V4L2_CID_VBLANK,
1238                       vblank_min,
1239                       OV13B10_VTS_MAX - mode->height, 1,
1240                       vblank_def);
1241 
1242     hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1243          mode->width;
1244     ov13b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1245                       V4L2_CID_HBLANK,
1246                       hblank, hblank, 1, hblank);
1247     if (ov13b->hblank)
1248         ov13b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1249 
1250     exposure_max = mode->vts_def - 8;
1251     ov13b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1252                         V4L2_CID_EXPOSURE,
1253                         OV13B10_EXPOSURE_MIN,
1254                         exposure_max, OV13B10_EXPOSURE_STEP,
1255                         exposure_max);
1256 
1257     v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1258               OV13B10_ANA_GAIN_MIN, OV13B10_ANA_GAIN_MAX,
1259               OV13B10_ANA_GAIN_STEP, OV13B10_ANA_GAIN_DEFAULT);
1260 
1261     /* Digital gain */
1262     v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1263               OV13B10_DGTL_GAIN_MIN, OV13B10_DGTL_GAIN_MAX,
1264               OV13B10_DGTL_GAIN_STEP, OV13B10_DGTL_GAIN_DEFAULT);
1265 
1266     v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13b10_ctrl_ops,
1267                      V4L2_CID_TEST_PATTERN,
1268                      ARRAY_SIZE(ov13b10_test_pattern_menu) - 1,
1269                      0, 0, ov13b10_test_pattern_menu);
1270 
1271     v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1272               V4L2_CID_HFLIP, 0, 1, 1, 0);
1273     v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1274               V4L2_CID_VFLIP, 0, 1, 1, 0);
1275 
1276     if (ctrl_hdlr->error) {
1277         ret = ctrl_hdlr->error;
1278         dev_err(&client->dev, "%s control init failed (%d)\n",
1279             __func__, ret);
1280         goto error;
1281     }
1282 
1283     ret = v4l2_fwnode_device_parse(&client->dev, &props);
1284     if (ret)
1285         goto error;
1286 
1287     ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13b10_ctrl_ops,
1288                           &props);
1289     if (ret)
1290         goto error;
1291 
1292     ov13b->sd.ctrl_handler = ctrl_hdlr;
1293 
1294     return 0;
1295 
1296 error:
1297     v4l2_ctrl_handler_free(ctrl_hdlr);
1298     mutex_destroy(&ov13b->mutex);
1299 
1300     return ret;
1301 }
1302 
1303 static void ov13b10_free_controls(struct ov13b10 *ov13b)
1304 {
1305     v4l2_ctrl_handler_free(ov13b->sd.ctrl_handler);
1306     mutex_destroy(&ov13b->mutex);
1307 }
1308 
1309 static int ov13b10_check_hwcfg(struct device *dev)
1310 {
1311     struct v4l2_fwnode_endpoint bus_cfg = {
1312         .bus_type = V4L2_MBUS_CSI2_DPHY
1313     };
1314     struct fwnode_handle *ep;
1315     struct fwnode_handle *fwnode = dev_fwnode(dev);
1316     unsigned int i, j;
1317     int ret;
1318     u32 ext_clk;
1319 
1320     if (!fwnode)
1321         return -ENXIO;
1322 
1323     ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1324                        &ext_clk);
1325     if (ret) {
1326         dev_err(dev, "can't get clock frequency");
1327         return ret;
1328     }
1329 
1330     if (ext_clk != OV13B10_EXT_CLK) {
1331         dev_err(dev, "external clock %d is not supported",
1332             ext_clk);
1333         return -EINVAL;
1334     }
1335 
1336     ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1337     if (!ep)
1338         return -ENXIO;
1339 
1340     ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1341     fwnode_handle_put(ep);
1342     if (ret)
1343         return ret;
1344 
1345     if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV13B10_DATA_LANES) {
1346         dev_err(dev, "number of CSI2 data lanes %d is not supported",
1347             bus_cfg.bus.mipi_csi2.num_data_lanes);
1348         ret = -EINVAL;
1349         goto out_err;
1350     }
1351 
1352     if (!bus_cfg.nr_of_link_frequencies) {
1353         dev_err(dev, "no link frequencies defined");
1354         ret = -EINVAL;
1355         goto out_err;
1356     }
1357 
1358     for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1359         for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1360             if (link_freq_menu_items[i] ==
1361                 bus_cfg.link_frequencies[j])
1362                 break;
1363         }
1364 
1365         if (j == bus_cfg.nr_of_link_frequencies) {
1366             dev_err(dev, "no link frequency %lld supported",
1367                 link_freq_menu_items[i]);
1368             ret = -EINVAL;
1369             goto out_err;
1370         }
1371     }
1372 
1373 out_err:
1374     v4l2_fwnode_endpoint_free(&bus_cfg);
1375 
1376     return ret;
1377 }
1378 
1379 static int ov13b10_probe(struct i2c_client *client)
1380 {
1381     struct ov13b10 *ov13b;
1382     int ret;
1383 
1384     /* Check HW config */
1385     ret = ov13b10_check_hwcfg(&client->dev);
1386     if (ret) {
1387         dev_err(&client->dev, "failed to check hwcfg: %d", ret);
1388         return ret;
1389     }
1390 
1391     ov13b = devm_kzalloc(&client->dev, sizeof(*ov13b), GFP_KERNEL);
1392     if (!ov13b)
1393         return -ENOMEM;
1394 
1395     /* Initialize subdev */
1396     v4l2_i2c_subdev_init(&ov13b->sd, client, &ov13b10_subdev_ops);
1397 
1398     /* Check module identity */
1399     ret = ov13b10_identify_module(ov13b);
1400     if (ret) {
1401         dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1402         return ret;
1403     }
1404 
1405     /* Set default mode to max resolution */
1406     ov13b->cur_mode = &supported_modes[0];
1407 
1408     ret = ov13b10_init_controls(ov13b);
1409     if (ret)
1410         return ret;
1411 
1412     /* Initialize subdev */
1413     ov13b->sd.internal_ops = &ov13b10_internal_ops;
1414     ov13b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1415     ov13b->sd.entity.ops = &ov13b10_subdev_entity_ops;
1416     ov13b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1417 
1418     /* Initialize source pad */
1419     ov13b->pad.flags = MEDIA_PAD_FL_SOURCE;
1420     ret = media_entity_pads_init(&ov13b->sd.entity, 1, &ov13b->pad);
1421     if (ret) {
1422         dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1423         goto error_handler_free;
1424     }
1425 
1426     ret = v4l2_async_register_subdev_sensor(&ov13b->sd);
1427     if (ret < 0)
1428         goto error_media_entity;
1429 
1430     /*
1431      * Device is already turned on by i2c-core with ACPI domain PM.
1432      * Enable runtime PM and turn off the device.
1433      */
1434     pm_runtime_set_active(&client->dev);
1435     pm_runtime_enable(&client->dev);
1436     pm_runtime_idle(&client->dev);
1437 
1438     return 0;
1439 
1440 error_media_entity:
1441     media_entity_cleanup(&ov13b->sd.entity);
1442 
1443 error_handler_free:
1444     ov13b10_free_controls(ov13b);
1445     dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1446 
1447     return ret;
1448 }
1449 
1450 static int ov13b10_remove(struct i2c_client *client)
1451 {
1452     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1453     struct ov13b10 *ov13b = to_ov13b10(sd);
1454 
1455     v4l2_async_unregister_subdev(sd);
1456     media_entity_cleanup(&sd->entity);
1457     ov13b10_free_controls(ov13b);
1458 
1459     pm_runtime_disable(&client->dev);
1460 
1461     return 0;
1462 }
1463 
1464 static const struct dev_pm_ops ov13b10_pm_ops = {
1465     SET_SYSTEM_SLEEP_PM_OPS(ov13b10_suspend, ov13b10_resume)
1466 };
1467 
1468 #ifdef CONFIG_ACPI
1469 static const struct acpi_device_id ov13b10_acpi_ids[] = {
1470     {"OVTIDB10"},
1471     { /* sentinel */ }
1472 };
1473 
1474 MODULE_DEVICE_TABLE(acpi, ov13b10_acpi_ids);
1475 #endif
1476 
1477 static struct i2c_driver ov13b10_i2c_driver = {
1478     .driver = {
1479         .name = "ov13b10",
1480         .pm = &ov13b10_pm_ops,
1481         .acpi_match_table = ACPI_PTR(ov13b10_acpi_ids),
1482     },
1483     .probe_new = ov13b10_probe,
1484     .remove = ov13b10_remove,
1485 };
1486 
1487 module_i2c_driver(ov13b10_i2c_driver);
1488 
1489 MODULE_AUTHOR("Kao, Arec <arec.kao@intel.com>");
1490 MODULE_DESCRIPTION("Omnivision ov13b10 sensor driver");
1491 MODULE_LICENSE("GPL v2");
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