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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2017 Intel Corporation.
0003 
0004 #include <linux/acpi.h>
0005 #include <linux/i2c.h>
0006 #include <linux/module.h>
0007 #include <linux/pm_runtime.h>
0008 #include <media/v4l2-ctrls.h>
0009 #include <media/v4l2-device.h>
0010 #include <media/v4l2-event.h>
0011 #include <media/v4l2-fwnode.h>
0012 
0013 #define OV13858_REG_VALUE_08BIT     1
0014 #define OV13858_REG_VALUE_16BIT     2
0015 #define OV13858_REG_VALUE_24BIT     3
0016 
0017 #define OV13858_REG_MODE_SELECT     0x0100
0018 #define OV13858_MODE_STANDBY        0x00
0019 #define OV13858_MODE_STREAMING      0x01
0020 
0021 #define OV13858_REG_SOFTWARE_RST    0x0103
0022 #define OV13858_SOFTWARE_RST        0x01
0023 
0024 /* PLL1 generates PCLK and MIPI_PHY_CLK */
0025 #define OV13858_REG_PLL1_CTRL_0     0x0300
0026 #define OV13858_REG_PLL1_CTRL_1     0x0301
0027 #define OV13858_REG_PLL1_CTRL_2     0x0302
0028 #define OV13858_REG_PLL1_CTRL_3     0x0303
0029 #define OV13858_REG_PLL1_CTRL_4     0x0304
0030 #define OV13858_REG_PLL1_CTRL_5     0x0305
0031 
0032 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
0033 #define OV13858_REG_PLL2_CTRL_B     0x030b
0034 #define OV13858_REG_PLL2_CTRL_C     0x030c
0035 #define OV13858_REG_PLL2_CTRL_D     0x030d
0036 #define OV13858_REG_PLL2_CTRL_E     0x030e
0037 #define OV13858_REG_PLL2_CTRL_F     0x030f
0038 #define OV13858_REG_PLL2_CTRL_12    0x0312
0039 #define OV13858_REG_MIPI_SC_CTRL0   0x3016
0040 #define OV13858_REG_MIPI_SC_CTRL1   0x3022
0041 
0042 /* Chip ID */
0043 #define OV13858_REG_CHIP_ID     0x300a
0044 #define OV13858_CHIP_ID         0x00d855
0045 
0046 /* V_TIMING internal */
0047 #define OV13858_REG_VTS         0x380e
0048 #define OV13858_VTS_30FPS       0x0c8e /* 30 fps */
0049 #define OV13858_VTS_60FPS       0x0648 /* 60 fps */
0050 #define OV13858_VTS_MAX         0x7fff
0051 
0052 /* HBLANK control - read only */
0053 #define OV13858_PPL_270MHZ      2244
0054 #define OV13858_PPL_540MHZ      4488
0055 
0056 /* Exposure control */
0057 #define OV13858_REG_EXPOSURE        0x3500
0058 #define OV13858_EXPOSURE_MIN        4
0059 #define OV13858_EXPOSURE_STEP       1
0060 #define OV13858_EXPOSURE_DEFAULT    0x640
0061 
0062 /* Analog gain control */
0063 #define OV13858_REG_ANALOG_GAIN     0x3508
0064 #define OV13858_ANA_GAIN_MIN        0
0065 #define OV13858_ANA_GAIN_MAX        0x1fff
0066 #define OV13858_ANA_GAIN_STEP       1
0067 #define OV13858_ANA_GAIN_DEFAULT    0x80
0068 
0069 /* Digital gain control */
0070 #define OV13858_REG_B_MWB_GAIN      0x5100
0071 #define OV13858_REG_G_MWB_GAIN      0x5102
0072 #define OV13858_REG_R_MWB_GAIN      0x5104
0073 #define OV13858_DGTL_GAIN_MIN       0
0074 #define OV13858_DGTL_GAIN_MAX       16384   /* Max = 16 X */
0075 #define OV13858_DGTL_GAIN_DEFAULT   1024    /* Default gain = 1 X */
0076 #define OV13858_DGTL_GAIN_STEP      1   /* Each step = 1/1024 */
0077 
0078 /* Test Pattern Control */
0079 #define OV13858_REG_TEST_PATTERN    0x4503
0080 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
0081 #define OV13858_TEST_PATTERN_MASK   0xfc
0082 
0083 /* Number of frames to skip */
0084 #define OV13858_NUM_OF_SKIP_FRAMES  2
0085 
0086 struct ov13858_reg {
0087     u16 address;
0088     u8 val;
0089 };
0090 
0091 struct ov13858_reg_list {
0092     u32 num_of_regs;
0093     const struct ov13858_reg *regs;
0094 };
0095 
0096 /* Link frequency config */
0097 struct ov13858_link_freq_config {
0098     u32 pixels_per_line;
0099 
0100     /* PLL registers for this link frequency */
0101     struct ov13858_reg_list reg_list;
0102 };
0103 
0104 /* Mode : resolution and related config&values */
0105 struct ov13858_mode {
0106     /* Frame width */
0107     u32 width;
0108     /* Frame height */
0109     u32 height;
0110 
0111     /* V-timing */
0112     u32 vts_def;
0113     u32 vts_min;
0114 
0115     /* Index of Link frequency config to be used */
0116     u32 link_freq_index;
0117     /* Default register values */
0118     struct ov13858_reg_list reg_list;
0119 };
0120 
0121 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
0122 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
0123     /* PLL1 registers */
0124     {OV13858_REG_PLL1_CTRL_0, 0x07},
0125     {OV13858_REG_PLL1_CTRL_1, 0x01},
0126     {OV13858_REG_PLL1_CTRL_2, 0xc2},
0127     {OV13858_REG_PLL1_CTRL_3, 0x00},
0128     {OV13858_REG_PLL1_CTRL_4, 0x00},
0129     {OV13858_REG_PLL1_CTRL_5, 0x01},
0130 
0131     /* PLL2 registers */
0132     {OV13858_REG_PLL2_CTRL_B, 0x05},
0133     {OV13858_REG_PLL2_CTRL_C, 0x01},
0134     {OV13858_REG_PLL2_CTRL_D, 0x0e},
0135     {OV13858_REG_PLL2_CTRL_E, 0x05},
0136     {OV13858_REG_PLL2_CTRL_F, 0x01},
0137     {OV13858_REG_PLL2_CTRL_12, 0x01},
0138     {OV13858_REG_MIPI_SC_CTRL0, 0x72},
0139     {OV13858_REG_MIPI_SC_CTRL1, 0x01},
0140 };
0141 
0142 /*
0143  * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
0144  * 4 lanes
0145  */
0146 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
0147     /* PLL1 registers */
0148     {OV13858_REG_PLL1_CTRL_0, 0x07},
0149     {OV13858_REG_PLL1_CTRL_1, 0x01},
0150     {OV13858_REG_PLL1_CTRL_2, 0xc2},
0151     {OV13858_REG_PLL1_CTRL_3, 0x01},
0152     {OV13858_REG_PLL1_CTRL_4, 0x00},
0153     {OV13858_REG_PLL1_CTRL_5, 0x01},
0154 
0155     /* PLL2 registers */
0156     {OV13858_REG_PLL2_CTRL_B, 0x05},
0157     {OV13858_REG_PLL2_CTRL_C, 0x01},
0158     {OV13858_REG_PLL2_CTRL_D, 0x0e},
0159     {OV13858_REG_PLL2_CTRL_E, 0x05},
0160     {OV13858_REG_PLL2_CTRL_F, 0x01},
0161     {OV13858_REG_PLL2_CTRL_12, 0x01},
0162     {OV13858_REG_MIPI_SC_CTRL0, 0x72},
0163     {OV13858_REG_MIPI_SC_CTRL1, 0x01},
0164 };
0165 
0166 static const struct ov13858_reg mode_4224x3136_regs[] = {
0167     {0x3013, 0x32},
0168     {0x301b, 0xf0},
0169     {0x301f, 0xd0},
0170     {0x3106, 0x15},
0171     {0x3107, 0x23},
0172     {0x350a, 0x00},
0173     {0x350e, 0x00},
0174     {0x3510, 0x00},
0175     {0x3511, 0x02},
0176     {0x3512, 0x00},
0177     {0x3600, 0x2b},
0178     {0x3601, 0x52},
0179     {0x3602, 0x60},
0180     {0x3612, 0x05},
0181     {0x3613, 0xa4},
0182     {0x3620, 0x80},
0183     {0x3621, 0x10},
0184     {0x3622, 0x30},
0185     {0x3624, 0x1c},
0186     {0x3640, 0x10},
0187     {0x3641, 0x70},
0188     {0x3660, 0x04},
0189     {0x3661, 0x80},
0190     {0x3662, 0x12},
0191     {0x3664, 0x73},
0192     {0x3665, 0xa7},
0193     {0x366e, 0xff},
0194     {0x366f, 0xf4},
0195     {0x3674, 0x00},
0196     {0x3679, 0x0c},
0197     {0x367f, 0x01},
0198     {0x3680, 0x0c},
0199     {0x3681, 0x50},
0200     {0x3682, 0x50},
0201     {0x3683, 0xa9},
0202     {0x3684, 0xa9},
0203     {0x3709, 0x5f},
0204     {0x3714, 0x24},
0205     {0x371a, 0x3e},
0206     {0x3737, 0x04},
0207     {0x3738, 0xcc},
0208     {0x3739, 0x12},
0209     {0x373d, 0x26},
0210     {0x3764, 0x20},
0211     {0x3765, 0x20},
0212     {0x37a1, 0x36},
0213     {0x37a8, 0x3b},
0214     {0x37ab, 0x31},
0215     {0x37c2, 0x04},
0216     {0x37c3, 0xf1},
0217     {0x37c5, 0x00},
0218     {0x37d8, 0x03},
0219     {0x37d9, 0x0c},
0220     {0x37da, 0xc2},
0221     {0x37dc, 0x02},
0222     {0x37e0, 0x00},
0223     {0x37e1, 0x0a},
0224     {0x37e2, 0x14},
0225     {0x37e3, 0x04},
0226     {0x37e4, 0x2a},
0227     {0x37e5, 0x03},
0228     {0x37e6, 0x04},
0229     {0x3800, 0x00},
0230     {0x3801, 0x00},
0231     {0x3802, 0x00},
0232     {0x3803, 0x08},
0233     {0x3804, 0x10},
0234     {0x3805, 0x9f},
0235     {0x3806, 0x0c},
0236     {0x3807, 0x57},
0237     {0x3808, 0x10},
0238     {0x3809, 0x80},
0239     {0x380a, 0x0c},
0240     {0x380b, 0x40},
0241     {0x380c, 0x04},
0242     {0x380d, 0x62},
0243     {0x380e, 0x0c},
0244     {0x380f, 0x8e},
0245     {0x3811, 0x04},
0246     {0x3813, 0x05},
0247     {0x3814, 0x01},
0248     {0x3815, 0x01},
0249     {0x3816, 0x01},
0250     {0x3817, 0x01},
0251     {0x3820, 0xa8},
0252     {0x3821, 0x00},
0253     {0x3822, 0xc2},
0254     {0x3823, 0x18},
0255     {0x3826, 0x11},
0256     {0x3827, 0x1c},
0257     {0x3829, 0x03},
0258     {0x3832, 0x00},
0259     {0x3c80, 0x00},
0260     {0x3c87, 0x01},
0261     {0x3c8c, 0x19},
0262     {0x3c8d, 0x1c},
0263     {0x3c90, 0x00},
0264     {0x3c91, 0x00},
0265     {0x3c92, 0x00},
0266     {0x3c93, 0x00},
0267     {0x3c94, 0x40},
0268     {0x3c95, 0x54},
0269     {0x3c96, 0x34},
0270     {0x3c97, 0x04},
0271     {0x3c98, 0x00},
0272     {0x3d8c, 0x73},
0273     {0x3d8d, 0xc0},
0274     {0x3f00, 0x0b},
0275     {0x3f03, 0x00},
0276     {0x4001, 0xe0},
0277     {0x4008, 0x00},
0278     {0x4009, 0x0f},
0279     {0x4011, 0xf0},
0280     {0x4017, 0x08},
0281     {0x4050, 0x04},
0282     {0x4051, 0x0b},
0283     {0x4052, 0x00},
0284     {0x4053, 0x80},
0285     {0x4054, 0x00},
0286     {0x4055, 0x80},
0287     {0x4056, 0x00},
0288     {0x4057, 0x80},
0289     {0x4058, 0x00},
0290     {0x4059, 0x80},
0291     {0x405e, 0x20},
0292     {0x4500, 0x07},
0293     {0x4503, 0x00},
0294     {0x450a, 0x04},
0295     {0x4809, 0x04},
0296     {0x480c, 0x12},
0297     {0x481f, 0x30},
0298     {0x4833, 0x10},
0299     {0x4837, 0x0e},
0300     {0x4902, 0x01},
0301     {0x4d00, 0x03},
0302     {0x4d01, 0xc9},
0303     {0x4d02, 0xbc},
0304     {0x4d03, 0xd7},
0305     {0x4d04, 0xf0},
0306     {0x4d05, 0xa2},
0307     {0x5000, 0xfd},
0308     {0x5001, 0x01},
0309     {0x5040, 0x39},
0310     {0x5041, 0x10},
0311     {0x5042, 0x10},
0312     {0x5043, 0x84},
0313     {0x5044, 0x62},
0314     {0x5180, 0x00},
0315     {0x5181, 0x10},
0316     {0x5182, 0x02},
0317     {0x5183, 0x0f},
0318     {0x5200, 0x1b},
0319     {0x520b, 0x07},
0320     {0x520c, 0x0f},
0321     {0x5300, 0x04},
0322     {0x5301, 0x0c},
0323     {0x5302, 0x0c},
0324     {0x5303, 0x0f},
0325     {0x5304, 0x00},
0326     {0x5305, 0x70},
0327     {0x5306, 0x00},
0328     {0x5307, 0x80},
0329     {0x5308, 0x00},
0330     {0x5309, 0xa5},
0331     {0x530a, 0x00},
0332     {0x530b, 0xd3},
0333     {0x530c, 0x00},
0334     {0x530d, 0xf0},
0335     {0x530e, 0x01},
0336     {0x530f, 0x10},
0337     {0x5310, 0x01},
0338     {0x5311, 0x20},
0339     {0x5312, 0x01},
0340     {0x5313, 0x20},
0341     {0x5314, 0x01},
0342     {0x5315, 0x20},
0343     {0x5316, 0x08},
0344     {0x5317, 0x08},
0345     {0x5318, 0x10},
0346     {0x5319, 0x88},
0347     {0x531a, 0x88},
0348     {0x531b, 0xa9},
0349     {0x531c, 0xaa},
0350     {0x531d, 0x0a},
0351     {0x5405, 0x02},
0352     {0x5406, 0x67},
0353     {0x5407, 0x01},
0354     {0x5408, 0x4a},
0355 };
0356 
0357 static const struct ov13858_reg mode_2112x1568_regs[] = {
0358     {0x3013, 0x32},
0359     {0x301b, 0xf0},
0360     {0x301f, 0xd0},
0361     {0x3106, 0x15},
0362     {0x3107, 0x23},
0363     {0x350a, 0x00},
0364     {0x350e, 0x00},
0365     {0x3510, 0x00},
0366     {0x3511, 0x02},
0367     {0x3512, 0x00},
0368     {0x3600, 0x2b},
0369     {0x3601, 0x52},
0370     {0x3602, 0x60},
0371     {0x3612, 0x05},
0372     {0x3613, 0xa4},
0373     {0x3620, 0x80},
0374     {0x3621, 0x10},
0375     {0x3622, 0x30},
0376     {0x3624, 0x1c},
0377     {0x3640, 0x10},
0378     {0x3641, 0x70},
0379     {0x3660, 0x04},
0380     {0x3661, 0x80},
0381     {0x3662, 0x10},
0382     {0x3664, 0x73},
0383     {0x3665, 0xa7},
0384     {0x366e, 0xff},
0385     {0x366f, 0xf4},
0386     {0x3674, 0x00},
0387     {0x3679, 0x0c},
0388     {0x367f, 0x01},
0389     {0x3680, 0x0c},
0390     {0x3681, 0x50},
0391     {0x3682, 0x50},
0392     {0x3683, 0xa9},
0393     {0x3684, 0xa9},
0394     {0x3709, 0x5f},
0395     {0x3714, 0x28},
0396     {0x371a, 0x3e},
0397     {0x3737, 0x08},
0398     {0x3738, 0xcc},
0399     {0x3739, 0x20},
0400     {0x373d, 0x26},
0401     {0x3764, 0x20},
0402     {0x3765, 0x20},
0403     {0x37a1, 0x36},
0404     {0x37a8, 0x3b},
0405     {0x37ab, 0x31},
0406     {0x37c2, 0x14},
0407     {0x37c3, 0xf1},
0408     {0x37c5, 0x00},
0409     {0x37d8, 0x03},
0410     {0x37d9, 0x0c},
0411     {0x37da, 0xc2},
0412     {0x37dc, 0x02},
0413     {0x37e0, 0x00},
0414     {0x37e1, 0x0a},
0415     {0x37e2, 0x14},
0416     {0x37e3, 0x08},
0417     {0x37e4, 0x38},
0418     {0x37e5, 0x03},
0419     {0x37e6, 0x08},
0420     {0x3800, 0x00},
0421     {0x3801, 0x00},
0422     {0x3802, 0x00},
0423     {0x3803, 0x00},
0424     {0x3804, 0x10},
0425     {0x3805, 0x9f},
0426     {0x3806, 0x0c},
0427     {0x3807, 0x5f},
0428     {0x3808, 0x08},
0429     {0x3809, 0x40},
0430     {0x380a, 0x06},
0431     {0x380b, 0x20},
0432     {0x380c, 0x04},
0433     {0x380d, 0x62},
0434     {0x380e, 0x0c},
0435     {0x380f, 0x8e},
0436     {0x3811, 0x04},
0437     {0x3813, 0x05},
0438     {0x3814, 0x03},
0439     {0x3815, 0x01},
0440     {0x3816, 0x03},
0441     {0x3817, 0x01},
0442     {0x3820, 0xab},
0443     {0x3821, 0x00},
0444     {0x3822, 0xc2},
0445     {0x3823, 0x18},
0446     {0x3826, 0x04},
0447     {0x3827, 0x90},
0448     {0x3829, 0x07},
0449     {0x3832, 0x00},
0450     {0x3c80, 0x00},
0451     {0x3c87, 0x01},
0452     {0x3c8c, 0x19},
0453     {0x3c8d, 0x1c},
0454     {0x3c90, 0x00},
0455     {0x3c91, 0x00},
0456     {0x3c92, 0x00},
0457     {0x3c93, 0x00},
0458     {0x3c94, 0x40},
0459     {0x3c95, 0x54},
0460     {0x3c96, 0x34},
0461     {0x3c97, 0x04},
0462     {0x3c98, 0x00},
0463     {0x3d8c, 0x73},
0464     {0x3d8d, 0xc0},
0465     {0x3f00, 0x0b},
0466     {0x3f03, 0x00},
0467     {0x4001, 0xe0},
0468     {0x4008, 0x00},
0469     {0x4009, 0x0d},
0470     {0x4011, 0xf0},
0471     {0x4017, 0x08},
0472     {0x4050, 0x04},
0473     {0x4051, 0x0b},
0474     {0x4052, 0x00},
0475     {0x4053, 0x80},
0476     {0x4054, 0x00},
0477     {0x4055, 0x80},
0478     {0x4056, 0x00},
0479     {0x4057, 0x80},
0480     {0x4058, 0x00},
0481     {0x4059, 0x80},
0482     {0x405e, 0x20},
0483     {0x4500, 0x07},
0484     {0x4503, 0x00},
0485     {0x450a, 0x04},
0486     {0x4809, 0x04},
0487     {0x480c, 0x12},
0488     {0x481f, 0x30},
0489     {0x4833, 0x10},
0490     {0x4837, 0x1c},
0491     {0x4902, 0x01},
0492     {0x4d00, 0x03},
0493     {0x4d01, 0xc9},
0494     {0x4d02, 0xbc},
0495     {0x4d03, 0xd7},
0496     {0x4d04, 0xf0},
0497     {0x4d05, 0xa2},
0498     {0x5000, 0xfd},
0499     {0x5001, 0x01},
0500     {0x5040, 0x39},
0501     {0x5041, 0x10},
0502     {0x5042, 0x10},
0503     {0x5043, 0x84},
0504     {0x5044, 0x62},
0505     {0x5180, 0x00},
0506     {0x5181, 0x10},
0507     {0x5182, 0x02},
0508     {0x5183, 0x0f},
0509     {0x5200, 0x1b},
0510     {0x520b, 0x07},
0511     {0x520c, 0x0f},
0512     {0x5300, 0x04},
0513     {0x5301, 0x0c},
0514     {0x5302, 0x0c},
0515     {0x5303, 0x0f},
0516     {0x5304, 0x00},
0517     {0x5305, 0x70},
0518     {0x5306, 0x00},
0519     {0x5307, 0x80},
0520     {0x5308, 0x00},
0521     {0x5309, 0xa5},
0522     {0x530a, 0x00},
0523     {0x530b, 0xd3},
0524     {0x530c, 0x00},
0525     {0x530d, 0xf0},
0526     {0x530e, 0x01},
0527     {0x530f, 0x10},
0528     {0x5310, 0x01},
0529     {0x5311, 0x20},
0530     {0x5312, 0x01},
0531     {0x5313, 0x20},
0532     {0x5314, 0x01},
0533     {0x5315, 0x20},
0534     {0x5316, 0x08},
0535     {0x5317, 0x08},
0536     {0x5318, 0x10},
0537     {0x5319, 0x88},
0538     {0x531a, 0x88},
0539     {0x531b, 0xa9},
0540     {0x531c, 0xaa},
0541     {0x531d, 0x0a},
0542     {0x5405, 0x02},
0543     {0x5406, 0x67},
0544     {0x5407, 0x01},
0545     {0x5408, 0x4a},
0546 };
0547 
0548 static const struct ov13858_reg mode_2112x1188_regs[] = {
0549     {0x3013, 0x32},
0550     {0x301b, 0xf0},
0551     {0x301f, 0xd0},
0552     {0x3106, 0x15},
0553     {0x3107, 0x23},
0554     {0x350a, 0x00},
0555     {0x350e, 0x00},
0556     {0x3510, 0x00},
0557     {0x3511, 0x02},
0558     {0x3512, 0x00},
0559     {0x3600, 0x2b},
0560     {0x3601, 0x52},
0561     {0x3602, 0x60},
0562     {0x3612, 0x05},
0563     {0x3613, 0xa4},
0564     {0x3620, 0x80},
0565     {0x3621, 0x10},
0566     {0x3622, 0x30},
0567     {0x3624, 0x1c},
0568     {0x3640, 0x10},
0569     {0x3641, 0x70},
0570     {0x3660, 0x04},
0571     {0x3661, 0x80},
0572     {0x3662, 0x10},
0573     {0x3664, 0x73},
0574     {0x3665, 0xa7},
0575     {0x366e, 0xff},
0576     {0x366f, 0xf4},
0577     {0x3674, 0x00},
0578     {0x3679, 0x0c},
0579     {0x367f, 0x01},
0580     {0x3680, 0x0c},
0581     {0x3681, 0x50},
0582     {0x3682, 0x50},
0583     {0x3683, 0xa9},
0584     {0x3684, 0xa9},
0585     {0x3709, 0x5f},
0586     {0x3714, 0x28},
0587     {0x371a, 0x3e},
0588     {0x3737, 0x08},
0589     {0x3738, 0xcc},
0590     {0x3739, 0x20},
0591     {0x373d, 0x26},
0592     {0x3764, 0x20},
0593     {0x3765, 0x20},
0594     {0x37a1, 0x36},
0595     {0x37a8, 0x3b},
0596     {0x37ab, 0x31},
0597     {0x37c2, 0x14},
0598     {0x37c3, 0xf1},
0599     {0x37c5, 0x00},
0600     {0x37d8, 0x03},
0601     {0x37d9, 0x0c},
0602     {0x37da, 0xc2},
0603     {0x37dc, 0x02},
0604     {0x37e0, 0x00},
0605     {0x37e1, 0x0a},
0606     {0x37e2, 0x14},
0607     {0x37e3, 0x08},
0608     {0x37e4, 0x38},
0609     {0x37e5, 0x03},
0610     {0x37e6, 0x08},
0611     {0x3800, 0x00},
0612     {0x3801, 0x00},
0613     {0x3802, 0x01},
0614     {0x3803, 0x84},
0615     {0x3804, 0x10},
0616     {0x3805, 0x9f},
0617     {0x3806, 0x0a},
0618     {0x3807, 0xd3},
0619     {0x3808, 0x08},
0620     {0x3809, 0x40},
0621     {0x380a, 0x04},
0622     {0x380b, 0xa4},
0623     {0x380c, 0x04},
0624     {0x380d, 0x62},
0625     {0x380e, 0x0c},
0626     {0x380f, 0x8e},
0627     {0x3811, 0x08},
0628     {0x3813, 0x03},
0629     {0x3814, 0x03},
0630     {0x3815, 0x01},
0631     {0x3816, 0x03},
0632     {0x3817, 0x01},
0633     {0x3820, 0xab},
0634     {0x3821, 0x00},
0635     {0x3822, 0xc2},
0636     {0x3823, 0x18},
0637     {0x3826, 0x04},
0638     {0x3827, 0x90},
0639     {0x3829, 0x07},
0640     {0x3832, 0x00},
0641     {0x3c80, 0x00},
0642     {0x3c87, 0x01},
0643     {0x3c8c, 0x19},
0644     {0x3c8d, 0x1c},
0645     {0x3c90, 0x00},
0646     {0x3c91, 0x00},
0647     {0x3c92, 0x00},
0648     {0x3c93, 0x00},
0649     {0x3c94, 0x40},
0650     {0x3c95, 0x54},
0651     {0x3c96, 0x34},
0652     {0x3c97, 0x04},
0653     {0x3c98, 0x00},
0654     {0x3d8c, 0x73},
0655     {0x3d8d, 0xc0},
0656     {0x3f00, 0x0b},
0657     {0x3f03, 0x00},
0658     {0x4001, 0xe0},
0659     {0x4008, 0x00},
0660     {0x4009, 0x0d},
0661     {0x4011, 0xf0},
0662     {0x4017, 0x08},
0663     {0x4050, 0x04},
0664     {0x4051, 0x0b},
0665     {0x4052, 0x00},
0666     {0x4053, 0x80},
0667     {0x4054, 0x00},
0668     {0x4055, 0x80},
0669     {0x4056, 0x00},
0670     {0x4057, 0x80},
0671     {0x4058, 0x00},
0672     {0x4059, 0x80},
0673     {0x405e, 0x20},
0674     {0x4500, 0x07},
0675     {0x4503, 0x00},
0676     {0x450a, 0x04},
0677     {0x4809, 0x04},
0678     {0x480c, 0x12},
0679     {0x481f, 0x30},
0680     {0x4833, 0x10},
0681     {0x4837, 0x1c},
0682     {0x4902, 0x01},
0683     {0x4d00, 0x03},
0684     {0x4d01, 0xc9},
0685     {0x4d02, 0xbc},
0686     {0x4d03, 0xd7},
0687     {0x4d04, 0xf0},
0688     {0x4d05, 0xa2},
0689     {0x5000, 0xfd},
0690     {0x5001, 0x01},
0691     {0x5040, 0x39},
0692     {0x5041, 0x10},
0693     {0x5042, 0x10},
0694     {0x5043, 0x84},
0695     {0x5044, 0x62},
0696     {0x5180, 0x00},
0697     {0x5181, 0x10},
0698     {0x5182, 0x02},
0699     {0x5183, 0x0f},
0700     {0x5200, 0x1b},
0701     {0x520b, 0x07},
0702     {0x520c, 0x0f},
0703     {0x5300, 0x04},
0704     {0x5301, 0x0c},
0705     {0x5302, 0x0c},
0706     {0x5303, 0x0f},
0707     {0x5304, 0x00},
0708     {0x5305, 0x70},
0709     {0x5306, 0x00},
0710     {0x5307, 0x80},
0711     {0x5308, 0x00},
0712     {0x5309, 0xa5},
0713     {0x530a, 0x00},
0714     {0x530b, 0xd3},
0715     {0x530c, 0x00},
0716     {0x530d, 0xf0},
0717     {0x530e, 0x01},
0718     {0x530f, 0x10},
0719     {0x5310, 0x01},
0720     {0x5311, 0x20},
0721     {0x5312, 0x01},
0722     {0x5313, 0x20},
0723     {0x5314, 0x01},
0724     {0x5315, 0x20},
0725     {0x5316, 0x08},
0726     {0x5317, 0x08},
0727     {0x5318, 0x10},
0728     {0x5319, 0x88},
0729     {0x531a, 0x88},
0730     {0x531b, 0xa9},
0731     {0x531c, 0xaa},
0732     {0x531d, 0x0a},
0733     {0x5405, 0x02},
0734     {0x5406, 0x67},
0735     {0x5407, 0x01},
0736     {0x5408, 0x4a},
0737 };
0738 
0739 static const struct ov13858_reg mode_1056x784_regs[] = {
0740     {0x3013, 0x32},
0741     {0x301b, 0xf0},
0742     {0x301f, 0xd0},
0743     {0x3106, 0x15},
0744     {0x3107, 0x23},
0745     {0x350a, 0x00},
0746     {0x350e, 0x00},
0747     {0x3510, 0x00},
0748     {0x3511, 0x02},
0749     {0x3512, 0x00},
0750     {0x3600, 0x2b},
0751     {0x3601, 0x52},
0752     {0x3602, 0x60},
0753     {0x3612, 0x05},
0754     {0x3613, 0xa4},
0755     {0x3620, 0x80},
0756     {0x3621, 0x10},
0757     {0x3622, 0x30},
0758     {0x3624, 0x1c},
0759     {0x3640, 0x10},
0760     {0x3641, 0x70},
0761     {0x3660, 0x04},
0762     {0x3661, 0x80},
0763     {0x3662, 0x08},
0764     {0x3664, 0x73},
0765     {0x3665, 0xa7},
0766     {0x366e, 0xff},
0767     {0x366f, 0xf4},
0768     {0x3674, 0x00},
0769     {0x3679, 0x0c},
0770     {0x367f, 0x01},
0771     {0x3680, 0x0c},
0772     {0x3681, 0x50},
0773     {0x3682, 0x50},
0774     {0x3683, 0xa9},
0775     {0x3684, 0xa9},
0776     {0x3709, 0x5f},
0777     {0x3714, 0x30},
0778     {0x371a, 0x3e},
0779     {0x3737, 0x08},
0780     {0x3738, 0xcc},
0781     {0x3739, 0x20},
0782     {0x373d, 0x26},
0783     {0x3764, 0x20},
0784     {0x3765, 0x20},
0785     {0x37a1, 0x36},
0786     {0x37a8, 0x3b},
0787     {0x37ab, 0x31},
0788     {0x37c2, 0x2c},
0789     {0x37c3, 0xf1},
0790     {0x37c5, 0x00},
0791     {0x37d8, 0x03},
0792     {0x37d9, 0x06},
0793     {0x37da, 0xc2},
0794     {0x37dc, 0x02},
0795     {0x37e0, 0x00},
0796     {0x37e1, 0x0a},
0797     {0x37e2, 0x14},
0798     {0x37e3, 0x08},
0799     {0x37e4, 0x36},
0800     {0x37e5, 0x03},
0801     {0x37e6, 0x08},
0802     {0x3800, 0x00},
0803     {0x3801, 0x00},
0804     {0x3802, 0x00},
0805     {0x3803, 0x00},
0806     {0x3804, 0x10},
0807     {0x3805, 0x9f},
0808     {0x3806, 0x0c},
0809     {0x3807, 0x5f},
0810     {0x3808, 0x04},
0811     {0x3809, 0x20},
0812     {0x380a, 0x03},
0813     {0x380b, 0x10},
0814     {0x380c, 0x04},
0815     {0x380d, 0x62},
0816     {0x380e, 0x0c},
0817     {0x380f, 0x8e},
0818     {0x3811, 0x04},
0819     {0x3813, 0x05},
0820     {0x3814, 0x07},
0821     {0x3815, 0x01},
0822     {0x3816, 0x07},
0823     {0x3817, 0x01},
0824     {0x3820, 0xac},
0825     {0x3821, 0x00},
0826     {0x3822, 0xc2},
0827     {0x3823, 0x18},
0828     {0x3826, 0x04},
0829     {0x3827, 0x48},
0830     {0x3829, 0x03},
0831     {0x3832, 0x00},
0832     {0x3c80, 0x00},
0833     {0x3c87, 0x01},
0834     {0x3c8c, 0x19},
0835     {0x3c8d, 0x1c},
0836     {0x3c90, 0x00},
0837     {0x3c91, 0x00},
0838     {0x3c92, 0x00},
0839     {0x3c93, 0x00},
0840     {0x3c94, 0x40},
0841     {0x3c95, 0x54},
0842     {0x3c96, 0x34},
0843     {0x3c97, 0x04},
0844     {0x3c98, 0x00},
0845     {0x3d8c, 0x73},
0846     {0x3d8d, 0xc0},
0847     {0x3f00, 0x0b},
0848     {0x3f03, 0x00},
0849     {0x4001, 0xe0},
0850     {0x4008, 0x00},
0851     {0x4009, 0x05},
0852     {0x4011, 0xf0},
0853     {0x4017, 0x08},
0854     {0x4050, 0x02},
0855     {0x4051, 0x05},
0856     {0x4052, 0x00},
0857     {0x4053, 0x80},
0858     {0x4054, 0x00},
0859     {0x4055, 0x80},
0860     {0x4056, 0x00},
0861     {0x4057, 0x80},
0862     {0x4058, 0x00},
0863     {0x4059, 0x80},
0864     {0x405e, 0x20},
0865     {0x4500, 0x07},
0866     {0x4503, 0x00},
0867     {0x450a, 0x04},
0868     {0x4809, 0x04},
0869     {0x480c, 0x12},
0870     {0x481f, 0x30},
0871     {0x4833, 0x10},
0872     {0x4837, 0x1e},
0873     {0x4902, 0x02},
0874     {0x4d00, 0x03},
0875     {0x4d01, 0xc9},
0876     {0x4d02, 0xbc},
0877     {0x4d03, 0xd7},
0878     {0x4d04, 0xf0},
0879     {0x4d05, 0xa2},
0880     {0x5000, 0xfd},
0881     {0x5001, 0x01},
0882     {0x5040, 0x39},
0883     {0x5041, 0x10},
0884     {0x5042, 0x10},
0885     {0x5043, 0x84},
0886     {0x5044, 0x62},
0887     {0x5180, 0x00},
0888     {0x5181, 0x10},
0889     {0x5182, 0x02},
0890     {0x5183, 0x0f},
0891     {0x5200, 0x1b},
0892     {0x520b, 0x07},
0893     {0x520c, 0x0f},
0894     {0x5300, 0x04},
0895     {0x5301, 0x0c},
0896     {0x5302, 0x0c},
0897     {0x5303, 0x0f},
0898     {0x5304, 0x00},
0899     {0x5305, 0x70},
0900     {0x5306, 0x00},
0901     {0x5307, 0x80},
0902     {0x5308, 0x00},
0903     {0x5309, 0xa5},
0904     {0x530a, 0x00},
0905     {0x530b, 0xd3},
0906     {0x530c, 0x00},
0907     {0x530d, 0xf0},
0908     {0x530e, 0x01},
0909     {0x530f, 0x10},
0910     {0x5310, 0x01},
0911     {0x5311, 0x20},
0912     {0x5312, 0x01},
0913     {0x5313, 0x20},
0914     {0x5314, 0x01},
0915     {0x5315, 0x20},
0916     {0x5316, 0x08},
0917     {0x5317, 0x08},
0918     {0x5318, 0x10},
0919     {0x5319, 0x88},
0920     {0x531a, 0x88},
0921     {0x531b, 0xa9},
0922     {0x531c, 0xaa},
0923     {0x531d, 0x0a},
0924     {0x5405, 0x02},
0925     {0x5406, 0x67},
0926     {0x5407, 0x01},
0927     {0x5408, 0x4a},
0928 };
0929 
0930 static const char * const ov13858_test_pattern_menu[] = {
0931     "Disabled",
0932     "Vertical Color Bar Type 1",
0933     "Vertical Color Bar Type 2",
0934     "Vertical Color Bar Type 3",
0935     "Vertical Color Bar Type 4"
0936 };
0937 
0938 /* Configurations for supported link frequencies */
0939 #define OV13858_NUM_OF_LINK_FREQS   2
0940 #define OV13858_LINK_FREQ_540MHZ    540000000ULL
0941 #define OV13858_LINK_FREQ_270MHZ    270000000ULL
0942 #define OV13858_LINK_FREQ_INDEX_0   0
0943 #define OV13858_LINK_FREQ_INDEX_1   1
0944 
0945 /*
0946  * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
0947  * data rate => double data rate; number of lanes => 4; bits per pixel => 10
0948  */
0949 static u64 link_freq_to_pixel_rate(u64 f)
0950 {
0951     f *= 2 * 4;
0952     do_div(f, 10);
0953 
0954     return f;
0955 }
0956 
0957 /* Menu items for LINK_FREQ V4L2 control */
0958 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
0959     OV13858_LINK_FREQ_540MHZ,
0960     OV13858_LINK_FREQ_270MHZ
0961 };
0962 
0963 /* Link frequency configs */
0964 static const struct ov13858_link_freq_config
0965             link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
0966     {
0967         .pixels_per_line = OV13858_PPL_540MHZ,
0968         .reg_list = {
0969             .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
0970             .regs = mipi_data_rate_1080mbps,
0971         }
0972     },
0973     {
0974         .pixels_per_line = OV13858_PPL_270MHZ,
0975         .reg_list = {
0976             .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
0977             .regs = mipi_data_rate_540mbps,
0978         }
0979     }
0980 };
0981 
0982 /* Mode configs */
0983 static const struct ov13858_mode supported_modes[] = {
0984     {
0985         .width = 4224,
0986         .height = 3136,
0987         .vts_def = OV13858_VTS_30FPS,
0988         .vts_min = OV13858_VTS_30FPS,
0989         .reg_list = {
0990             .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
0991             .regs = mode_4224x3136_regs,
0992         },
0993         .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
0994     },
0995     {
0996         .width = 2112,
0997         .height = 1568,
0998         .vts_def = OV13858_VTS_30FPS,
0999         .vts_min = 1608,
1000         .reg_list = {
1001             .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1002             .regs = mode_2112x1568_regs,
1003         },
1004         .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1005     },
1006     {
1007         .width = 2112,
1008         .height = 1188,
1009         .vts_def = OV13858_VTS_30FPS,
1010         .vts_min = 1608,
1011         .reg_list = {
1012             .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1013             .regs = mode_2112x1188_regs,
1014         },
1015         .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1016     },
1017     {
1018         .width = 1056,
1019         .height = 784,
1020         .vts_def = OV13858_VTS_30FPS,
1021         .vts_min = 804,
1022         .reg_list = {
1023             .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1024             .regs = mode_1056x784_regs,
1025         },
1026         .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1027     }
1028 };
1029 
1030 struct ov13858 {
1031     struct v4l2_subdev sd;
1032     struct media_pad pad;
1033 
1034     struct v4l2_ctrl_handler ctrl_handler;
1035     /* V4L2 Controls */
1036     struct v4l2_ctrl *link_freq;
1037     struct v4l2_ctrl *pixel_rate;
1038     struct v4l2_ctrl *vblank;
1039     struct v4l2_ctrl *hblank;
1040     struct v4l2_ctrl *exposure;
1041 
1042     /* Current mode */
1043     const struct ov13858_mode *cur_mode;
1044 
1045     /* Mutex for serialized access */
1046     struct mutex mutex;
1047 
1048     /* Streaming on/off */
1049     bool streaming;
1050 };
1051 
1052 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1053 
1054 /* Read registers up to 4 at a time */
1055 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1056                 u32 *val)
1057 {
1058     struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1059     struct i2c_msg msgs[2];
1060     u8 *data_be_p;
1061     int ret;
1062     __be32 data_be = 0;
1063     __be16 reg_addr_be = cpu_to_be16(reg);
1064 
1065     if (len > 4)
1066         return -EINVAL;
1067 
1068     data_be_p = (u8 *)&data_be;
1069     /* Write register address */
1070     msgs[0].addr = client->addr;
1071     msgs[0].flags = 0;
1072     msgs[0].len = 2;
1073     msgs[0].buf = (u8 *)&reg_addr_be;
1074 
1075     /* Read data from register */
1076     msgs[1].addr = client->addr;
1077     msgs[1].flags = I2C_M_RD;
1078     msgs[1].len = len;
1079     msgs[1].buf = &data_be_p[4 - len];
1080 
1081     ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1082     if (ret != ARRAY_SIZE(msgs))
1083         return -EIO;
1084 
1085     *val = be32_to_cpu(data_be);
1086 
1087     return 0;
1088 }
1089 
1090 /* Write registers up to 4 at a time */
1091 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1092                  u32 __val)
1093 {
1094     struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1095     int buf_i, val_i;
1096     u8 buf[6], *val_p;
1097     __be32 val;
1098 
1099     if (len > 4)
1100         return -EINVAL;
1101 
1102     buf[0] = reg >> 8;
1103     buf[1] = reg & 0xff;
1104 
1105     val = cpu_to_be32(__val);
1106     val_p = (u8 *)&val;
1107     buf_i = 2;
1108     val_i = 4 - len;
1109 
1110     while (val_i < 4)
1111         buf[buf_i++] = val_p[val_i++];
1112 
1113     if (i2c_master_send(client, buf, len + 2) != len + 2)
1114         return -EIO;
1115 
1116     return 0;
1117 }
1118 
1119 /* Write a list of registers */
1120 static int ov13858_write_regs(struct ov13858 *ov13858,
1121                   const struct ov13858_reg *regs, u32 len)
1122 {
1123     struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1124     int ret;
1125     u32 i;
1126 
1127     for (i = 0; i < len; i++) {
1128         ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1129                     regs[i].val);
1130         if (ret) {
1131             dev_err_ratelimited(
1132                 &client->dev,
1133                 "Failed to write reg 0x%4.4x. error = %d\n",
1134                 regs[i].address, ret);
1135 
1136             return ret;
1137         }
1138     }
1139 
1140     return 0;
1141 }
1142 
1143 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1144                   const struct ov13858_reg_list *r_list)
1145 {
1146     return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1147 }
1148 
1149 /* Open sub-device */
1150 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1151 {
1152     struct ov13858 *ov13858 = to_ov13858(sd);
1153     struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1154                                     fh->state,
1155                                     0);
1156 
1157     mutex_lock(&ov13858->mutex);
1158 
1159     /* Initialize try_fmt */
1160     try_fmt->width = ov13858->cur_mode->width;
1161     try_fmt->height = ov13858->cur_mode->height;
1162     try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1163     try_fmt->field = V4L2_FIELD_NONE;
1164 
1165     /* No crop or compose */
1166     mutex_unlock(&ov13858->mutex);
1167 
1168     return 0;
1169 }
1170 
1171 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1172 {
1173     int ret;
1174 
1175     ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1176                 OV13858_REG_VALUE_16BIT, d_gain);
1177     if (ret)
1178         return ret;
1179 
1180     ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1181                 OV13858_REG_VALUE_16BIT, d_gain);
1182     if (ret)
1183         return ret;
1184 
1185     ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1186                 OV13858_REG_VALUE_16BIT, d_gain);
1187 
1188     return ret;
1189 }
1190 
1191 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1192 {
1193     int ret;
1194     u32 val;
1195 
1196     ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1197                    OV13858_REG_VALUE_08BIT, &val);
1198     if (ret)
1199         return ret;
1200 
1201     if (pattern) {
1202         val &= OV13858_TEST_PATTERN_MASK;
1203         val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1204     } else {
1205         val &= ~OV13858_TEST_PATTERN_ENABLE;
1206     }
1207 
1208     return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1209                  OV13858_REG_VALUE_08BIT, val);
1210 }
1211 
1212 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1213 {
1214     struct ov13858 *ov13858 = container_of(ctrl->handler,
1215                            struct ov13858, ctrl_handler);
1216     struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1217     s64 max;
1218     int ret;
1219 
1220     /* Propagate change of current control to all related controls */
1221     switch (ctrl->id) {
1222     case V4L2_CID_VBLANK:
1223         /* Update max exposure while meeting expected vblanking */
1224         max = ov13858->cur_mode->height + ctrl->val - 8;
1225         __v4l2_ctrl_modify_range(ov13858->exposure,
1226                      ov13858->exposure->minimum,
1227                      max, ov13858->exposure->step, max);
1228         break;
1229     }
1230 
1231     /*
1232      * Applying V4L2 control value only happens
1233      * when power is up for streaming
1234      */
1235     if (!pm_runtime_get_if_in_use(&client->dev))
1236         return 0;
1237 
1238     ret = 0;
1239     switch (ctrl->id) {
1240     case V4L2_CID_ANALOGUE_GAIN:
1241         ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1242                     OV13858_REG_VALUE_16BIT, ctrl->val);
1243         break;
1244     case V4L2_CID_DIGITAL_GAIN:
1245         ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1246         break;
1247     case V4L2_CID_EXPOSURE:
1248         ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1249                     OV13858_REG_VALUE_24BIT,
1250                     ctrl->val << 4);
1251         break;
1252     case V4L2_CID_VBLANK:
1253         /* Update VTS that meets expected vertical blanking */
1254         ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1255                     OV13858_REG_VALUE_16BIT,
1256                     ov13858->cur_mode->height
1257                       + ctrl->val);
1258         break;
1259     case V4L2_CID_TEST_PATTERN:
1260         ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1261         break;
1262     default:
1263         dev_info(&client->dev,
1264              "ctrl(id:0x%x,val:0x%x) is not handled\n",
1265              ctrl->id, ctrl->val);
1266         break;
1267     }
1268 
1269     pm_runtime_put(&client->dev);
1270 
1271     return ret;
1272 }
1273 
1274 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1275     .s_ctrl = ov13858_set_ctrl,
1276 };
1277 
1278 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1279                   struct v4l2_subdev_state *sd_state,
1280                   struct v4l2_subdev_mbus_code_enum *code)
1281 {
1282     /* Only one bayer order(GRBG) is supported */
1283     if (code->index > 0)
1284         return -EINVAL;
1285 
1286     code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1287 
1288     return 0;
1289 }
1290 
1291 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1292                    struct v4l2_subdev_state *sd_state,
1293                    struct v4l2_subdev_frame_size_enum *fse)
1294 {
1295     if (fse->index >= ARRAY_SIZE(supported_modes))
1296         return -EINVAL;
1297 
1298     if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1299         return -EINVAL;
1300 
1301     fse->min_width = supported_modes[fse->index].width;
1302     fse->max_width = fse->min_width;
1303     fse->min_height = supported_modes[fse->index].height;
1304     fse->max_height = fse->min_height;
1305 
1306     return 0;
1307 }
1308 
1309 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1310                       struct v4l2_subdev_format *fmt)
1311 {
1312     fmt->format.width = mode->width;
1313     fmt->format.height = mode->height;
1314     fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1315     fmt->format.field = V4L2_FIELD_NONE;
1316 }
1317 
1318 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1319                      struct v4l2_subdev_state *sd_state,
1320                      struct v4l2_subdev_format *fmt)
1321 {
1322     struct v4l2_mbus_framefmt *framefmt;
1323     struct v4l2_subdev *sd = &ov13858->sd;
1324 
1325     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1326         framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1327         fmt->format = *framefmt;
1328     } else {
1329         ov13858_update_pad_format(ov13858->cur_mode, fmt);
1330     }
1331 
1332     return 0;
1333 }
1334 
1335 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1336                   struct v4l2_subdev_state *sd_state,
1337                   struct v4l2_subdev_format *fmt)
1338 {
1339     struct ov13858 *ov13858 = to_ov13858(sd);
1340     int ret;
1341 
1342     mutex_lock(&ov13858->mutex);
1343     ret = ov13858_do_get_pad_format(ov13858, sd_state, fmt);
1344     mutex_unlock(&ov13858->mutex);
1345 
1346     return ret;
1347 }
1348 
1349 static int
1350 ov13858_set_pad_format(struct v4l2_subdev *sd,
1351                struct v4l2_subdev_state *sd_state,
1352                struct v4l2_subdev_format *fmt)
1353 {
1354     struct ov13858 *ov13858 = to_ov13858(sd);
1355     const struct ov13858_mode *mode;
1356     struct v4l2_mbus_framefmt *framefmt;
1357     s32 vblank_def;
1358     s32 vblank_min;
1359     s64 h_blank;
1360     s64 pixel_rate;
1361     s64 link_freq;
1362 
1363     mutex_lock(&ov13858->mutex);
1364 
1365     /* Only one raw bayer(GRBG) order is supported */
1366     if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1367         fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1368 
1369     mode = v4l2_find_nearest_size(supported_modes,
1370                       ARRAY_SIZE(supported_modes),
1371                       width, height,
1372                       fmt->format.width, fmt->format.height);
1373     ov13858_update_pad_format(mode, fmt);
1374     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1375         framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1376         *framefmt = fmt->format;
1377     } else {
1378         ov13858->cur_mode = mode;
1379         __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1380         link_freq = link_freq_menu_items[mode->link_freq_index];
1381         pixel_rate = link_freq_to_pixel_rate(link_freq);
1382         __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
1383 
1384         /* Update limits and set FPS to default */
1385         vblank_def = ov13858->cur_mode->vts_def -
1386                  ov13858->cur_mode->height;
1387         vblank_min = ov13858->cur_mode->vts_min -
1388                  ov13858->cur_mode->height;
1389         __v4l2_ctrl_modify_range(
1390             ov13858->vblank, vblank_min,
1391             OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1392             vblank_def);
1393         __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1394         h_blank =
1395             link_freq_configs[mode->link_freq_index].pixels_per_line
1396              - ov13858->cur_mode->width;
1397         __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1398                      h_blank, 1, h_blank);
1399     }
1400 
1401     mutex_unlock(&ov13858->mutex);
1402 
1403     return 0;
1404 }
1405 
1406 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1407 {
1408     *frames = OV13858_NUM_OF_SKIP_FRAMES;
1409 
1410     return 0;
1411 }
1412 
1413 /* Start streaming */
1414 static int ov13858_start_streaming(struct ov13858 *ov13858)
1415 {
1416     struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1417     const struct ov13858_reg_list *reg_list;
1418     int ret, link_freq_index;
1419 
1420     /* Get out of from software reset */
1421     ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1422                 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1423     if (ret) {
1424         dev_err(&client->dev, "%s failed to set powerup registers\n",
1425             __func__);
1426         return ret;
1427     }
1428 
1429     /* Setup PLL */
1430     link_freq_index = ov13858->cur_mode->link_freq_index;
1431     reg_list = &link_freq_configs[link_freq_index].reg_list;
1432     ret = ov13858_write_reg_list(ov13858, reg_list);
1433     if (ret) {
1434         dev_err(&client->dev, "%s failed to set plls\n", __func__);
1435         return ret;
1436     }
1437 
1438     /* Apply default values of current mode */
1439     reg_list = &ov13858->cur_mode->reg_list;
1440     ret = ov13858_write_reg_list(ov13858, reg_list);
1441     if (ret) {
1442         dev_err(&client->dev, "%s failed to set mode\n", __func__);
1443         return ret;
1444     }
1445 
1446     /* Apply customized values from user */
1447     ret =  __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1448     if (ret)
1449         return ret;
1450 
1451     return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1452                  OV13858_REG_VALUE_08BIT,
1453                  OV13858_MODE_STREAMING);
1454 }
1455 
1456 /* Stop streaming */
1457 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1458 {
1459     return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1460                  OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1461 }
1462 
1463 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1464 {
1465     struct ov13858 *ov13858 = to_ov13858(sd);
1466     struct i2c_client *client = v4l2_get_subdevdata(sd);
1467     int ret = 0;
1468 
1469     mutex_lock(&ov13858->mutex);
1470     if (ov13858->streaming == enable) {
1471         mutex_unlock(&ov13858->mutex);
1472         return 0;
1473     }
1474 
1475     if (enable) {
1476         ret = pm_runtime_resume_and_get(&client->dev);
1477         if (ret < 0)
1478             goto err_unlock;
1479 
1480         /*
1481          * Apply default & customized values
1482          * and then start streaming.
1483          */
1484         ret = ov13858_start_streaming(ov13858);
1485         if (ret)
1486             goto err_rpm_put;
1487     } else {
1488         ov13858_stop_streaming(ov13858);
1489         pm_runtime_put(&client->dev);
1490     }
1491 
1492     ov13858->streaming = enable;
1493     mutex_unlock(&ov13858->mutex);
1494 
1495     return ret;
1496 
1497 err_rpm_put:
1498     pm_runtime_put(&client->dev);
1499 err_unlock:
1500     mutex_unlock(&ov13858->mutex);
1501 
1502     return ret;
1503 }
1504 
1505 static int __maybe_unused ov13858_suspend(struct device *dev)
1506 {
1507     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1508     struct ov13858 *ov13858 = to_ov13858(sd);
1509 
1510     if (ov13858->streaming)
1511         ov13858_stop_streaming(ov13858);
1512 
1513     return 0;
1514 }
1515 
1516 static int __maybe_unused ov13858_resume(struct device *dev)
1517 {
1518     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1519     struct ov13858 *ov13858 = to_ov13858(sd);
1520     int ret;
1521 
1522     if (ov13858->streaming) {
1523         ret = ov13858_start_streaming(ov13858);
1524         if (ret)
1525             goto error;
1526     }
1527 
1528     return 0;
1529 
1530 error:
1531     ov13858_stop_streaming(ov13858);
1532     ov13858->streaming = false;
1533     return ret;
1534 }
1535 
1536 /* Verify chip ID */
1537 static int ov13858_identify_module(struct ov13858 *ov13858)
1538 {
1539     struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1540     int ret;
1541     u32 val;
1542 
1543     ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1544                    OV13858_REG_VALUE_24BIT, &val);
1545     if (ret)
1546         return ret;
1547 
1548     if (val != OV13858_CHIP_ID) {
1549         dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1550             OV13858_CHIP_ID, val);
1551         return -EIO;
1552     }
1553 
1554     return 0;
1555 }
1556 
1557 static const struct v4l2_subdev_core_ops ov13858_core_ops = {
1558     .log_status = v4l2_ctrl_subdev_log_status,
1559     .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1560     .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1561 };
1562 
1563 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1564     .s_stream = ov13858_set_stream,
1565 };
1566 
1567 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1568     .enum_mbus_code = ov13858_enum_mbus_code,
1569     .get_fmt = ov13858_get_pad_format,
1570     .set_fmt = ov13858_set_pad_format,
1571     .enum_frame_size = ov13858_enum_frame_size,
1572 };
1573 
1574 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1575     .g_skip_frames = ov13858_get_skip_frames,
1576 };
1577 
1578 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1579     .core = &ov13858_core_ops,
1580     .video = &ov13858_video_ops,
1581     .pad = &ov13858_pad_ops,
1582     .sensor = &ov13858_sensor_ops,
1583 };
1584 
1585 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1586     .link_validate = v4l2_subdev_link_validate,
1587 };
1588 
1589 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1590     .open = ov13858_open,
1591 };
1592 
1593 /* Initialize control handlers */
1594 static int ov13858_init_controls(struct ov13858 *ov13858)
1595 {
1596     struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1597     struct v4l2_fwnode_device_properties props;
1598     struct v4l2_ctrl_handler *ctrl_hdlr;
1599     s64 exposure_max;
1600     s64 vblank_def;
1601     s64 vblank_min;
1602     s64 hblank;
1603     s64 pixel_rate_min;
1604     s64 pixel_rate_max;
1605     const struct ov13858_mode *mode;
1606     int ret;
1607 
1608     ctrl_hdlr = &ov13858->ctrl_handler;
1609     ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1610     if (ret)
1611         return ret;
1612 
1613     mutex_init(&ov13858->mutex);
1614     ctrl_hdlr->lock = &ov13858->mutex;
1615     ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1616                 &ov13858_ctrl_ops,
1617                 V4L2_CID_LINK_FREQ,
1618                 OV13858_NUM_OF_LINK_FREQS - 1,
1619                 0,
1620                 link_freq_menu_items);
1621     if (ov13858->link_freq)
1622         ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1623 
1624     pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1625     pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1626     /* By default, PIXEL_RATE is read only */
1627     ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1628                         V4L2_CID_PIXEL_RATE,
1629                         pixel_rate_min, pixel_rate_max,
1630                         1, pixel_rate_max);
1631 
1632     mode = ov13858->cur_mode;
1633     vblank_def = mode->vts_def - mode->height;
1634     vblank_min = mode->vts_min - mode->height;
1635     ov13858->vblank = v4l2_ctrl_new_std(
1636                 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1637                 vblank_min, OV13858_VTS_MAX - mode->height, 1,
1638                 vblank_def);
1639 
1640     hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1641          mode->width;
1642     ov13858->hblank = v4l2_ctrl_new_std(
1643                 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1644                 hblank, hblank, 1, hblank);
1645     if (ov13858->hblank)
1646         ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1647 
1648     exposure_max = mode->vts_def - 8;
1649     ov13858->exposure = v4l2_ctrl_new_std(
1650                 ctrl_hdlr, &ov13858_ctrl_ops,
1651                 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1652                 exposure_max, OV13858_EXPOSURE_STEP,
1653                 OV13858_EXPOSURE_DEFAULT);
1654 
1655     v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1656               OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1657               OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1658 
1659     /* Digital gain */
1660     v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1661               OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1662               OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1663 
1664     v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1665                      V4L2_CID_TEST_PATTERN,
1666                      ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1667                      0, 0, ov13858_test_pattern_menu);
1668     if (ctrl_hdlr->error) {
1669         ret = ctrl_hdlr->error;
1670         dev_err(&client->dev, "%s control init failed (%d)\n",
1671             __func__, ret);
1672         goto error;
1673     }
1674 
1675     ret = v4l2_fwnode_device_parse(&client->dev, &props);
1676     if (ret)
1677         goto error;
1678 
1679     ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13858_ctrl_ops,
1680                           &props);
1681     if (ret)
1682         goto error;
1683 
1684     ov13858->sd.ctrl_handler = ctrl_hdlr;
1685 
1686     return 0;
1687 
1688 error:
1689     v4l2_ctrl_handler_free(ctrl_hdlr);
1690     mutex_destroy(&ov13858->mutex);
1691 
1692     return ret;
1693 }
1694 
1695 static void ov13858_free_controls(struct ov13858 *ov13858)
1696 {
1697     v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1698     mutex_destroy(&ov13858->mutex);
1699 }
1700 
1701 static int ov13858_probe(struct i2c_client *client,
1702              const struct i2c_device_id *devid)
1703 {
1704     struct ov13858 *ov13858;
1705     int ret;
1706     u32 val = 0;
1707 
1708     device_property_read_u32(&client->dev, "clock-frequency", &val);
1709     if (val != 19200000)
1710         return -EINVAL;
1711 
1712     ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1713     if (!ov13858)
1714         return -ENOMEM;
1715 
1716     /* Initialize subdev */
1717     v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1718 
1719     /* Check module identity */
1720     ret = ov13858_identify_module(ov13858);
1721     if (ret) {
1722         dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1723         return ret;
1724     }
1725 
1726     /* Set default mode to max resolution */
1727     ov13858->cur_mode = &supported_modes[0];
1728 
1729     ret = ov13858_init_controls(ov13858);
1730     if (ret)
1731         return ret;
1732 
1733     /* Initialize subdev */
1734     ov13858->sd.internal_ops = &ov13858_internal_ops;
1735     ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1736                  V4L2_SUBDEV_FL_HAS_EVENTS;
1737     ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1738     ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1739 
1740     /* Initialize source pad */
1741     ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1742     ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1743     if (ret) {
1744         dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1745         goto error_handler_free;
1746     }
1747 
1748     ret = v4l2_async_register_subdev_sensor(&ov13858->sd);
1749     if (ret < 0)
1750         goto error_media_entity;
1751 
1752     /*
1753      * Device is already turned on by i2c-core with ACPI domain PM.
1754      * Enable runtime PM and turn off the device.
1755      */
1756     pm_runtime_set_active(&client->dev);
1757     pm_runtime_enable(&client->dev);
1758     pm_runtime_idle(&client->dev);
1759 
1760     return 0;
1761 
1762 error_media_entity:
1763     media_entity_cleanup(&ov13858->sd.entity);
1764 
1765 error_handler_free:
1766     ov13858_free_controls(ov13858);
1767     dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1768 
1769     return ret;
1770 }
1771 
1772 static int ov13858_remove(struct i2c_client *client)
1773 {
1774     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1775     struct ov13858 *ov13858 = to_ov13858(sd);
1776 
1777     v4l2_async_unregister_subdev(sd);
1778     media_entity_cleanup(&sd->entity);
1779     ov13858_free_controls(ov13858);
1780 
1781     pm_runtime_disable(&client->dev);
1782 
1783     return 0;
1784 }
1785 
1786 static const struct i2c_device_id ov13858_id_table[] = {
1787     {"ov13858", 0},
1788     {},
1789 };
1790 
1791 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1792 
1793 static const struct dev_pm_ops ov13858_pm_ops = {
1794     SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
1795 };
1796 
1797 #ifdef CONFIG_ACPI
1798 static const struct acpi_device_id ov13858_acpi_ids[] = {
1799     {"OVTID858"},
1800     { /* sentinel */ }
1801 };
1802 
1803 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1804 #endif
1805 
1806 static struct i2c_driver ov13858_i2c_driver = {
1807     .driver = {
1808         .name = "ov13858",
1809         .pm = &ov13858_pm_ops,
1810         .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1811     },
1812     .probe = ov13858_probe,
1813     .remove = ov13858_remove,
1814     .id_table = ov13858_id_table,
1815 };
1816 
1817 module_i2c_driver(ov13858_i2c_driver);
1818 
1819 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1820 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
1821 MODULE_AUTHOR("Yang, Hyungwoo");
1822 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1823 MODULE_LICENSE("GPL v2");
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