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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2020 MediaTek Inc.
0003 
0004 #include <linux/clk.h>
0005 #include <linux/delay.h>
0006 #include <linux/device.h>
0007 #include <linux/gpio/consumer.h>
0008 #include <linux/i2c.h>
0009 #include <linux/module.h>
0010 #include <linux/pm_runtime.h>
0011 #include <linux/regulator/consumer.h>
0012 #include <linux/units.h>
0013 #include <media/media-entity.h>
0014 #include <media/v4l2-async.h>
0015 #include <media/v4l2-ctrls.h>
0016 #include <media/v4l2-fwnode.h>
0017 #include <media/v4l2-subdev.h>
0018 
0019 #define OV02A10_ID                  0x2509
0020 #define OV02A10_ID_MASK                 GENMASK(15, 0)
0021 
0022 #define OV02A10_REG_CHIP_ID             0x02
0023 
0024 /* Bit[1] vertical upside down */
0025 /* Bit[0] horizontal mirror */
0026 #define REG_MIRROR_FLIP_CONTROL             0x3f
0027 
0028 /* Orientation */
0029 #define REG_MIRROR_FLIP_ENABLE              0x03
0030 
0031 /* Bit[2:0] MIPI transmission speed select */
0032 #define TX_SPEED_AREA_SEL               0xa1
0033 #define OV02A10_MIPI_TX_SPEED_DEFAULT           0x04
0034 
0035 #define REG_PAGE_SWITCH                 0xfd
0036 #define REG_GLOBAL_EFFECTIVE                0x01
0037 #define REG_ENABLE                  BIT(0)
0038 
0039 #define REG_SC_CTRL_MODE                0xac
0040 #define SC_CTRL_MODE_STANDBY                0x00
0041 #define SC_CTRL_MODE_STREAMING              0x01
0042 
0043 /* Exposure control */
0044 #define OV02A10_EXP_SHIFT               8
0045 #define OV02A10_REG_EXPOSURE_H              0x03
0046 #define OV02A10_REG_EXPOSURE_L              0x04
0047 #define OV02A10_EXPOSURE_MIN                4
0048 #define OV02A10_EXPOSURE_MAX_MARGIN         4
0049 #define OV02A10_EXPOSURE_STEP               1
0050 
0051 /* Vblanking control */
0052 #define OV02A10_VTS_SHIFT               8
0053 #define OV02A10_REG_VTS_H               0x05
0054 #define OV02A10_REG_VTS_L               0x06
0055 #define OV02A10_VTS_MAX                 0x209f
0056 #define OV02A10_BASE_LINES              1224
0057 
0058 /* Analog gain control */
0059 #define OV02A10_REG_GAIN                0x24
0060 #define OV02A10_GAIN_MIN                0x10
0061 #define OV02A10_GAIN_MAX                0xf8
0062 #define OV02A10_GAIN_STEP               0x01
0063 #define OV02A10_GAIN_DEFAULT                0x40
0064 
0065 /* Test pattern control */
0066 #define OV02A10_REG_TEST_PATTERN            0xb6
0067 
0068 #define OV02A10_LINK_FREQ_390MHZ            (390 * HZ_PER_MHZ)
0069 #define OV02A10_ECLK_FREQ               (24 * HZ_PER_MHZ)
0070 
0071 /* Number of lanes supported by this driver */
0072 #define OV02A10_DATA_LANES              1
0073 
0074 /* Bits per sample of sensor output */
0075 #define OV02A10_BITS_PER_SAMPLE             10
0076 
0077 static const char * const ov02a10_supply_names[] = {
0078     "dovdd",    /* Digital I/O power */
0079     "avdd",     /* Analog power */
0080     "dvdd",     /* Digital core power */
0081 };
0082 
0083 struct ov02a10_reg {
0084     u8 addr;
0085     u8 val;
0086 };
0087 
0088 struct ov02a10_reg_list {
0089     u32 num_of_regs;
0090     const struct ov02a10_reg *regs;
0091 };
0092 
0093 struct ov02a10_mode {
0094     u32 width;
0095     u32 height;
0096     u32 exp_def;
0097     u32 hts_def;
0098     u32 vts_def;
0099     const struct ov02a10_reg_list reg_list;
0100 };
0101 
0102 struct ov02a10 {
0103     u32 eclk_freq;
0104     /* Indication of MIPI transmission speed select */
0105     u32 mipi_clock_voltage;
0106 
0107     struct clk *eclk;
0108     struct gpio_desc *pd_gpio;
0109     struct gpio_desc *rst_gpio;
0110     struct regulator_bulk_data supplies[ARRAY_SIZE(ov02a10_supply_names)];
0111 
0112     bool streaming;
0113     bool upside_down;
0114 
0115     /*
0116      * Serialize control access, get/set format, get selection
0117      * and start streaming.
0118      */
0119     struct mutex mutex;
0120     struct v4l2_subdev subdev;
0121     struct media_pad pad;
0122     struct v4l2_mbus_framefmt fmt;
0123     struct v4l2_ctrl_handler ctrl_handler;
0124     struct v4l2_ctrl *exposure;
0125 
0126     const struct ov02a10_mode *cur_mode;
0127 };
0128 
0129 static inline struct ov02a10 *to_ov02a10(struct v4l2_subdev *sd)
0130 {
0131     return container_of(sd, struct ov02a10, subdev);
0132 }
0133 
0134 /*
0135  * eclk 24Mhz
0136  * pclk 39Mhz
0137  * linelength 934(0x3a6)
0138  * framelength 1390(0x56E)
0139  * grabwindow_width 1600
0140  * grabwindow_height 1200
0141  * max_framerate 30fps
0142  * mipi_datarate per lane 780Mbps
0143  */
0144 static const struct ov02a10_reg ov02a10_1600x1200_regs[] = {
0145     {0xfd, 0x01},
0146     {0xac, 0x00},
0147     {0xfd, 0x00},
0148     {0x2f, 0x29},
0149     {0x34, 0x00},
0150     {0x35, 0x21},
0151     {0x30, 0x15},
0152     {0x33, 0x01},
0153     {0xfd, 0x01},
0154     {0x44, 0x00},
0155     {0x2a, 0x4c},
0156     {0x2b, 0x1e},
0157     {0x2c, 0x60},
0158     {0x25, 0x11},
0159     {0x03, 0x01},
0160     {0x04, 0xae},
0161     {0x09, 0x00},
0162     {0x0a, 0x02},
0163     {0x06, 0xa6},
0164     {0x31, 0x00},
0165     {0x24, 0x40},
0166     {0x01, 0x01},
0167     {0xfb, 0x73},
0168     {0xfd, 0x01},
0169     {0x16, 0x04},
0170     {0x1c, 0x09},
0171     {0x21, 0x42},
0172     {0x12, 0x04},
0173     {0x13, 0x10},
0174     {0x11, 0x40},
0175     {0x33, 0x81},
0176     {0xd0, 0x00},
0177     {0xd1, 0x01},
0178     {0xd2, 0x00},
0179     {0x50, 0x10},
0180     {0x51, 0x23},
0181     {0x52, 0x20},
0182     {0x53, 0x10},
0183     {0x54, 0x02},
0184     {0x55, 0x20},
0185     {0x56, 0x02},
0186     {0x58, 0x48},
0187     {0x5d, 0x15},
0188     {0x5e, 0x05},
0189     {0x66, 0x66},
0190     {0x68, 0x68},
0191     {0x6b, 0x00},
0192     {0x6c, 0x00},
0193     {0x6f, 0x40},
0194     {0x70, 0x40},
0195     {0x71, 0x0a},
0196     {0x72, 0xf0},
0197     {0x73, 0x10},
0198     {0x75, 0x80},
0199     {0x76, 0x10},
0200     {0x84, 0x00},
0201     {0x85, 0x10},
0202     {0x86, 0x10},
0203     {0x87, 0x00},
0204     {0x8a, 0x22},
0205     {0x8b, 0x22},
0206     {0x19, 0xf1},
0207     {0x29, 0x01},
0208     {0xfd, 0x01},
0209     {0x9d, 0x16},
0210     {0xa0, 0x29},
0211     {0xa1, 0x04},
0212     {0xad, 0x62},
0213     {0xae, 0x00},
0214     {0xaf, 0x85},
0215     {0xb1, 0x01},
0216     {0x8e, 0x06},
0217     {0x8f, 0x40},
0218     {0x90, 0x04},
0219     {0x91, 0xb0},
0220     {0x45, 0x01},
0221     {0x46, 0x00},
0222     {0x47, 0x6c},
0223     {0x48, 0x03},
0224     {0x49, 0x8b},
0225     {0x4a, 0x00},
0226     {0x4b, 0x07},
0227     {0x4c, 0x04},
0228     {0x4d, 0xb7},
0229     {0xf0, 0x40},
0230     {0xf1, 0x40},
0231     {0xf2, 0x40},
0232     {0xf3, 0x40},
0233     {0x3f, 0x00},
0234     {0xfd, 0x01},
0235     {0x05, 0x00},
0236     {0x06, 0xa6},
0237     {0xfd, 0x01},
0238 };
0239 
0240 static const char * const ov02a10_test_pattern_menu[] = {
0241     "Disabled",
0242     "Eight Vertical Colour Bars",
0243 };
0244 
0245 static const s64 link_freq_menu_items[] = {
0246     OV02A10_LINK_FREQ_390MHZ,
0247 };
0248 
0249 static u64 to_pixel_rate(u32 f_index)
0250 {
0251     u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02A10_DATA_LANES;
0252 
0253     do_div(pixel_rate, OV02A10_BITS_PER_SAMPLE);
0254 
0255     return pixel_rate;
0256 }
0257 
0258 static const struct ov02a10_mode supported_modes[] = {
0259     {
0260         .width = 1600,
0261         .height = 1200,
0262         .exp_def = 0x01ae,
0263         .hts_def = 0x03a6,
0264         .vts_def = 0x056e,
0265         .reg_list = {
0266             .num_of_regs = ARRAY_SIZE(ov02a10_1600x1200_regs),
0267             .regs = ov02a10_1600x1200_regs,
0268         },
0269     },
0270 };
0271 
0272 static int ov02a10_write_array(struct ov02a10 *ov02a10,
0273                    const struct ov02a10_reg_list *r_list)
0274 {
0275     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0276     unsigned int i;
0277     int ret;
0278 
0279     for (i = 0; i < r_list->num_of_regs; i++) {
0280         ret = i2c_smbus_write_byte_data(client, r_list->regs[i].addr,
0281                         r_list->regs[i].val);
0282         if (ret < 0)
0283             return ret;
0284     }
0285 
0286     return 0;
0287 }
0288 
0289 static void ov02a10_fill_fmt(const struct ov02a10_mode *mode,
0290                  struct v4l2_mbus_framefmt *fmt)
0291 {
0292     fmt->width = mode->width;
0293     fmt->height = mode->height;
0294     fmt->field = V4L2_FIELD_NONE;
0295 }
0296 
0297 static int ov02a10_set_fmt(struct v4l2_subdev *sd,
0298                struct v4l2_subdev_state *sd_state,
0299                struct v4l2_subdev_format *fmt)
0300 {
0301     struct ov02a10 *ov02a10 = to_ov02a10(sd);
0302     struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
0303     struct v4l2_mbus_framefmt *frame_fmt;
0304     int ret = 0;
0305 
0306     mutex_lock(&ov02a10->mutex);
0307 
0308     if (ov02a10->streaming && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
0309         ret = -EBUSY;
0310         goto out_unlock;
0311     }
0312 
0313     /* Only one sensor mode supported */
0314     mbus_fmt->code = ov02a10->fmt.code;
0315     ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
0316 
0317     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
0318         frame_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
0319     else
0320         frame_fmt = &ov02a10->fmt;
0321 
0322     *frame_fmt = *mbus_fmt;
0323 
0324 out_unlock:
0325     mutex_unlock(&ov02a10->mutex);
0326     return ret;
0327 }
0328 
0329 static int ov02a10_get_fmt(struct v4l2_subdev *sd,
0330                struct v4l2_subdev_state *sd_state,
0331                struct v4l2_subdev_format *fmt)
0332 {
0333     struct ov02a10 *ov02a10 = to_ov02a10(sd);
0334     struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
0335 
0336     mutex_lock(&ov02a10->mutex);
0337 
0338     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0339         fmt->format = *v4l2_subdev_get_try_format(sd, sd_state,
0340                               fmt->pad);
0341     } else {
0342         fmt->format = ov02a10->fmt;
0343         mbus_fmt->code = ov02a10->fmt.code;
0344         ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
0345     }
0346 
0347     mutex_unlock(&ov02a10->mutex);
0348 
0349     return 0;
0350 }
0351 
0352 static int ov02a10_enum_mbus_code(struct v4l2_subdev *sd,
0353                   struct v4l2_subdev_state *sd_state,
0354                   struct v4l2_subdev_mbus_code_enum *code)
0355 {
0356     struct ov02a10 *ov02a10 = to_ov02a10(sd);
0357 
0358     if (code->index != 0)
0359         return -EINVAL;
0360 
0361     code->code = ov02a10->fmt.code;
0362 
0363     return 0;
0364 }
0365 
0366 static int ov02a10_enum_frame_sizes(struct v4l2_subdev *sd,
0367                     struct v4l2_subdev_state *sd_state,
0368                     struct v4l2_subdev_frame_size_enum *fse)
0369 {
0370     if (fse->index >= ARRAY_SIZE(supported_modes))
0371         return -EINVAL;
0372 
0373     fse->min_width  = supported_modes[fse->index].width;
0374     fse->max_width  = supported_modes[fse->index].width;
0375     fse->max_height = supported_modes[fse->index].height;
0376     fse->min_height = supported_modes[fse->index].height;
0377 
0378     return 0;
0379 }
0380 
0381 static int ov02a10_check_sensor_id(struct ov02a10 *ov02a10)
0382 {
0383     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0384     u16 chip_id;
0385     int ret;
0386 
0387     /* Validate the chip ID */
0388     ret = i2c_smbus_read_word_swapped(client, OV02A10_REG_CHIP_ID);
0389     if (ret < 0)
0390         return ret;
0391 
0392     chip_id = le16_to_cpu((__force __le16)ret);
0393 
0394     if ((chip_id & OV02A10_ID_MASK) != OV02A10_ID) {
0395         dev_err(&client->dev, "unexpected sensor id(0x%04x)\n", chip_id);
0396         return -EINVAL;
0397     }
0398 
0399     return 0;
0400 }
0401 
0402 static int ov02a10_power_on(struct device *dev)
0403 {
0404     struct i2c_client *client = to_i2c_client(dev);
0405     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0406     struct ov02a10 *ov02a10 = to_ov02a10(sd);
0407     int ret;
0408 
0409     gpiod_set_value_cansleep(ov02a10->rst_gpio, 1);
0410     gpiod_set_value_cansleep(ov02a10->pd_gpio, 1);
0411 
0412     ret = clk_prepare_enable(ov02a10->eclk);
0413     if (ret < 0) {
0414         dev_err(dev, "failed to enable eclk\n");
0415         return ret;
0416     }
0417 
0418     ret = regulator_bulk_enable(ARRAY_SIZE(ov02a10_supply_names),
0419                     ov02a10->supplies);
0420     if (ret < 0) {
0421         dev_err(dev, "failed to enable regulators\n");
0422         goto disable_clk;
0423     }
0424     usleep_range(5000, 6000);
0425 
0426     gpiod_set_value_cansleep(ov02a10->pd_gpio, 0);
0427     usleep_range(5000, 6000);
0428 
0429     gpiod_set_value_cansleep(ov02a10->rst_gpio, 0);
0430     usleep_range(5000, 6000);
0431 
0432     ret = ov02a10_check_sensor_id(ov02a10);
0433     if (ret)
0434         goto disable_regulator;
0435 
0436     return 0;
0437 
0438 disable_regulator:
0439     regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names),
0440                    ov02a10->supplies);
0441 disable_clk:
0442     clk_disable_unprepare(ov02a10->eclk);
0443 
0444     return ret;
0445 }
0446 
0447 static int ov02a10_power_off(struct device *dev)
0448 {
0449     struct i2c_client *client = to_i2c_client(dev);
0450     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0451     struct ov02a10 *ov02a10 = to_ov02a10(sd);
0452 
0453     gpiod_set_value_cansleep(ov02a10->rst_gpio, 1);
0454     clk_disable_unprepare(ov02a10->eclk);
0455     gpiod_set_value_cansleep(ov02a10->pd_gpio, 1);
0456     regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names),
0457                    ov02a10->supplies);
0458 
0459     return 0;
0460 }
0461 
0462 static int __ov02a10_start_stream(struct ov02a10 *ov02a10)
0463 {
0464     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0465     const struct ov02a10_reg_list *reg_list;
0466     int ret;
0467 
0468     /* Apply default values of current mode */
0469     reg_list = &ov02a10->cur_mode->reg_list;
0470     ret = ov02a10_write_array(ov02a10, reg_list);
0471     if (ret)
0472         return ret;
0473 
0474     /* Apply customized values from user */
0475     ret = __v4l2_ctrl_handler_setup(ov02a10->subdev.ctrl_handler);
0476     if (ret)
0477         return ret;
0478 
0479     /* Set orientation to 180 degree */
0480     if (ov02a10->upside_down) {
0481         ret = i2c_smbus_write_byte_data(client, REG_MIRROR_FLIP_CONTROL,
0482                         REG_MIRROR_FLIP_ENABLE);
0483         if (ret < 0) {
0484             dev_err(&client->dev, "failed to set orientation\n");
0485             return ret;
0486         }
0487         ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
0488                         REG_ENABLE);
0489         if (ret < 0)
0490             return ret;
0491     }
0492 
0493     /* Set MIPI TX speed according to DT property */
0494     if (ov02a10->mipi_clock_voltage != OV02A10_MIPI_TX_SPEED_DEFAULT) {
0495         ret = i2c_smbus_write_byte_data(client, TX_SPEED_AREA_SEL,
0496                         ov02a10->mipi_clock_voltage);
0497         if (ret < 0)
0498             return ret;
0499     }
0500 
0501     /* Set stream on register */
0502     return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
0503                      SC_CTRL_MODE_STREAMING);
0504 }
0505 
0506 static int __ov02a10_stop_stream(struct ov02a10 *ov02a10)
0507 {
0508     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0509 
0510     return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
0511                      SC_CTRL_MODE_STANDBY);
0512 }
0513 
0514 static int ov02a10_entity_init_cfg(struct v4l2_subdev *sd,
0515                    struct v4l2_subdev_state *sd_state)
0516 {
0517     struct v4l2_subdev_format fmt = {
0518         .which = V4L2_SUBDEV_FORMAT_TRY,
0519         .format = {
0520             .width = 1600,
0521             .height = 1200,
0522         }
0523     };
0524 
0525     ov02a10_set_fmt(sd, sd_state, &fmt);
0526 
0527     return 0;
0528 }
0529 
0530 static int ov02a10_s_stream(struct v4l2_subdev *sd, int on)
0531 {
0532     struct ov02a10 *ov02a10 = to_ov02a10(sd);
0533     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0534     int ret;
0535 
0536     mutex_lock(&ov02a10->mutex);
0537 
0538     if (ov02a10->streaming == on) {
0539         ret = 0;
0540         goto unlock_and_return;
0541     }
0542 
0543     if (on) {
0544         ret = pm_runtime_resume_and_get(&client->dev);
0545         if (ret < 0)
0546             goto unlock_and_return;
0547 
0548         ret = __ov02a10_start_stream(ov02a10);
0549         if (ret) {
0550             __ov02a10_stop_stream(ov02a10);
0551             ov02a10->streaming = !on;
0552             goto err_rpm_put;
0553         }
0554     } else {
0555         __ov02a10_stop_stream(ov02a10);
0556         pm_runtime_put(&client->dev);
0557     }
0558 
0559     ov02a10->streaming = on;
0560     mutex_unlock(&ov02a10->mutex);
0561 
0562     return 0;
0563 
0564 err_rpm_put:
0565     pm_runtime_put(&client->dev);
0566 unlock_and_return:
0567     mutex_unlock(&ov02a10->mutex);
0568 
0569     return ret;
0570 }
0571 
0572 static const struct dev_pm_ops ov02a10_pm_ops = {
0573     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0574                 pm_runtime_force_resume)
0575     SET_RUNTIME_PM_OPS(ov02a10_power_off, ov02a10_power_on, NULL)
0576 };
0577 
0578 static int ov02a10_set_exposure(struct ov02a10 *ov02a10, int val)
0579 {
0580     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0581     int ret;
0582 
0583     ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
0584     if (ret < 0)
0585         return ret;
0586 
0587     ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_H,
0588                     val >> OV02A10_EXP_SHIFT);
0589     if (ret < 0)
0590         return ret;
0591 
0592     ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_L, val);
0593     if (ret < 0)
0594         return ret;
0595 
0596     return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
0597                      REG_ENABLE);
0598 }
0599 
0600 static int ov02a10_set_gain(struct ov02a10 *ov02a10, int val)
0601 {
0602     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0603     int ret;
0604 
0605     ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
0606     if (ret < 0)
0607         return ret;
0608 
0609     ret = i2c_smbus_write_byte_data(client, OV02A10_REG_GAIN, val);
0610     if (ret < 0)
0611         return ret;
0612 
0613     return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
0614                      REG_ENABLE);
0615 }
0616 
0617 static int ov02a10_set_vblank(struct ov02a10 *ov02a10, int val)
0618 {
0619     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0620     u32 vts = val + ov02a10->cur_mode->height - OV02A10_BASE_LINES;
0621     int ret;
0622 
0623     ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
0624     if (ret < 0)
0625         return ret;
0626 
0627     ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_H,
0628                     vts >> OV02A10_VTS_SHIFT);
0629     if (ret < 0)
0630         return ret;
0631 
0632     ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_L, vts);
0633     if (ret < 0)
0634         return ret;
0635 
0636     return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
0637                      REG_ENABLE);
0638 }
0639 
0640 static int ov02a10_set_test_pattern(struct ov02a10 *ov02a10, int pattern)
0641 {
0642     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0643     int ret;
0644 
0645     ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
0646     if (ret < 0)
0647         return ret;
0648 
0649     ret = i2c_smbus_write_byte_data(client, OV02A10_REG_TEST_PATTERN,
0650                     pattern);
0651     if (ret < 0)
0652         return ret;
0653 
0654     ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
0655                     REG_ENABLE);
0656     if (ret < 0)
0657         return ret;
0658 
0659     return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
0660                      SC_CTRL_MODE_STREAMING);
0661 }
0662 
0663 static int ov02a10_set_ctrl(struct v4l2_ctrl *ctrl)
0664 {
0665     struct ov02a10 *ov02a10 = container_of(ctrl->handler,
0666                            struct ov02a10, ctrl_handler);
0667     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0668     s64 max_expo;
0669     int ret;
0670 
0671     /* Propagate change of current control to all related controls */
0672     if (ctrl->id == V4L2_CID_VBLANK) {
0673         /* Update max exposure while meeting expected vblanking */
0674         max_expo = ov02a10->cur_mode->height + ctrl->val -
0675                OV02A10_EXPOSURE_MAX_MARGIN;
0676         __v4l2_ctrl_modify_range(ov02a10->exposure,
0677                      ov02a10->exposure->minimum, max_expo,
0678                      ov02a10->exposure->step,
0679                      ov02a10->exposure->default_value);
0680     }
0681 
0682     /* V4L2 controls values will be applied only when power is already up */
0683     if (!pm_runtime_get_if_in_use(&client->dev))
0684         return 0;
0685 
0686     switch (ctrl->id) {
0687     case V4L2_CID_EXPOSURE:
0688         ret = ov02a10_set_exposure(ov02a10, ctrl->val);
0689         break;
0690     case V4L2_CID_ANALOGUE_GAIN:
0691         ret = ov02a10_set_gain(ov02a10, ctrl->val);
0692         break;
0693     case V4L2_CID_VBLANK:
0694         ret = ov02a10_set_vblank(ov02a10, ctrl->val);
0695         break;
0696     case V4L2_CID_TEST_PATTERN:
0697         ret = ov02a10_set_test_pattern(ov02a10, ctrl->val);
0698         break;
0699     default:
0700         ret = -EINVAL;
0701         break;
0702     }
0703 
0704     pm_runtime_put(&client->dev);
0705 
0706     return ret;
0707 }
0708 
0709 static const struct v4l2_subdev_video_ops ov02a10_video_ops = {
0710     .s_stream = ov02a10_s_stream,
0711 };
0712 
0713 static const struct v4l2_subdev_pad_ops ov02a10_pad_ops = {
0714     .init_cfg = ov02a10_entity_init_cfg,
0715     .enum_mbus_code = ov02a10_enum_mbus_code,
0716     .enum_frame_size = ov02a10_enum_frame_sizes,
0717     .get_fmt = ov02a10_get_fmt,
0718     .set_fmt = ov02a10_set_fmt,
0719 };
0720 
0721 static const struct v4l2_subdev_ops ov02a10_subdev_ops = {
0722     .video  = &ov02a10_video_ops,
0723     .pad    = &ov02a10_pad_ops,
0724 };
0725 
0726 static const struct media_entity_operations ov02a10_subdev_entity_ops = {
0727     .link_validate = v4l2_subdev_link_validate,
0728 };
0729 
0730 static const struct v4l2_ctrl_ops ov02a10_ctrl_ops = {
0731     .s_ctrl = ov02a10_set_ctrl,
0732 };
0733 
0734 static int ov02a10_initialize_controls(struct ov02a10 *ov02a10)
0735 {
0736     struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
0737     const struct ov02a10_mode *mode;
0738     struct v4l2_ctrl_handler *handler;
0739     struct v4l2_ctrl *ctrl;
0740     s64 exposure_max;
0741     s64 vblank_def;
0742     s64 pixel_rate;
0743     s64 h_blank;
0744     int ret;
0745 
0746     handler = &ov02a10->ctrl_handler;
0747     mode = ov02a10->cur_mode;
0748     ret = v4l2_ctrl_handler_init(handler, 7);
0749     if (ret)
0750         return ret;
0751 
0752     handler->lock = &ov02a10->mutex;
0753 
0754     ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0,
0755                       link_freq_menu_items);
0756     if (ctrl)
0757         ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0758 
0759     pixel_rate = to_pixel_rate(0);
0760     v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1,
0761               pixel_rate);
0762 
0763     h_blank = mode->hts_def - mode->width;
0764     v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, h_blank, h_blank, 1,
0765               h_blank);
0766 
0767     vblank_def = mode->vts_def - mode->height;
0768     v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, V4L2_CID_VBLANK,
0769               vblank_def, OV02A10_VTS_MAX - mode->height, 1,
0770               vblank_def);
0771 
0772     exposure_max = mode->vts_def - 4;
0773     ov02a10->exposure = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
0774                           V4L2_CID_EXPOSURE,
0775                           OV02A10_EXPOSURE_MIN,
0776                           exposure_max,
0777                           OV02A10_EXPOSURE_STEP,
0778                           mode->exp_def);
0779 
0780     v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
0781               V4L2_CID_ANALOGUE_GAIN, OV02A10_GAIN_MIN,
0782               OV02A10_GAIN_MAX, OV02A10_GAIN_STEP,
0783               OV02A10_GAIN_DEFAULT);
0784 
0785     v4l2_ctrl_new_std_menu_items(handler, &ov02a10_ctrl_ops,
0786                      V4L2_CID_TEST_PATTERN,
0787                      ARRAY_SIZE(ov02a10_test_pattern_menu) - 1,
0788                      0, 0, ov02a10_test_pattern_menu);
0789 
0790     if (handler->error) {
0791         ret = handler->error;
0792         dev_err(&client->dev, "failed to init controls(%d)\n", ret);
0793         goto err_free_handler;
0794     }
0795 
0796     ov02a10->subdev.ctrl_handler = handler;
0797 
0798     return 0;
0799 
0800 err_free_handler:
0801     v4l2_ctrl_handler_free(handler);
0802 
0803     return ret;
0804 }
0805 
0806 static int ov02a10_check_hwcfg(struct device *dev, struct ov02a10 *ov02a10)
0807 {
0808     struct fwnode_handle *ep;
0809     struct fwnode_handle *fwnode = dev_fwnode(dev);
0810     struct v4l2_fwnode_endpoint bus_cfg = {
0811         .bus_type = V4L2_MBUS_CSI2_DPHY,
0812     };
0813     unsigned int i, j;
0814     u32 clk_volt;
0815     int ret;
0816 
0817     if (!fwnode)
0818         return -EINVAL;
0819 
0820     ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
0821     if (!ep)
0822         return -ENXIO;
0823 
0824     ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
0825     fwnode_handle_put(ep);
0826     if (ret)
0827         return ret;
0828 
0829     /* Optional indication of MIPI clock voltage unit */
0830     ret = fwnode_property_read_u32(ep, "ovti,mipi-clock-voltage",
0831                        &clk_volt);
0832 
0833     if (!ret)
0834         ov02a10->mipi_clock_voltage = clk_volt;
0835 
0836     for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
0837         for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
0838             if (link_freq_menu_items[i] ==
0839                 bus_cfg.link_frequencies[j])
0840                 break;
0841         }
0842 
0843         if (j == bus_cfg.nr_of_link_frequencies) {
0844             dev_err(dev, "no link frequency %lld supported\n",
0845                 link_freq_menu_items[i]);
0846             ret = -EINVAL;
0847             break;
0848         }
0849     }
0850 
0851     v4l2_fwnode_endpoint_free(&bus_cfg);
0852 
0853     return ret;
0854 }
0855 
0856 static int ov02a10_probe(struct i2c_client *client)
0857 {
0858     struct device *dev = &client->dev;
0859     struct ov02a10 *ov02a10;
0860     unsigned int i;
0861     unsigned int rotation;
0862     int ret;
0863 
0864     ov02a10 = devm_kzalloc(dev, sizeof(*ov02a10), GFP_KERNEL);
0865     if (!ov02a10)
0866         return -ENOMEM;
0867 
0868     ret = ov02a10_check_hwcfg(dev, ov02a10);
0869     if (ret)
0870         return dev_err_probe(dev, ret,
0871                      "failed to check HW configuration\n");
0872 
0873     v4l2_i2c_subdev_init(&ov02a10->subdev, client, &ov02a10_subdev_ops);
0874 
0875     ov02a10->mipi_clock_voltage = OV02A10_MIPI_TX_SPEED_DEFAULT;
0876     ov02a10->fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10;
0877 
0878     /* Optional indication of physical rotation of sensor */
0879     rotation = 0;
0880     device_property_read_u32(dev, "rotation", &rotation);
0881     if (rotation == 180) {
0882         ov02a10->upside_down = true;
0883         ov02a10->fmt.code = MEDIA_BUS_FMT_SRGGB10_1X10;
0884     }
0885 
0886     ov02a10->eclk = devm_clk_get(dev, "eclk");
0887     if (IS_ERR(ov02a10->eclk))
0888         return dev_err_probe(dev, PTR_ERR(ov02a10->eclk),
0889                      "failed to get eclk\n");
0890 
0891     ret = device_property_read_u32(dev, "clock-frequency",
0892                        &ov02a10->eclk_freq);
0893     if (ret < 0)
0894         return dev_err_probe(dev, ret,
0895                      "failed to get eclk frequency\n");
0896 
0897     ret = clk_set_rate(ov02a10->eclk, ov02a10->eclk_freq);
0898     if (ret < 0)
0899         return dev_err_probe(dev, ret,
0900                      "failed to set eclk frequency (24MHz)\n");
0901 
0902     if (clk_get_rate(ov02a10->eclk) != OV02A10_ECLK_FREQ)
0903         dev_warn(dev, "eclk mismatched, mode is based on 24MHz\n");
0904 
0905     ov02a10->pd_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_HIGH);
0906     if (IS_ERR(ov02a10->pd_gpio))
0907         return dev_err_probe(dev, PTR_ERR(ov02a10->pd_gpio),
0908                      "failed to get powerdown-gpios\n");
0909 
0910     ov02a10->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
0911     if (IS_ERR(ov02a10->rst_gpio))
0912         return dev_err_probe(dev, PTR_ERR(ov02a10->rst_gpio),
0913                      "failed to get reset-gpios\n");
0914 
0915     for (i = 0; i < ARRAY_SIZE(ov02a10_supply_names); i++)
0916         ov02a10->supplies[i].supply = ov02a10_supply_names[i];
0917 
0918     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02a10_supply_names),
0919                       ov02a10->supplies);
0920     if (ret)
0921         return dev_err_probe(dev, ret, "failed to get regulators\n");
0922 
0923     mutex_init(&ov02a10->mutex);
0924 
0925     /* Set default mode */
0926     ov02a10->cur_mode = &supported_modes[0];
0927 
0928     ret = ov02a10_initialize_controls(ov02a10);
0929     if (ret) {
0930         dev_err_probe(dev, ret, "failed to initialize controls\n");
0931         goto err_destroy_mutex;
0932     }
0933 
0934     /* Initialize subdev */
0935     ov02a10->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
0936     ov02a10->subdev.entity.ops = &ov02a10_subdev_entity_ops;
0937     ov02a10->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
0938     ov02a10->pad.flags = MEDIA_PAD_FL_SOURCE;
0939 
0940     ret = media_entity_pads_init(&ov02a10->subdev.entity, 1, &ov02a10->pad);
0941     if (ret < 0) {
0942         dev_err_probe(dev, ret, "failed to initialize entity pads\n");
0943         goto err_free_handler;
0944     }
0945 
0946     pm_runtime_enable(dev);
0947     if (!pm_runtime_enabled(dev)) {
0948         ret = ov02a10_power_on(dev);
0949         if (ret < 0) {
0950             dev_err_probe(dev, ret, "failed to power on\n");
0951             goto err_clean_entity;
0952         }
0953     }
0954 
0955     ret = v4l2_async_register_subdev(&ov02a10->subdev);
0956     if (ret) {
0957         dev_err_probe(dev, ret, "failed to register V4L2 subdev\n");
0958         goto err_power_off;
0959     }
0960 
0961     return 0;
0962 
0963 err_power_off:
0964     if (pm_runtime_enabled(dev))
0965         pm_runtime_disable(dev);
0966     else
0967         ov02a10_power_off(dev);
0968 err_clean_entity:
0969     media_entity_cleanup(&ov02a10->subdev.entity);
0970 err_free_handler:
0971     v4l2_ctrl_handler_free(ov02a10->subdev.ctrl_handler);
0972 err_destroy_mutex:
0973     mutex_destroy(&ov02a10->mutex);
0974 
0975     return ret;
0976 }
0977 
0978 static int ov02a10_remove(struct i2c_client *client)
0979 {
0980     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0981     struct ov02a10 *ov02a10 = to_ov02a10(sd);
0982 
0983     v4l2_async_unregister_subdev(sd);
0984     media_entity_cleanup(&sd->entity);
0985     v4l2_ctrl_handler_free(sd->ctrl_handler);
0986     pm_runtime_disable(&client->dev);
0987     if (!pm_runtime_status_suspended(&client->dev))
0988         ov02a10_power_off(&client->dev);
0989     pm_runtime_set_suspended(&client->dev);
0990     mutex_destroy(&ov02a10->mutex);
0991 
0992     return 0;
0993 }
0994 
0995 static const struct of_device_id ov02a10_of_match[] = {
0996     { .compatible = "ovti,ov02a10" },
0997     {}
0998 };
0999 MODULE_DEVICE_TABLE(of, ov02a10_of_match);
1000 
1001 static struct i2c_driver ov02a10_i2c_driver = {
1002     .driver = {
1003         .name = "ov02a10",
1004         .pm = &ov02a10_pm_ops,
1005         .of_match_table = ov02a10_of_match,
1006     },
1007     .probe_new  = &ov02a10_probe,
1008     .remove     = &ov02a10_remove,
1009 };
1010 module_i2c_driver(ov02a10_i2c_driver);
1011 
1012 MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
1013 MODULE_DESCRIPTION("OmniVision OV02A10 sensor driver");
1014 MODULE_LICENSE("GPL v2");
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