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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
0004  *
0005  * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0006  *
0007  * Based on the MT9M001 driver,
0008  *
0009  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/gpio/consumer.h>
0015 #include <linux/i2c.h>
0016 #include <linux/log2.h>
0017 #include <linux/mutex.h>
0018 #include <linux/of.h>
0019 #include <linux/of_graph.h>
0020 #include <linux/regmap.h>
0021 #include <linux/slab.h>
0022 #include <linux/videodev2.h>
0023 #include <linux/v4l2-mediabus.h>
0024 #include <linux/module.h>
0025 
0026 #include <media/i2c/mt9v032.h>
0027 #include <media/v4l2-ctrls.h>
0028 #include <media/v4l2-device.h>
0029 #include <media/v4l2-fwnode.h>
0030 #include <media/v4l2-subdev.h>
0031 
0032 /* The first four rows are black rows. The active area spans 753x481 pixels. */
0033 #define MT9V032_PIXEL_ARRAY_HEIGHT          485
0034 #define MT9V032_PIXEL_ARRAY_WIDTH           753
0035 
0036 #define MT9V032_SYSCLK_FREQ_DEF             26600000
0037 
0038 #define MT9V032_CHIP_VERSION                0x00
0039 #define     MT9V032_CHIP_ID_REV1            0x1311
0040 #define     MT9V032_CHIP_ID_REV3            0x1313
0041 #define     MT9V034_CHIP_ID_REV1            0X1324
0042 #define MT9V032_COLUMN_START                0x01
0043 #define     MT9V032_COLUMN_START_MIN        1
0044 #define     MT9V032_COLUMN_START_DEF        1
0045 #define     MT9V032_COLUMN_START_MAX        752
0046 #define MT9V032_ROW_START               0x02
0047 #define     MT9V032_ROW_START_MIN           4
0048 #define     MT9V032_ROW_START_DEF           5
0049 #define     MT9V032_ROW_START_MAX           482
0050 #define MT9V032_WINDOW_HEIGHT               0x03
0051 #define     MT9V032_WINDOW_HEIGHT_MIN       1
0052 #define     MT9V032_WINDOW_HEIGHT_DEF       480
0053 #define     MT9V032_WINDOW_HEIGHT_MAX       480
0054 #define MT9V032_WINDOW_WIDTH                0x04
0055 #define     MT9V032_WINDOW_WIDTH_MIN        1
0056 #define     MT9V032_WINDOW_WIDTH_DEF        752
0057 #define     MT9V032_WINDOW_WIDTH_MAX        752
0058 #define MT9V032_HORIZONTAL_BLANKING         0x05
0059 #define     MT9V032_HORIZONTAL_BLANKING_MIN     43
0060 #define     MT9V034_HORIZONTAL_BLANKING_MIN     61
0061 #define     MT9V032_HORIZONTAL_BLANKING_DEF     94
0062 #define     MT9V032_HORIZONTAL_BLANKING_MAX     1023
0063 #define MT9V032_VERTICAL_BLANKING           0x06
0064 #define     MT9V032_VERTICAL_BLANKING_MIN       4
0065 #define     MT9V034_VERTICAL_BLANKING_MIN       2
0066 #define     MT9V032_VERTICAL_BLANKING_DEF       45
0067 #define     MT9V032_VERTICAL_BLANKING_MAX       3000
0068 #define     MT9V034_VERTICAL_BLANKING_MAX       32288
0069 #define MT9V032_CHIP_CONTROL                0x07
0070 #define     MT9V032_CHIP_CONTROL_MASTER_MODE    (1 << 3)
0071 #define     MT9V032_CHIP_CONTROL_DOUT_ENABLE    (1 << 7)
0072 #define     MT9V032_CHIP_CONTROL_SEQUENTIAL     (1 << 8)
0073 #define MT9V032_SHUTTER_WIDTH1              0x08
0074 #define MT9V032_SHUTTER_WIDTH2              0x09
0075 #define MT9V032_SHUTTER_WIDTH_CONTROL           0x0a
0076 #define MT9V032_TOTAL_SHUTTER_WIDTH         0x0b
0077 #define     MT9V032_TOTAL_SHUTTER_WIDTH_MIN     1
0078 #define     MT9V034_TOTAL_SHUTTER_WIDTH_MIN     0
0079 #define     MT9V032_TOTAL_SHUTTER_WIDTH_DEF     480
0080 #define     MT9V032_TOTAL_SHUTTER_WIDTH_MAX     32767
0081 #define     MT9V034_TOTAL_SHUTTER_WIDTH_MAX     32765
0082 #define MT9V032_RESET                   0x0c
0083 #define MT9V032_READ_MODE               0x0d
0084 #define     MT9V032_READ_MODE_ROW_BIN_MASK      (3 << 0)
0085 #define     MT9V032_READ_MODE_ROW_BIN_SHIFT     0
0086 #define     MT9V032_READ_MODE_COLUMN_BIN_MASK   (3 << 2)
0087 #define     MT9V032_READ_MODE_COLUMN_BIN_SHIFT  2
0088 #define     MT9V032_READ_MODE_ROW_FLIP      (1 << 4)
0089 #define     MT9V032_READ_MODE_COLUMN_FLIP       (1 << 5)
0090 #define     MT9V032_READ_MODE_DARK_COLUMNS      (1 << 6)
0091 #define     MT9V032_READ_MODE_DARK_ROWS     (1 << 7)
0092 #define     MT9V032_READ_MODE_RESERVED      0x0300
0093 #define MT9V032_PIXEL_OPERATION_MODE            0x0f
0094 #define     MT9V034_PIXEL_OPERATION_MODE_HDR    (1 << 0)
0095 #define     MT9V034_PIXEL_OPERATION_MODE_COLOR  (1 << 1)
0096 #define     MT9V032_PIXEL_OPERATION_MODE_COLOR  (1 << 2)
0097 #define     MT9V032_PIXEL_OPERATION_MODE_HDR    (1 << 6)
0098 #define MT9V032_ANALOG_GAIN             0x35
0099 #define     MT9V032_ANALOG_GAIN_MIN         16
0100 #define     MT9V032_ANALOG_GAIN_DEF         16
0101 #define     MT9V032_ANALOG_GAIN_MAX         64
0102 #define MT9V032_MAX_ANALOG_GAIN             0x36
0103 #define     MT9V032_MAX_ANALOG_GAIN_MAX     127
0104 #define MT9V032_FRAME_DARK_AVERAGE          0x42
0105 #define MT9V032_DARK_AVG_THRESH             0x46
0106 #define     MT9V032_DARK_AVG_LOW_THRESH_MASK    (255 << 0)
0107 #define     MT9V032_DARK_AVG_LOW_THRESH_SHIFT   0
0108 #define     MT9V032_DARK_AVG_HIGH_THRESH_MASK   (255 << 8)
0109 #define     MT9V032_DARK_AVG_HIGH_THRESH_SHIFT  8
0110 #define MT9V032_ROW_NOISE_CORR_CONTROL          0x70
0111 #define     MT9V034_ROW_NOISE_CORR_ENABLE       (1 << 0)
0112 #define     MT9V034_ROW_NOISE_CORR_USE_BLK_AVG  (1 << 1)
0113 #define     MT9V032_ROW_NOISE_CORR_ENABLE       (1 << 5)
0114 #define     MT9V032_ROW_NOISE_CORR_USE_BLK_AVG  (1 << 7)
0115 #define MT9V032_PIXEL_CLOCK             0x74
0116 #define MT9V034_PIXEL_CLOCK             0x72
0117 #define     MT9V032_PIXEL_CLOCK_INV_LINE        (1 << 0)
0118 #define     MT9V032_PIXEL_CLOCK_INV_FRAME       (1 << 1)
0119 #define     MT9V032_PIXEL_CLOCK_XOR_LINE        (1 << 2)
0120 #define     MT9V032_PIXEL_CLOCK_CONT_LINE       (1 << 3)
0121 #define     MT9V032_PIXEL_CLOCK_INV_PXL_CLK     (1 << 4)
0122 #define MT9V032_TEST_PATTERN                0x7f
0123 #define     MT9V032_TEST_PATTERN_DATA_MASK      (1023 << 0)
0124 #define     MT9V032_TEST_PATTERN_DATA_SHIFT     0
0125 #define     MT9V032_TEST_PATTERN_USE_DATA       (1 << 10)
0126 #define     MT9V032_TEST_PATTERN_GRAY_MASK      (3 << 11)
0127 #define     MT9V032_TEST_PATTERN_GRAY_NONE      (0 << 11)
0128 #define     MT9V032_TEST_PATTERN_GRAY_VERTICAL  (1 << 11)
0129 #define     MT9V032_TEST_PATTERN_GRAY_HORIZONTAL    (2 << 11)
0130 #define     MT9V032_TEST_PATTERN_GRAY_DIAGONAL  (3 << 11)
0131 #define     MT9V032_TEST_PATTERN_ENABLE     (1 << 13)
0132 #define     MT9V032_TEST_PATTERN_FLIP       (1 << 14)
0133 #define MT9V032_AEGC_DESIRED_BIN            0xa5
0134 #define MT9V032_AEC_UPDATE_FREQUENCY            0xa6
0135 #define MT9V032_AEC_LPF                 0xa8
0136 #define MT9V032_AGC_UPDATE_FREQUENCY            0xa9
0137 #define MT9V032_AGC_LPF                 0xaa
0138 #define MT9V032_AEC_AGC_ENABLE              0xaf
0139 #define     MT9V032_AEC_ENABLE          (1 << 0)
0140 #define     MT9V032_AGC_ENABLE          (1 << 1)
0141 #define MT9V034_AEC_MAX_SHUTTER_WIDTH           0xad
0142 #define MT9V032_AEC_MAX_SHUTTER_WIDTH           0xbd
0143 #define MT9V032_THERMAL_INFO                0xc1
0144 
0145 enum mt9v032_model {
0146     MT9V032_MODEL_V022_COLOR,   /* MT9V022IX7ATC */
0147     MT9V032_MODEL_V022_MONO,    /* MT9V022IX7ATM */
0148     MT9V032_MODEL_V024_COLOR,   /* MT9V024IA7XTC */
0149     MT9V032_MODEL_V024_MONO,    /* MT9V024IA7XTM */
0150     MT9V032_MODEL_V032_COLOR,   /* MT9V032C12STM */
0151     MT9V032_MODEL_V032_MONO,    /* MT9V032C12STC */
0152     MT9V032_MODEL_V034_COLOR,
0153     MT9V032_MODEL_V034_MONO,
0154 };
0155 
0156 struct mt9v032_model_version {
0157     unsigned int version;
0158     const char *name;
0159 };
0160 
0161 struct mt9v032_model_data {
0162     unsigned int min_row_time;
0163     unsigned int min_hblank;
0164     unsigned int min_vblank;
0165     unsigned int max_vblank;
0166     unsigned int min_shutter;
0167     unsigned int max_shutter;
0168     unsigned int pclk_reg;
0169     unsigned int aec_max_shutter_reg;
0170     const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
0171 };
0172 
0173 struct mt9v032_model_info {
0174     const struct mt9v032_model_data *data;
0175     bool color;
0176 };
0177 
0178 static const struct mt9v032_model_version mt9v032_versions[] = {
0179     { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
0180     { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
0181     { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
0182 };
0183 
0184 struct mt9v032 {
0185     struct v4l2_subdev subdev;
0186     struct media_pad pad;
0187 
0188     struct v4l2_mbus_framefmt format;
0189     struct v4l2_rect crop;
0190     unsigned int hratio;
0191     unsigned int vratio;
0192 
0193     struct v4l2_ctrl_handler ctrls;
0194     struct {
0195         struct v4l2_ctrl *link_freq;
0196         struct v4l2_ctrl *pixel_rate;
0197     };
0198 
0199     struct mutex power_lock;
0200     int power_count;
0201 
0202     struct regmap *regmap;
0203     struct clk *clk;
0204     struct gpio_desc *reset_gpio;
0205     struct gpio_desc *standby_gpio;
0206 
0207     struct mt9v032_platform_data *pdata;
0208     const struct mt9v032_model_info *model;
0209     const struct mt9v032_model_version *version;
0210 
0211     u32 sysclk;
0212     u16 aec_agc;
0213     u16 hblank;
0214     struct {
0215         struct v4l2_ctrl *test_pattern;
0216         struct v4l2_ctrl *test_pattern_color;
0217     };
0218 };
0219 
0220 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
0221 {
0222     return container_of(sd, struct mt9v032, subdev);
0223 }
0224 
0225 static int
0226 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
0227 {
0228     struct regmap *map = mt9v032->regmap;
0229     u16 value = mt9v032->aec_agc;
0230     int ret;
0231 
0232     if (enable)
0233         value |= which;
0234     else
0235         value &= ~which;
0236 
0237     ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
0238     if (ret < 0)
0239         return ret;
0240 
0241     mt9v032->aec_agc = value;
0242     return 0;
0243 }
0244 
0245 static int
0246 mt9v032_update_hblank(struct mt9v032 *mt9v032)
0247 {
0248     struct v4l2_rect *crop = &mt9v032->crop;
0249     unsigned int min_hblank = mt9v032->model->data->min_hblank;
0250     unsigned int hblank;
0251 
0252     if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
0253         min_hblank += (mt9v032->hratio - 1) * 10;
0254     min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
0255                min_hblank);
0256     hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
0257 
0258     return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
0259                 hblank);
0260 }
0261 
0262 static int mt9v032_power_on(struct mt9v032 *mt9v032)
0263 {
0264     struct regmap *map = mt9v032->regmap;
0265     int ret;
0266 
0267     gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
0268 
0269     ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
0270     if (ret < 0)
0271         return ret;
0272 
0273     /* System clock has to be enabled before releasing the reset */
0274     ret = clk_prepare_enable(mt9v032->clk);
0275     if (ret)
0276         return ret;
0277 
0278     udelay(1);
0279 
0280     if (mt9v032->reset_gpio) {
0281         gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
0282 
0283         /* After releasing reset we need to wait 10 clock cycles
0284          * before accessing the sensor over I2C. As the minimum SYSCLK
0285          * frequency is 13MHz, waiting 1µs will be enough in the worst
0286          * case.
0287          */
0288         udelay(1);
0289     }
0290 
0291     /* Reset the chip and stop data read out */
0292     ret = regmap_write(map, MT9V032_RESET, 1);
0293     if (ret < 0)
0294         goto err;
0295 
0296     ret = regmap_write(map, MT9V032_RESET, 0);
0297     if (ret < 0)
0298         goto err;
0299 
0300     ret = regmap_write(map, MT9V032_CHIP_CONTROL,
0301                MT9V032_CHIP_CONTROL_MASTER_MODE);
0302     if (ret < 0)
0303         goto err;
0304 
0305     return 0;
0306 
0307 err:
0308     clk_disable_unprepare(mt9v032->clk);
0309     return ret;
0310 }
0311 
0312 static void mt9v032_power_off(struct mt9v032 *mt9v032)
0313 {
0314     clk_disable_unprepare(mt9v032->clk);
0315 }
0316 
0317 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
0318 {
0319     struct regmap *map = mt9v032->regmap;
0320     int ret;
0321 
0322     if (!on) {
0323         mt9v032_power_off(mt9v032);
0324         return 0;
0325     }
0326 
0327     ret = mt9v032_power_on(mt9v032);
0328     if (ret < 0)
0329         return ret;
0330 
0331     /* Configure the pixel clock polarity */
0332     if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
0333         ret = regmap_write(map, mt9v032->model->data->pclk_reg,
0334                 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
0335         if (ret < 0)
0336             return ret;
0337     }
0338 
0339     /* Disable the noise correction algorithm and restore the controls. */
0340     ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
0341     if (ret < 0)
0342         return ret;
0343 
0344     return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
0345 }
0346 
0347 /* -----------------------------------------------------------------------------
0348  * V4L2 subdev video operations
0349  */
0350 
0351 static struct v4l2_mbus_framefmt *
0352 __mt9v032_get_pad_format(struct mt9v032 *mt9v032,
0353              struct v4l2_subdev_state *sd_state,
0354              unsigned int pad, enum v4l2_subdev_format_whence which)
0355 {
0356     switch (which) {
0357     case V4L2_SUBDEV_FORMAT_TRY:
0358         return v4l2_subdev_get_try_format(&mt9v032->subdev, sd_state,
0359                           pad);
0360     case V4L2_SUBDEV_FORMAT_ACTIVE:
0361         return &mt9v032->format;
0362     default:
0363         return NULL;
0364     }
0365 }
0366 
0367 static struct v4l2_rect *
0368 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032,
0369                struct v4l2_subdev_state *sd_state,
0370                unsigned int pad, enum v4l2_subdev_format_whence which)
0371 {
0372     switch (which) {
0373     case V4L2_SUBDEV_FORMAT_TRY:
0374         return v4l2_subdev_get_try_crop(&mt9v032->subdev, sd_state,
0375                         pad);
0376     case V4L2_SUBDEV_FORMAT_ACTIVE:
0377         return &mt9v032->crop;
0378     default:
0379         return NULL;
0380     }
0381 }
0382 
0383 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
0384 {
0385     const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
0386                | MT9V032_CHIP_CONTROL_SEQUENTIAL;
0387     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0388     struct v4l2_rect *crop = &mt9v032->crop;
0389     struct regmap *map = mt9v032->regmap;
0390     unsigned int hbin;
0391     unsigned int vbin;
0392     int ret;
0393 
0394     if (!enable)
0395         return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
0396 
0397     /* Configure the window size and row/column bin */
0398     hbin = fls(mt9v032->hratio) - 1;
0399     vbin = fls(mt9v032->vratio) - 1;
0400     ret = regmap_update_bits(map, MT9V032_READ_MODE,
0401                  ~MT9V032_READ_MODE_RESERVED,
0402                  hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
0403                  vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
0404     if (ret < 0)
0405         return ret;
0406 
0407     ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
0408     if (ret < 0)
0409         return ret;
0410 
0411     ret = regmap_write(map, MT9V032_ROW_START, crop->top);
0412     if (ret < 0)
0413         return ret;
0414 
0415     ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
0416     if (ret < 0)
0417         return ret;
0418 
0419     ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
0420     if (ret < 0)
0421         return ret;
0422 
0423     ret = mt9v032_update_hblank(mt9v032);
0424     if (ret < 0)
0425         return ret;
0426 
0427     /* Switch to master "normal" mode */
0428     return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
0429 }
0430 
0431 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
0432                   struct v4l2_subdev_state *sd_state,
0433                   struct v4l2_subdev_mbus_code_enum *code)
0434 {
0435     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0436 
0437     if (code->index > 0)
0438         return -EINVAL;
0439 
0440     code->code = mt9v032->format.code;
0441     return 0;
0442 }
0443 
0444 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
0445                    struct v4l2_subdev_state *sd_state,
0446                    struct v4l2_subdev_frame_size_enum *fse)
0447 {
0448     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0449 
0450     if (fse->index >= 3)
0451         return -EINVAL;
0452     if (mt9v032->format.code != fse->code)
0453         return -EINVAL;
0454 
0455     fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
0456     fse->max_width = fse->min_width;
0457     fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
0458     fse->max_height = fse->min_height;
0459 
0460     return 0;
0461 }
0462 
0463 static int mt9v032_get_format(struct v4l2_subdev *subdev,
0464                   struct v4l2_subdev_state *sd_state,
0465                   struct v4l2_subdev_format *format)
0466 {
0467     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0468 
0469     format->format = *__mt9v032_get_pad_format(mt9v032, sd_state,
0470                            format->pad,
0471                            format->which);
0472     return 0;
0473 }
0474 
0475 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
0476 {
0477     struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
0478     int ret;
0479 
0480     ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
0481                      mt9v032->sysclk / mt9v032->hratio);
0482     if (ret < 0)
0483         dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
0484 }
0485 
0486 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
0487 {
0488     /* Compute the power-of-two binning factor closest to the input size to
0489      * output size ratio. Given that the output size is bounded by input/4
0490      * and input, a generic implementation would be an ineffective luxury.
0491      */
0492     if (output * 3 > input * 2)
0493         return 1;
0494     if (output * 3 > input)
0495         return 2;
0496     return 4;
0497 }
0498 
0499 static int mt9v032_set_format(struct v4l2_subdev *subdev,
0500                   struct v4l2_subdev_state *sd_state,
0501                   struct v4l2_subdev_format *format)
0502 {
0503     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0504     struct v4l2_mbus_framefmt *__format;
0505     struct v4l2_rect *__crop;
0506     unsigned int width;
0507     unsigned int height;
0508     unsigned int hratio;
0509     unsigned int vratio;
0510 
0511     __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, format->pad,
0512                     format->which);
0513 
0514     /* Clamp the width and height to avoid dividing by zero. */
0515     width = clamp(ALIGN(format->format.width, 2),
0516               max_t(unsigned int, __crop->width / 4,
0517                 MT9V032_WINDOW_WIDTH_MIN),
0518               __crop->width);
0519     height = clamp(ALIGN(format->format.height, 2),
0520                max_t(unsigned int, __crop->height / 4,
0521                  MT9V032_WINDOW_HEIGHT_MIN),
0522                __crop->height);
0523 
0524     hratio = mt9v032_calc_ratio(__crop->width, width);
0525     vratio = mt9v032_calc_ratio(__crop->height, height);
0526 
0527     __format = __mt9v032_get_pad_format(mt9v032, sd_state, format->pad,
0528                         format->which);
0529     __format->width = __crop->width / hratio;
0530     __format->height = __crop->height / vratio;
0531 
0532     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
0533         mt9v032->hratio = hratio;
0534         mt9v032->vratio = vratio;
0535         mt9v032_configure_pixel_rate(mt9v032);
0536     }
0537 
0538     format->format = *__format;
0539 
0540     return 0;
0541 }
0542 
0543 static int mt9v032_get_selection(struct v4l2_subdev *subdev,
0544                  struct v4l2_subdev_state *sd_state,
0545                  struct v4l2_subdev_selection *sel)
0546 {
0547     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0548 
0549     if (sel->target != V4L2_SEL_TGT_CROP)
0550         return -EINVAL;
0551 
0552     sel->r = *__mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad,
0553                      sel->which);
0554     return 0;
0555 }
0556 
0557 static int mt9v032_set_selection(struct v4l2_subdev *subdev,
0558                  struct v4l2_subdev_state *sd_state,
0559                  struct v4l2_subdev_selection *sel)
0560 {
0561     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0562     struct v4l2_mbus_framefmt *__format;
0563     struct v4l2_rect *__crop;
0564     struct v4l2_rect rect;
0565 
0566     if (sel->target != V4L2_SEL_TGT_CROP)
0567         return -EINVAL;
0568 
0569     /* Clamp the crop rectangle boundaries and align them to a non multiple
0570      * of 2 pixels to ensure a GRBG Bayer pattern.
0571      */
0572     rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
0573               MT9V032_COLUMN_START_MIN,
0574               MT9V032_COLUMN_START_MAX);
0575     rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
0576              MT9V032_ROW_START_MIN,
0577              MT9V032_ROW_START_MAX);
0578     rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
0579                  MT9V032_WINDOW_WIDTH_MIN,
0580                  MT9V032_WINDOW_WIDTH_MAX);
0581     rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
0582                   MT9V032_WINDOW_HEIGHT_MIN,
0583                   MT9V032_WINDOW_HEIGHT_MAX);
0584 
0585     rect.width = min_t(unsigned int,
0586                rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
0587     rect.height = min_t(unsigned int,
0588                 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
0589 
0590     __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad,
0591                     sel->which);
0592 
0593     if (rect.width != __crop->width || rect.height != __crop->height) {
0594         /* Reset the output image size if the crop rectangle size has
0595          * been modified.
0596          */
0597         __format = __mt9v032_get_pad_format(mt9v032, sd_state,
0598                             sel->pad,
0599                             sel->which);
0600         __format->width = rect.width;
0601         __format->height = rect.height;
0602         if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
0603             mt9v032->hratio = 1;
0604             mt9v032->vratio = 1;
0605             mt9v032_configure_pixel_rate(mt9v032);
0606         }
0607     }
0608 
0609     *__crop = rect;
0610     sel->r = rect;
0611 
0612     return 0;
0613 }
0614 
0615 /* -----------------------------------------------------------------------------
0616  * V4L2 subdev control operations
0617  */
0618 
0619 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
0620 /*
0621  * Value between 1 and 64 to set the desired bin. This is effectively a measure
0622  * of how bright the image is supposed to be. Both AGC and AEC try to reach
0623  * this.
0624  */
0625 #define V4L2_CID_AEGC_DESIRED_BIN   (V4L2_CID_USER_BASE | 0x1002)
0626 /*
0627  * LPF is the low pass filter capability of the chip. Both AEC and AGC have
0628  * this setting. This limits the speed in which AGC/AEC adjust their settings.
0629  * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used:
0630  *
0631  * if |(calculated new exp - current exp)| > (current exp / 4)
0632  *  next exp = calculated new exp
0633  * else
0634  *  next exp = current exp + ((calculated new exp - current exp) / 2^LPF)
0635  */
0636 #define V4L2_CID_AEC_LPF        (V4L2_CID_USER_BASE | 0x1003)
0637 #define V4L2_CID_AGC_LPF        (V4L2_CID_USER_BASE | 0x1004)
0638 /*
0639  * Value between 0 and 15. This is the number of frames being skipped before
0640  * updating the auto exposure/gain.
0641  */
0642 #define V4L2_CID_AEC_UPDATE_INTERVAL    (V4L2_CID_USER_BASE | 0x1005)
0643 #define V4L2_CID_AGC_UPDATE_INTERVAL    (V4L2_CID_USER_BASE | 0x1006)
0644 /*
0645  * Maximum shutter width used for AEC.
0646  */
0647 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH  (V4L2_CID_USER_BASE | 0x1007)
0648 
0649 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
0650 {
0651     struct mt9v032 *mt9v032 =
0652             container_of(ctrl->handler, struct mt9v032, ctrls);
0653     struct regmap *map = mt9v032->regmap;
0654     u32 freq;
0655     u16 data;
0656 
0657     switch (ctrl->id) {
0658     case V4L2_CID_AUTOGAIN:
0659         return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
0660                           ctrl->val);
0661 
0662     case V4L2_CID_GAIN:
0663         return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
0664 
0665     case V4L2_CID_EXPOSURE_AUTO:
0666         return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
0667                           !ctrl->val);
0668 
0669     case V4L2_CID_EXPOSURE:
0670         return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
0671                     ctrl->val);
0672 
0673     case V4L2_CID_HBLANK:
0674         mt9v032->hblank = ctrl->val;
0675         return mt9v032_update_hblank(mt9v032);
0676 
0677     case V4L2_CID_VBLANK:
0678         return regmap_write(map, MT9V032_VERTICAL_BLANKING,
0679                     ctrl->val);
0680 
0681     case V4L2_CID_PIXEL_RATE:
0682     case V4L2_CID_LINK_FREQ:
0683         if (mt9v032->link_freq == NULL)
0684             break;
0685 
0686         freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
0687         *mt9v032->pixel_rate->p_new.p_s64 = freq;
0688         mt9v032->sysclk = freq;
0689         break;
0690 
0691     case V4L2_CID_TEST_PATTERN:
0692         switch (mt9v032->test_pattern->val) {
0693         case 0:
0694             data = 0;
0695             break;
0696         case 1:
0697             data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
0698                  | MT9V032_TEST_PATTERN_ENABLE;
0699             break;
0700         case 2:
0701             data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
0702                  | MT9V032_TEST_PATTERN_ENABLE;
0703             break;
0704         case 3:
0705             data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
0706                  | MT9V032_TEST_PATTERN_ENABLE;
0707             break;
0708         default:
0709             data = (mt9v032->test_pattern_color->val <<
0710                 MT9V032_TEST_PATTERN_DATA_SHIFT)
0711                  | MT9V032_TEST_PATTERN_USE_DATA
0712                  | MT9V032_TEST_PATTERN_ENABLE
0713                  | MT9V032_TEST_PATTERN_FLIP;
0714             break;
0715         }
0716         return regmap_write(map, MT9V032_TEST_PATTERN, data);
0717 
0718     case V4L2_CID_AEGC_DESIRED_BIN:
0719         return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
0720 
0721     case V4L2_CID_AEC_LPF:
0722         return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
0723 
0724     case V4L2_CID_AGC_LPF:
0725         return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
0726 
0727     case V4L2_CID_AEC_UPDATE_INTERVAL:
0728         return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
0729                     ctrl->val);
0730 
0731     case V4L2_CID_AGC_UPDATE_INTERVAL:
0732         return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
0733                     ctrl->val);
0734 
0735     case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
0736         return regmap_write(map,
0737                     mt9v032->model->data->aec_max_shutter_reg,
0738                     ctrl->val);
0739     }
0740 
0741     return 0;
0742 }
0743 
0744 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
0745     .s_ctrl = mt9v032_s_ctrl,
0746 };
0747 
0748 static const char * const mt9v032_test_pattern_menu[] = {
0749     "Disabled",
0750     "Gray Vertical Shade",
0751     "Gray Horizontal Shade",
0752     "Gray Diagonal Shade",
0753     "Plain",
0754 };
0755 
0756 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
0757     .ops        = &mt9v032_ctrl_ops,
0758     .id     = V4L2_CID_TEST_PATTERN_COLOR,
0759     .type       = V4L2_CTRL_TYPE_INTEGER,
0760     .name       = "Test Pattern Color",
0761     .min        = 0,
0762     .max        = 1023,
0763     .step       = 1,
0764     .def        = 0,
0765     .flags      = 0,
0766 };
0767 
0768 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
0769     {
0770         .ops        = &mt9v032_ctrl_ops,
0771         .id     = V4L2_CID_AEGC_DESIRED_BIN,
0772         .type       = V4L2_CTRL_TYPE_INTEGER,
0773         .name       = "AEC/AGC Desired Bin",
0774         .min        = 1,
0775         .max        = 64,
0776         .step       = 1,
0777         .def        = 58,
0778         .flags      = 0,
0779     }, {
0780         .ops        = &mt9v032_ctrl_ops,
0781         .id     = V4L2_CID_AEC_LPF,
0782         .type       = V4L2_CTRL_TYPE_INTEGER,
0783         .name       = "AEC Low Pass Filter",
0784         .min        = 0,
0785         .max        = 2,
0786         .step       = 1,
0787         .def        = 0,
0788         .flags      = 0,
0789     }, {
0790         .ops        = &mt9v032_ctrl_ops,
0791         .id     = V4L2_CID_AGC_LPF,
0792         .type       = V4L2_CTRL_TYPE_INTEGER,
0793         .name       = "AGC Low Pass Filter",
0794         .min        = 0,
0795         .max        = 2,
0796         .step       = 1,
0797         .def        = 2,
0798         .flags      = 0,
0799     }, {
0800         .ops        = &mt9v032_ctrl_ops,
0801         .id     = V4L2_CID_AEC_UPDATE_INTERVAL,
0802         .type       = V4L2_CTRL_TYPE_INTEGER,
0803         .name       = "AEC Update Interval",
0804         .min        = 0,
0805         .max        = 16,
0806         .step       = 1,
0807         .def        = 2,
0808         .flags      = 0,
0809     }, {
0810         .ops        = &mt9v032_ctrl_ops,
0811         .id     = V4L2_CID_AGC_UPDATE_INTERVAL,
0812         .type       = V4L2_CTRL_TYPE_INTEGER,
0813         .name       = "AGC Update Interval",
0814         .min        = 0,
0815         .max        = 16,
0816         .step       = 1,
0817         .def        = 2,
0818         .flags      = 0,
0819     }
0820 };
0821 
0822 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
0823     .ops        = &mt9v032_ctrl_ops,
0824     .id     = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
0825     .type       = V4L2_CTRL_TYPE_INTEGER,
0826     .name       = "AEC Max Shutter Width",
0827     .min        = 1,
0828     .max        = 2047,
0829     .step       = 1,
0830     .def        = 480,
0831     .flags      = 0,
0832 };
0833 
0834 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
0835     .ops        = &mt9v032_ctrl_ops,
0836     .id     = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
0837     .type       = V4L2_CTRL_TYPE_INTEGER,
0838     .name       = "AEC Max Shutter Width",
0839     .min        = 1,
0840     .max        = 32765,
0841     .step       = 1,
0842     .def        = 480,
0843     .flags      = 0,
0844 };
0845 
0846 /* -----------------------------------------------------------------------------
0847  * V4L2 subdev core operations
0848  */
0849 
0850 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
0851 {
0852     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0853     int ret = 0;
0854 
0855     mutex_lock(&mt9v032->power_lock);
0856 
0857     /* If the power count is modified from 0 to != 0 or from != 0 to 0,
0858      * update the power state.
0859      */
0860     if (mt9v032->power_count == !on) {
0861         ret = __mt9v032_set_power(mt9v032, !!on);
0862         if (ret < 0)
0863             goto done;
0864     }
0865 
0866     /* Update the power count. */
0867     mt9v032->power_count += on ? 1 : -1;
0868     WARN_ON(mt9v032->power_count < 0);
0869 
0870 done:
0871     mutex_unlock(&mt9v032->power_lock);
0872     return ret;
0873 }
0874 
0875 /* -----------------------------------------------------------------------------
0876  * V4L2 subdev internal operations
0877  */
0878 
0879 static int mt9v032_registered(struct v4l2_subdev *subdev)
0880 {
0881     struct i2c_client *client = v4l2_get_subdevdata(subdev);
0882     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0883     unsigned int i;
0884     u32 version;
0885     int ret;
0886 
0887     dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
0888             client->addr);
0889 
0890     ret = mt9v032_power_on(mt9v032);
0891     if (ret < 0) {
0892         dev_err(&client->dev, "MT9V032 power up failed\n");
0893         return ret;
0894     }
0895 
0896     /* Read and check the sensor version */
0897     ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
0898 
0899     mt9v032_power_off(mt9v032);
0900 
0901     if (ret < 0) {
0902         dev_err(&client->dev, "Failed reading chip version\n");
0903         return ret;
0904     }
0905 
0906     for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
0907         if (mt9v032_versions[i].version == version) {
0908             mt9v032->version = &mt9v032_versions[i];
0909             break;
0910         }
0911     }
0912 
0913     if (mt9v032->version == NULL) {
0914         dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
0915             version);
0916         return -ENODEV;
0917     }
0918 
0919     dev_info(&client->dev, "%s detected at address 0x%02x\n",
0920          mt9v032->version->name, client->addr);
0921 
0922     mt9v032_configure_pixel_rate(mt9v032);
0923 
0924     return ret;
0925 }
0926 
0927 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
0928 {
0929     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
0930     struct v4l2_mbus_framefmt *format;
0931     struct v4l2_rect *crop;
0932 
0933     crop = v4l2_subdev_get_try_crop(subdev, fh->state, 0);
0934     crop->left = MT9V032_COLUMN_START_DEF;
0935     crop->top = MT9V032_ROW_START_DEF;
0936     crop->width = MT9V032_WINDOW_WIDTH_DEF;
0937     crop->height = MT9V032_WINDOW_HEIGHT_DEF;
0938 
0939     format = v4l2_subdev_get_try_format(subdev, fh->state, 0);
0940 
0941     if (mt9v032->model->color)
0942         format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
0943     else
0944         format->code = MEDIA_BUS_FMT_Y10_1X10;
0945 
0946     format->width = MT9V032_WINDOW_WIDTH_DEF;
0947     format->height = MT9V032_WINDOW_HEIGHT_DEF;
0948     format->field = V4L2_FIELD_NONE;
0949     format->colorspace = V4L2_COLORSPACE_SRGB;
0950 
0951     return mt9v032_set_power(subdev, 1);
0952 }
0953 
0954 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
0955 {
0956     return mt9v032_set_power(subdev, 0);
0957 }
0958 
0959 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
0960     .s_power    = mt9v032_set_power,
0961 };
0962 
0963 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
0964     .s_stream   = mt9v032_s_stream,
0965 };
0966 
0967 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
0968     .enum_mbus_code = mt9v032_enum_mbus_code,
0969     .enum_frame_size = mt9v032_enum_frame_size,
0970     .get_fmt = mt9v032_get_format,
0971     .set_fmt = mt9v032_set_format,
0972     .get_selection = mt9v032_get_selection,
0973     .set_selection = mt9v032_set_selection,
0974 };
0975 
0976 static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
0977     .core   = &mt9v032_subdev_core_ops,
0978     .video  = &mt9v032_subdev_video_ops,
0979     .pad    = &mt9v032_subdev_pad_ops,
0980 };
0981 
0982 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
0983     .registered = mt9v032_registered,
0984     .open = mt9v032_open,
0985     .close = mt9v032_close,
0986 };
0987 
0988 static const struct regmap_config mt9v032_regmap_config = {
0989     .reg_bits = 8,
0990     .val_bits = 16,
0991     .max_register = 0xff,
0992     .cache_type = REGCACHE_RBTREE,
0993 };
0994 
0995 /* -----------------------------------------------------------------------------
0996  * Driver initialization and probing
0997  */
0998 
0999 static struct mt9v032_platform_data *
1000 mt9v032_get_pdata(struct i2c_client *client)
1001 {
1002     struct mt9v032_platform_data *pdata = NULL;
1003     struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
1004     struct device_node *np;
1005     struct property *prop;
1006 
1007     if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1008         return client->dev.platform_data;
1009 
1010     np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1011     if (!np)
1012         return NULL;
1013 
1014     if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
1015         goto done;
1016 
1017     pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1018     if (!pdata)
1019         goto done;
1020 
1021     prop = of_find_property(np, "link-frequencies", NULL);
1022     if (prop) {
1023         u64 *link_freqs;
1024         size_t size = prop->length / sizeof(*link_freqs);
1025 
1026         link_freqs = devm_kcalloc(&client->dev, size,
1027                       sizeof(*link_freqs), GFP_KERNEL);
1028         if (!link_freqs)
1029             goto done;
1030 
1031         if (of_property_read_u64_array(np, "link-frequencies",
1032                            link_freqs, size) < 0)
1033             goto done;
1034 
1035         pdata->link_freqs = link_freqs;
1036         pdata->link_def_freq = link_freqs[0];
1037     }
1038 
1039     pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1040                 V4L2_MBUS_PCLK_SAMPLE_RISING);
1041 
1042 done:
1043     of_node_put(np);
1044     return pdata;
1045 }
1046 
1047 static int mt9v032_probe(struct i2c_client *client,
1048         const struct i2c_device_id *did)
1049 {
1050     struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
1051     struct mt9v032 *mt9v032;
1052     unsigned int i;
1053     int ret;
1054 
1055     mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
1056     if (!mt9v032)
1057         return -ENOMEM;
1058 
1059     mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1060     if (IS_ERR(mt9v032->regmap))
1061         return PTR_ERR(mt9v032->regmap);
1062 
1063     mt9v032->clk = devm_clk_get(&client->dev, NULL);
1064     if (IS_ERR(mt9v032->clk))
1065         return PTR_ERR(mt9v032->clk);
1066 
1067     mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1068                               GPIOD_OUT_HIGH);
1069     if (IS_ERR(mt9v032->reset_gpio))
1070         return PTR_ERR(mt9v032->reset_gpio);
1071 
1072     mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1073                             GPIOD_OUT_LOW);
1074     if (IS_ERR(mt9v032->standby_gpio))
1075         return PTR_ERR(mt9v032->standby_gpio);
1076 
1077     mutex_init(&mt9v032->power_lock);
1078     mt9v032->pdata = pdata;
1079     mt9v032->model = (const void *)did->driver_data;
1080 
1081     v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1082                    ARRAY_SIZE(mt9v032_aegc_controls));
1083 
1084     v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1085               V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1086     v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1087               V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1088               MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1089     v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1090                    V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1091                    V4L2_EXPOSURE_AUTO);
1092     v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1093               V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1094               mt9v032->model->data->max_shutter, 1,
1095               MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
1096     v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1097               V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
1098               MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1099               MT9V032_HORIZONTAL_BLANKING_DEF);
1100     v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1101               V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1102               mt9v032->model->data->max_vblank, 1,
1103               MT9V032_VERTICAL_BLANKING_DEF);
1104     mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1105                 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1106                 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1107                 mt9v032_test_pattern_menu);
1108     mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1109                       &mt9v032_test_pattern_color, NULL);
1110 
1111     v4l2_ctrl_new_custom(&mt9v032->ctrls,
1112                  mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1113                  NULL);
1114     for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1115         v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1116                      NULL);
1117 
1118     v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
1119 
1120     mt9v032->pixel_rate =
1121         v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1122                   V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1123 
1124     if (pdata && pdata->link_freqs) {
1125         unsigned int def = 0;
1126 
1127         for (i = 0; pdata->link_freqs[i]; ++i) {
1128             if (pdata->link_freqs[i] == pdata->link_def_freq)
1129                 def = i;
1130         }
1131 
1132         mt9v032->link_freq =
1133             v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1134                            &mt9v032_ctrl_ops,
1135                            V4L2_CID_LINK_FREQ, i - 1, def,
1136                            pdata->link_freqs);
1137         v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1138     }
1139 
1140 
1141     mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1142 
1143     if (mt9v032->ctrls.error) {
1144         dev_err(&client->dev, "control initialization error %d\n",
1145             mt9v032->ctrls.error);
1146         ret = mt9v032->ctrls.error;
1147         goto err;
1148     }
1149 
1150     mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1151     mt9v032->crop.top = MT9V032_ROW_START_DEF;
1152     mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1153     mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1154 
1155     if (mt9v032->model->color)
1156         mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1157     else
1158         mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1159 
1160     mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1161     mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1162     mt9v032->format.field = V4L2_FIELD_NONE;
1163     mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1164 
1165     mt9v032->hratio = 1;
1166     mt9v032->vratio = 1;
1167 
1168     mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1169     mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1170     mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1171 
1172     v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1173     mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1174     mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1175 
1176     mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1177     mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1178     ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
1179     if (ret < 0)
1180         goto err;
1181 
1182     mt9v032->subdev.dev = &client->dev;
1183     ret = v4l2_async_register_subdev(&mt9v032->subdev);
1184     if (ret < 0)
1185         goto err;
1186 
1187     return 0;
1188 
1189 err:
1190     media_entity_cleanup(&mt9v032->subdev.entity);
1191     v4l2_ctrl_handler_free(&mt9v032->ctrls);
1192     return ret;
1193 }
1194 
1195 static int mt9v032_remove(struct i2c_client *client)
1196 {
1197     struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1198     struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1199 
1200     v4l2_async_unregister_subdev(subdev);
1201     v4l2_ctrl_handler_free(&mt9v032->ctrls);
1202     media_entity_cleanup(&subdev->entity);
1203 
1204     return 0;
1205 }
1206 
1207 static const struct mt9v032_model_data mt9v032_model_data[] = {
1208     {
1209         /* MT9V022, MT9V032 revisions 1/2/3 */
1210         .min_row_time = 660,
1211         .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1212         .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1213         .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1214         .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1215         .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1216         .pclk_reg = MT9V032_PIXEL_CLOCK,
1217         .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1218         .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1219     }, {
1220         /* MT9V024, MT9V034 */
1221         .min_row_time = 690,
1222         .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1223         .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1224         .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1225         .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1226         .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1227         .pclk_reg = MT9V034_PIXEL_CLOCK,
1228         .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1229         .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1230     },
1231 };
1232 
1233 static const struct mt9v032_model_info mt9v032_models[] = {
1234     [MT9V032_MODEL_V022_COLOR] = {
1235         .data = &mt9v032_model_data[0],
1236         .color = true,
1237     },
1238     [MT9V032_MODEL_V022_MONO] = {
1239         .data = &mt9v032_model_data[0],
1240         .color = false,
1241     },
1242     [MT9V032_MODEL_V024_COLOR] = {
1243         .data = &mt9v032_model_data[1],
1244         .color = true,
1245     },
1246     [MT9V032_MODEL_V024_MONO] = {
1247         .data = &mt9v032_model_data[1],
1248         .color = false,
1249     },
1250     [MT9V032_MODEL_V032_COLOR] = {
1251         .data = &mt9v032_model_data[0],
1252         .color = true,
1253     },
1254     [MT9V032_MODEL_V032_MONO] = {
1255         .data = &mt9v032_model_data[0],
1256         .color = false,
1257     },
1258     [MT9V032_MODEL_V034_COLOR] = {
1259         .data = &mt9v032_model_data[1],
1260         .color = true,
1261     },
1262     [MT9V032_MODEL_V034_MONO] = {
1263         .data = &mt9v032_model_data[1],
1264         .color = false,
1265     },
1266 };
1267 
1268 static const struct i2c_device_id mt9v032_id[] = {
1269     { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1270     { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1271     { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1272     { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1273     { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1274     { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1275     { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1276     { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1277     { }
1278 };
1279 MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1280 
1281 #if IS_ENABLED(CONFIG_OF)
1282 static const struct of_device_id mt9v032_of_match[] = {
1283     { .compatible = "aptina,mt9v022" },
1284     { .compatible = "aptina,mt9v022m" },
1285     { .compatible = "aptina,mt9v024" },
1286     { .compatible = "aptina,mt9v024m" },
1287     { .compatible = "aptina,mt9v032" },
1288     { .compatible = "aptina,mt9v032m" },
1289     { .compatible = "aptina,mt9v034" },
1290     { .compatible = "aptina,mt9v034m" },
1291     { /* Sentinel */ }
1292 };
1293 MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1294 #endif
1295 
1296 static struct i2c_driver mt9v032_driver = {
1297     .driver = {
1298         .name = "mt9v032",
1299         .of_match_table = of_match_ptr(mt9v032_of_match),
1300     },
1301     .probe      = mt9v032_probe,
1302     .remove     = mt9v032_remove,
1303     .id_table   = mt9v032_id,
1304 };
1305 
1306 module_i2c_driver(mt9v032_driver);
1307 
1308 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1309 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1310 MODULE_LICENSE("GPL");
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