media/i2c/mt9v011.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // mt9v011 -Micron 1/4-Inch VGA Digital Image Sensor
0004 //
0005 // Copyright (c) 2009 Mauro Carvalho Chehab <mchehab@kernel.org>
0006
0007 #include <linux/i2c.h>
0008 #include <linux/slab.h>
0009 #include <linux/videodev2.h>
0010 #include <linux/delay.h>
0011 #include <linux/module.h>
0012 #include <asm/div64.h>
0013 #include <media/v4l2-device.h>
0014 #include <media/v4l2-ctrls.h>
0015 #include <media/i2c/mt9v011.h>
0016
0017 MODULE_DESCRIPTION("Micron mt9v011 sensor driver");
0018 MODULE_AUTHOR("Mauro Carvalho Chehab");
0019 MODULE_LICENSE("GPL v2");
0020
0021 static int debug;
0022 module_param(debug, int, 0);
0023 MODULE_PARM_DESC(debug, "Debug level (0-2)");
0024
0025 #define R00_MT9V011_CHIP_VERSION    0x00
0026 #define R01_MT9V011_ROWSTART        0x01
0027 #define R02_MT9V011_COLSTART        0x02
0028 #define R03_MT9V011_HEIGHT      0x03
0029 #define R04_MT9V011_WIDTH       0x04
0030 #define R05_MT9V011_HBLANK      0x05
0031 #define R06_MT9V011_VBLANK      0x06
0032 #define R07_MT9V011_OUT_CTRL        0x07
0033 #define R09_MT9V011_SHUTTER_WIDTH   0x09
0034 #define R0A_MT9V011_CLK_SPEED       0x0a
0035 #define R0B_MT9V011_RESTART     0x0b
0036 #define R0C_MT9V011_SHUTTER_DELAY   0x0c
0037 #define R0D_MT9V011_RESET       0x0d
0038 #define R1E_MT9V011_DIGITAL_ZOOM    0x1e
0039 #define R20_MT9V011_READ_MODE       0x20
0040 #define R2B_MT9V011_GREEN_1_GAIN    0x2b
0041 #define R2C_MT9V011_BLUE_GAIN       0x2c
0042 #define R2D_MT9V011_RED_GAIN        0x2d
0043 #define R2E_MT9V011_GREEN_2_GAIN    0x2e
0044 #define R35_MT9V011_GLOBAL_GAIN     0x35
0045 #define RF1_MT9V011_CHIP_ENABLE     0xf1
0046
0047 #define MT9V011_VERSION         0x8232
0048 #define MT9V011_REV_B_VERSION       0x8243
0049
0050 struct mt9v011 {
0051     struct v4l2_subdev sd;
0052 #ifdef CONFIG_MEDIA_CONTROLLER
0053     struct media_pad pad;
0054 #endif
0055     struct v4l2_ctrl_handler ctrls;
0056     unsigned width, height;
0057     unsigned xtal;
0058     unsigned hflip:1;
0059     unsigned vflip:1;
0060
0061     u16 global_gain, exposure;
0062     s16 red_bal, blue_bal;
0063 };
0064
0065 static inline struct mt9v011 *to_mt9v011(struct v4l2_subdev *sd)
0066 {
0067     return container_of(sd, struct mt9v011, sd);
0068 }
0069
0070 static int mt9v011_read(struct v4l2_subdev *sd, unsigned char addr)
0071 {
0072     struct i2c_client *c = v4l2_get_subdevdata(sd);
0073     __be16 buffer;
0074     int rc, val;
0075
0076     rc = i2c_master_send(c, &addr, 1);
0077     if (rc != 1)
0078         v4l2_dbg(0, debug, sd,
0079              "i2c i/o error: rc == %d (should be 1)\n", rc);
0080
0081     msleep(10);
0082
0083     rc = i2c_master_recv(c, (char *)&buffer, 2);
0084     if (rc != 2)
0085         v4l2_dbg(0, debug, sd,
0086              "i2c i/o error: rc == %d (should be 2)\n", rc);
0087
0088     val = be16_to_cpu(buffer);
0089
0090     v4l2_dbg(2, debug, sd, "mt9v011: read 0x%02x = 0x%04x\n", addr, val);
0091
0092     return val;
0093 }
0094
0095 static void mt9v011_write(struct v4l2_subdev *sd, unsigned char addr,
0096                  u16 value)
0097 {
0098     struct i2c_client *c = v4l2_get_subdevdata(sd);
0099     unsigned char buffer[3];
0100     int rc;
0101
0102     buffer[0] = addr;
0103     buffer[1] = value >> 8;
0104     buffer[2] = value & 0xff;
0105
0106     v4l2_dbg(2, debug, sd,
0107          "mt9v011: writing 0x%02x 0x%04x\n", buffer[0], value);
0108     rc = i2c_master_send(c, buffer, 3);
0109     if (rc != 3)
0110         v4l2_dbg(0, debug, sd,
0111              "i2c i/o error: rc == %d (should be 3)\n", rc);
0112 }
0113
0114
0115 struct i2c_reg_value {
0116     unsigned char reg;
0117     u16           value;
0118 };
0119
0120 /*
0121  * Values used at the original driver
0122  * Some values are marked as Reserved at the datasheet
0123  */
0124 static const struct i2c_reg_value mt9v011_init_default[] = {
0125         { R0D_MT9V011_RESET, 0x0001 },
0126         { R0D_MT9V011_RESET, 0x0000 },
0127
0128         { R0C_MT9V011_SHUTTER_DELAY, 0x0000 },
0129         { R09_MT9V011_SHUTTER_WIDTH, 0x1fc },
0130
0131         { R0A_MT9V011_CLK_SPEED, 0x0000 },
0132         { R1E_MT9V011_DIGITAL_ZOOM,  0x0000 },
0133
0134         { R07_MT9V011_OUT_CTRL, 0x0002 },   /* chip enable */
0135 };
0136
0137
0138 static u16 calc_mt9v011_gain(s16 lineargain)
0139 {
0140
0141     u16 digitalgain = 0;
0142     u16 analogmult = 0;
0143     u16 analoginit = 0;
0144
0145     if (lineargain < 0)
0146         lineargain = 0;
0147
0148     /* recommended minimum */
0149     lineargain += 0x0020;
0150
0151     if (lineargain > 2047)
0152         lineargain = 2047;
0153
0154     if (lineargain > 1023) {
0155         digitalgain = 3;
0156         analogmult = 3;
0157         analoginit = lineargain / 16;
0158     } else if (lineargain > 511) {
0159         digitalgain = 1;
0160         analogmult = 3;
0161         analoginit = lineargain / 8;
0162     } else if (lineargain > 255) {
0163         analogmult = 3;
0164         analoginit = lineargain / 4;
0165     } else if (lineargain > 127) {
0166         analogmult = 1;
0167         analoginit = lineargain / 2;
0168     } else
0169         analoginit = lineargain;
0170
0171     return analoginit + (analogmult << 7) + (digitalgain << 9);
0172
0173 }
0174
0175 static void set_balance(struct v4l2_subdev *sd)
0176 {
0177     struct mt9v011 *core = to_mt9v011(sd);
0178     u16 green_gain, blue_gain, red_gain;
0179     u16 exposure;
0180     s16 bal;
0181
0182     exposure = core->exposure;
0183
0184     green_gain = calc_mt9v011_gain(core->global_gain);
0185
0186     bal = core->global_gain;
0187     bal += (core->blue_bal * core->global_gain / (1 << 7));
0188     blue_gain = calc_mt9v011_gain(bal);
0189
0190     bal = core->global_gain;
0191     bal += (core->red_bal * core->global_gain / (1 << 7));
0192     red_gain = calc_mt9v011_gain(bal);
0193
0194     mt9v011_write(sd, R2B_MT9V011_GREEN_1_GAIN, green_gain);
0195     mt9v011_write(sd, R2E_MT9V011_GREEN_2_GAIN, green_gain);
0196     mt9v011_write(sd, R2C_MT9V011_BLUE_GAIN, blue_gain);
0197     mt9v011_write(sd, R2D_MT9V011_RED_GAIN, red_gain);
0198     mt9v011_write(sd, R09_MT9V011_SHUTTER_WIDTH, exposure);
0199 }
0200
0201 static void calc_fps(struct v4l2_subdev *sd, u32 *numerator, u32 *denominator)
0202 {
0203     struct mt9v011 *core = to_mt9v011(sd);
0204     unsigned height, width, hblank, vblank, speed;
0205     unsigned row_time, t_time;
0206     u64 frames_per_ms;
0207     unsigned tmp;
0208
0209     height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
0210     width = mt9v011_read(sd, R04_MT9V011_WIDTH);
0211     hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
0212     vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);
0213     speed = mt9v011_read(sd, R0A_MT9V011_CLK_SPEED);
0214
0215     row_time = (width + 113 + hblank) * (speed + 2);
0216     t_time = row_time * (height + vblank + 1);
0217
0218     frames_per_ms = core->xtal * 1000l;
0219     do_div(frames_per_ms, t_time);
0220     tmp = frames_per_ms;
0221
0222     v4l2_dbg(1, debug, sd, "Programmed to %u.%03u fps (%d pixel clcks)\n",
0223         tmp / 1000, tmp % 1000, t_time);
0224
0225     if (numerator && denominator) {
0226         *numerator = 1000;
0227         *denominator = (u32)frames_per_ms;
0228     }
0229 }
0230
0231 static u16 calc_speed(struct v4l2_subdev *sd, u32 numerator, u32 denominator)
0232 {
0233     struct mt9v011 *core = to_mt9v011(sd);
0234     unsigned height, width, hblank, vblank;
0235     unsigned row_time, line_time;
0236     u64 t_time, speed;
0237
0238     /* Avoid bogus calculus */
0239     if (!numerator || !denominator)
0240         return 0;
0241
0242     height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
0243     width = mt9v011_read(sd, R04_MT9V011_WIDTH);
0244     hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
0245     vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);
0246
0247     row_time = width + 113 + hblank;
0248     line_time = height + vblank + 1;
0249
0250     t_time = core->xtal * ((u64)numerator);
0251     /* round to the closest value */
0252     t_time += denominator / 2;
0253     do_div(t_time, denominator);
0254
0255     speed = t_time;
0256     do_div(speed, row_time * line_time);
0257
0258     /* Avoid having a negative value for speed */
0259     if (speed < 2)
0260         speed = 0;
0261     else
0262         speed -= 2;
0263
0264     /* Avoid speed overflow */
0265     if (speed > 15)
0266         return 15;
0267
0268     return (u16)speed;
0269 }
0270
0271 static void set_res(struct v4l2_subdev *sd)
0272 {
0273     struct mt9v011 *core = to_mt9v011(sd);
0274     unsigned vstart, hstart;
0275
0276     /*
0277      * The mt9v011 doesn't have scaling. So, in order to select the desired
0278      * resolution, we're cropping at the middle of the sensor.
0279      * hblank and vblank should be adjusted, in order to warrant that
0280      * we'll preserve the line timings for 30 fps, no matter what resolution
0281      * is selected.
0282      * NOTE: datasheet says that width (and height) should be filled with
0283      * width-1. However, this doesn't work, since one pixel per line will
0284      * be missing.
0285      */
0286
0287     hstart = 20 + (640 - core->width) / 2;
0288     mt9v011_write(sd, R02_MT9V011_COLSTART, hstart);
0289     mt9v011_write(sd, R04_MT9V011_WIDTH, core->width);
0290     mt9v011_write(sd, R05_MT9V011_HBLANK, 771 - core->width);
0291
0292     vstart = 8 + (480 - core->height) / 2;
0293     mt9v011_write(sd, R01_MT9V011_ROWSTART, vstart);
0294     mt9v011_write(sd, R03_MT9V011_HEIGHT, core->height);
0295     mt9v011_write(sd, R06_MT9V011_VBLANK, 508 - core->height);
0296
0297     calc_fps(sd, NULL, NULL);
0298 };
0299
0300 static void set_read_mode(struct v4l2_subdev *sd)
0301 {
0302     struct mt9v011 *core = to_mt9v011(sd);
0303     unsigned mode = 0x1000;
0304
0305     if (core->hflip)
0306         mode |= 0x4000;
0307
0308     if (core->vflip)
0309         mode |= 0x8000;
0310
0311     mt9v011_write(sd, R20_MT9V011_READ_MODE, mode);
0312 }
0313
0314 static int mt9v011_reset(struct v4l2_subdev *sd, u32 val)
0315 {
0316     int i;
0317
0318     for (i = 0; i < ARRAY_SIZE(mt9v011_init_default); i++)
0319         mt9v011_write(sd, mt9v011_init_default[i].reg,
0320                    mt9v011_init_default[i].value);
0321
0322     set_balance(sd);
0323     set_res(sd);
0324     set_read_mode(sd);
0325
0326     return 0;
0327 }
0328
0329 static int mt9v011_enum_mbus_code(struct v4l2_subdev *sd,
0330         struct v4l2_subdev_state *sd_state,
0331         struct v4l2_subdev_mbus_code_enum *code)
0332 {
0333     if (code->pad || code->index > 0)
0334         return -EINVAL;
0335
0336     code->code = MEDIA_BUS_FMT_SGRBG8_1X8;
0337     return 0;
0338 }
0339
0340 static int mt9v011_set_fmt(struct v4l2_subdev *sd,
0341         struct v4l2_subdev_state *sd_state,
0342         struct v4l2_subdev_format *format)
0343 {
0344     struct v4l2_mbus_framefmt *fmt = &format->format;
0345     struct mt9v011 *core = to_mt9v011(sd);
0346
0347     if (format->pad || fmt->code != MEDIA_BUS_FMT_SGRBG8_1X8)
0348         return -EINVAL;
0349
0350     v4l_bound_align_image(&fmt->width, 48, 639, 1,
0351                   &fmt->height, 32, 480, 1, 0);
0352     fmt->field = V4L2_FIELD_NONE;
0353     fmt->colorspace = V4L2_COLORSPACE_SRGB;
0354
0355     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
0356         core->width = fmt->width;
0357         core->height = fmt->height;
0358
0359         set_res(sd);
0360     } else {
0361         sd_state->pads->try_fmt = *fmt;
0362     }
0363
0364     return 0;
0365 }
0366
0367 static int mt9v011_g_frame_interval(struct v4l2_subdev *sd,
0368                     struct v4l2_subdev_frame_interval *ival)
0369 {
0370     calc_fps(sd,
0371          &ival->interval.numerator,
0372          &ival->interval.denominator);
0373
0374     return 0;
0375 }
0376
0377 static int mt9v011_s_frame_interval(struct v4l2_subdev *sd,
0378                     struct v4l2_subdev_frame_interval *ival)
0379 {
0380     struct v4l2_fract *tpf = &ival->interval;
0381     u16 speed;
0382
0383     speed = calc_speed(sd, tpf->numerator, tpf->denominator);
0384
0385     mt9v011_write(sd, R0A_MT9V011_CLK_SPEED, speed);
0386     v4l2_dbg(1, debug, sd, "Setting speed to %d\n", speed);
0387
0388     /* Recalculate and update fps info */
0389     calc_fps(sd, &tpf->numerator, &tpf->denominator);
0390
0391     return 0;
0392 }
0393
0394 #ifdef CONFIG_VIDEO_ADV_DEBUG
0395 static int mt9v011_g_register(struct v4l2_subdev *sd,
0396                   struct v4l2_dbg_register *reg)
0397 {
0398     reg->val = mt9v011_read(sd, reg->reg & 0xff);
0399     reg->size = 2;
0400
0401     return 0;
0402 }
0403
0404 static int mt9v011_s_register(struct v4l2_subdev *sd,
0405                   const struct v4l2_dbg_register *reg)
0406 {
0407     mt9v011_write(sd, reg->reg & 0xff, reg->val & 0xffff);
0408
0409     return 0;
0410 }
0411 #endif
0412
0413 static int mt9v011_s_ctrl(struct v4l2_ctrl *ctrl)
0414 {
0415     struct mt9v011 *core =
0416         container_of(ctrl->handler, struct mt9v011, ctrls);
0417     struct v4l2_subdev *sd = &core->sd;
0418
0419     switch (ctrl->id) {
0420     case V4L2_CID_GAIN:
0421         core->global_gain = ctrl->val;
0422         break;
0423     case V4L2_CID_EXPOSURE:
0424         core->exposure = ctrl->val;
0425         break;
0426     case V4L2_CID_RED_BALANCE:
0427         core->red_bal = ctrl->val;
0428         break;
0429     case V4L2_CID_BLUE_BALANCE:
0430         core->blue_bal = ctrl->val;
0431         break;
0432     case V4L2_CID_HFLIP:
0433         core->hflip = ctrl->val;
0434         set_read_mode(sd);
0435         return 0;
0436     case V4L2_CID_VFLIP:
0437         core->vflip = ctrl->val;
0438         set_read_mode(sd);
0439         return 0;
0440     default:
0441         return -EINVAL;
0442     }
0443
0444     set_balance(sd);
0445     return 0;
0446 }
0447
0448 static const struct v4l2_ctrl_ops mt9v011_ctrl_ops = {
0449     .s_ctrl = mt9v011_s_ctrl,
0450 };
0451
0452 static const struct v4l2_subdev_core_ops mt9v011_core_ops = {
0453     .reset = mt9v011_reset,
0454 #ifdef CONFIG_VIDEO_ADV_DEBUG
0455     .g_register = mt9v011_g_register,
0456     .s_register = mt9v011_s_register,
0457 #endif
0458 };
0459
0460 static const struct v4l2_subdev_video_ops mt9v011_video_ops = {
0461     .g_frame_interval = mt9v011_g_frame_interval,
0462     .s_frame_interval = mt9v011_s_frame_interval,
0463 };
0464
0465 static const struct v4l2_subdev_pad_ops mt9v011_pad_ops = {
0466     .enum_mbus_code = mt9v011_enum_mbus_code,
0467     .set_fmt = mt9v011_set_fmt,
0468 };
0469
0470 static const struct v4l2_subdev_ops mt9v011_ops = {
0471     .core  = &mt9v011_core_ops,
0472     .video = &mt9v011_video_ops,
0473     .pad   = &mt9v011_pad_ops,
0474 };
0475
0476
0477 /****************************************************************************
0478             I2C Client & Driver
0479  ****************************************************************************/
0480
0481 static int mt9v011_probe(struct i2c_client *c,
0482              const struct i2c_device_id *id)
0483 {
0484     u16 version;
0485     struct mt9v011 *core;
0486     struct v4l2_subdev *sd;
0487 #ifdef CONFIG_MEDIA_CONTROLLER
0488     int ret;
0489 #endif
0490
0491     /* Check if the adapter supports the needed features */
0492     if (!i2c_check_functionality(c->adapter,
0493          I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
0494         return -EIO;
0495
0496     core = devm_kzalloc(&c->dev, sizeof(struct mt9v011), GFP_KERNEL);
0497     if (!core)
0498         return -ENOMEM;
0499
0500     sd = &core->sd;
0501     v4l2_i2c_subdev_init(sd, c, &mt9v011_ops);
0502
0503 #ifdef CONFIG_MEDIA_CONTROLLER
0504     core->pad.flags = MEDIA_PAD_FL_SOURCE;
0505     sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
0506
0507     ret = media_entity_pads_init(&sd->entity, 1, &core->pad);
0508     if (ret < 0)
0509         return ret;
0510 #endif
0511
0512     /* Check if the sensor is really a MT9V011 */
0513     version = mt9v011_read(sd, R00_MT9V011_CHIP_VERSION);
0514     if ((version != MT9V011_VERSION) &&
0515         (version != MT9V011_REV_B_VERSION)) {
0516         v4l2_info(sd, "*** unknown micron chip detected (0x%04x).\n",
0517               version);
0518         return -EINVAL;
0519     }
0520
0521     v4l2_ctrl_handler_init(&core->ctrls, 5);
0522     v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
0523               V4L2_CID_GAIN, 0, (1 << 12) - 1 - 0x20, 1, 0x20);
0524     v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
0525               V4L2_CID_EXPOSURE, 0, 2047, 1, 0x01fc);
0526     v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
0527               V4L2_CID_RED_BALANCE, -(1 << 9), (1 << 9) - 1, 1, 0);
0528     v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
0529               V4L2_CID_BLUE_BALANCE, -(1 << 9), (1 << 9) - 1, 1, 0);
0530     v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
0531               V4L2_CID_HFLIP, 0, 1, 1, 0);
0532     v4l2_ctrl_new_std(&core->ctrls, &mt9v011_ctrl_ops,
0533               V4L2_CID_VFLIP, 0, 1, 1, 0);
0534
0535     if (core->ctrls.error) {
0536         int ret = core->ctrls.error;
0537
0538         v4l2_err(sd, "control initialization error %d\n", ret);
0539         v4l2_ctrl_handler_free(&core->ctrls);
0540         return ret;
0541     }
0542     core->sd.ctrl_handler = &core->ctrls;
0543
0544     core->global_gain = 0x0024;
0545     core->exposure = 0x01fc;
0546     core->width  = 640;
0547     core->height = 480;
0548     core->xtal = 27000000;  /* Hz */
0549
0550     if (c->dev.platform_data) {
0551         struct mt9v011_platform_data *pdata = c->dev.platform_data;
0552
0553         core->xtal = pdata->xtal;
0554         v4l2_dbg(1, debug, sd, "xtal set to %d.%03d MHz\n",
0555             core->xtal / 1000000, (core->xtal / 1000) % 1000);
0556     }
0557
0558     v4l_info(c, "chip found @ 0x%02x (%s - chip version 0x%04x)\n",
0559          c->addr << 1, c->adapter->name, version);
0560
0561     return 0;
0562 }
0563
0564 static int mt9v011_remove(struct i2c_client *c)
0565 {
0566     struct v4l2_subdev *sd = i2c_get_clientdata(c);
0567     struct mt9v011 *core = to_mt9v011(sd);
0568
0569     v4l2_dbg(1, debug, sd,
0570         "mt9v011.c: removing mt9v011 adapter on address 0x%x\n",
0571         c->addr << 1);
0572
0573     v4l2_device_unregister_subdev(sd);
0574     v4l2_ctrl_handler_free(&core->ctrls);
0575
0576     return 0;
0577 }
0578
0579 /* ----------------------------------------------------------------------- */
0580
0581 static const struct i2c_device_id mt9v011_id[] = {
0582     { "mt9v011", 0 },
0583     { }
0584 };
0585 MODULE_DEVICE_TABLE(i2c, mt9v011_id);
0586
0587 static struct i2c_driver mt9v011_driver = {
0588     .driver = {
0589         .name   = "mt9v011",
0590     },
0591     .probe      = mt9v011_probe,
0592     .remove     = mt9v011_remove,
0593     .id_table   = mt9v011_id,
0594 };
0595
0596 module_i2c_driver(mt9v011_driver);