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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * mt9t112 Camera Driver
0004  *
0005  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
0006  *
0007  * Copyright (C) 2009 Renesas Solutions Corp.
0008  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
0009  *
0010  * Based on ov772x driver, mt9m111 driver,
0011  *
0012  * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
0013  * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
0014  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
0015  * Copyright (C) 2008 Magnus Damm
0016  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
0017  *
0018  * TODO: This driver lacks support for frame rate control due to missing
0019  *   register level documentation and suitable hardware for testing.
0020  *   v4l-utils compliance tools will report errors.
0021  */
0022 
0023 #include <linux/clk.h>
0024 #include <linux/delay.h>
0025 #include <linux/gpio/consumer.h>
0026 #include <linux/i2c.h>
0027 #include <linux/init.h>
0028 #include <linux/module.h>
0029 #include <linux/slab.h>
0030 #include <linux/v4l2-mediabus.h>
0031 #include <linux/videodev2.h>
0032 
0033 #include <media/i2c/mt9t112.h>
0034 #include <media/v4l2-common.h>
0035 #include <media/v4l2-image-sizes.h>
0036 #include <media/v4l2-subdev.h>
0037 
0038 /* you can check PLL/clock info */
0039 /* #define EXT_CLOCK 24000000 */
0040 
0041 /************************************************************************
0042  *          macro
0043  ***********************************************************************/
0044 /*
0045  * frame size
0046  */
0047 #define MAX_WIDTH   2048
0048 #define MAX_HEIGHT  1536
0049 
0050 /*
0051  * macro of read/write
0052  */
0053 #define ECHECKER(ret, x)        \
0054     do {                \
0055         (ret) = (x);        \
0056         if ((ret) < 0)      \
0057             return (ret);   \
0058     } while (0)
0059 
0060 #define mt9t112_reg_write(ret, client, a, b) \
0061     ECHECKER(ret, __mt9t112_reg_write(client, a, b))
0062 #define mt9t112_mcu_write(ret, client, a, b) \
0063     ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
0064 
0065 #define mt9t112_reg_mask_set(ret, client, a, b, c) \
0066     ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
0067 #define mt9t112_mcu_mask_set(ret, client, a, b, c) \
0068     ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
0069 
0070 #define mt9t112_reg_read(ret, client, a) \
0071     ECHECKER(ret, __mt9t112_reg_read(client, a))
0072 
0073 /*
0074  * Logical address
0075  */
0076 #define _VAR(id, offset, base)  (base | (id & 0x1f) << 10 | (offset & 0x3ff))
0077 #define VAR(id, offset)  _VAR(id, offset, 0x0000)
0078 #define VAR8(id, offset) _VAR(id, offset, 0x8000)
0079 
0080 /************************************************************************
0081  *          struct
0082  ***********************************************************************/
0083 struct mt9t112_format {
0084     u32 code;
0085     enum v4l2_colorspace colorspace;
0086     u16 fmt;
0087     u16 order;
0088 };
0089 
0090 struct mt9t112_priv {
0091     struct v4l2_subdev       subdev;
0092     struct mt9t112_platform_data    *info;
0093     struct i2c_client       *client;
0094     struct v4l2_rect         frame;
0095     struct clk          *clk;
0096     struct gpio_desc        *standby_gpio;
0097     const struct mt9t112_format *format;
0098     int              num_formats;
0099     bool                 init_done;
0100 };
0101 
0102 /************************************************************************
0103  *          supported format
0104  ***********************************************************************/
0105 
0106 static const struct mt9t112_format mt9t112_cfmts[] = {
0107     {
0108         .code       = MEDIA_BUS_FMT_UYVY8_2X8,
0109         .colorspace = V4L2_COLORSPACE_SRGB,
0110         .fmt        = 1,
0111         .order      = 0,
0112     }, {
0113         .code       = MEDIA_BUS_FMT_VYUY8_2X8,
0114         .colorspace = V4L2_COLORSPACE_SRGB,
0115         .fmt        = 1,
0116         .order      = 1,
0117     }, {
0118         .code       = MEDIA_BUS_FMT_YUYV8_2X8,
0119         .colorspace = V4L2_COLORSPACE_SRGB,
0120         .fmt        = 1,
0121         .order      = 2,
0122     }, {
0123         .code       = MEDIA_BUS_FMT_YVYU8_2X8,
0124         .colorspace = V4L2_COLORSPACE_SRGB,
0125         .fmt        = 1,
0126         .order      = 3,
0127     }, {
0128         .code       = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
0129         .colorspace = V4L2_COLORSPACE_SRGB,
0130         .fmt        = 8,
0131         .order      = 2,
0132     }, {
0133         .code       = MEDIA_BUS_FMT_RGB565_2X8_LE,
0134         .colorspace = V4L2_COLORSPACE_SRGB,
0135         .fmt        = 4,
0136         .order      = 2,
0137     },
0138 };
0139 
0140 /************************************************************************
0141  *          general function
0142  ***********************************************************************/
0143 static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
0144 {
0145     return container_of(i2c_get_clientdata(client),
0146                 struct mt9t112_priv,
0147                 subdev);
0148 }
0149 
0150 static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
0151 {
0152     struct i2c_msg msg[2];
0153     u8 buf[2];
0154     int ret;
0155 
0156     command = swab16(command);
0157 
0158     msg[0].addr  = client->addr;
0159     msg[0].flags = 0;
0160     msg[0].len   = 2;
0161     msg[0].buf   = (u8 *)&command;
0162 
0163     msg[1].addr  = client->addr;
0164     msg[1].flags = I2C_M_RD;
0165     msg[1].len   = 2;
0166     msg[1].buf   = buf;
0167 
0168     /*
0169      * If return value of this function is < 0, it means error, else,
0170      * below 16bit is valid data.
0171      */
0172     ret = i2c_transfer(client->adapter, msg, 2);
0173     if (ret < 0)
0174         return ret;
0175 
0176     memcpy(&ret, buf, 2);
0177 
0178     return swab16(ret);
0179 }
0180 
0181 static int __mt9t112_reg_write(const struct i2c_client *client,
0182                    u16 command, u16 data)
0183 {
0184     struct i2c_msg msg;
0185     u8 buf[4];
0186     int ret;
0187 
0188     command = swab16(command);
0189     data = swab16(data);
0190 
0191     memcpy(buf + 0, &command, 2);
0192     memcpy(buf + 2, &data,    2);
0193 
0194     msg.addr  = client->addr;
0195     msg.flags = 0;
0196     msg.len   = 4;
0197     msg.buf   = buf;
0198 
0199     /*
0200      * i2c_transfer return message length, but this function should
0201      * return 0 if correct case.
0202      */
0203     ret = i2c_transfer(client->adapter, &msg, 1);
0204 
0205     return ret >= 0 ? 0 : ret;
0206 }
0207 
0208 static int __mt9t112_reg_mask_set(const struct i2c_client *client,
0209                   u16  command, u16  mask, u16  set)
0210 {
0211     int val = __mt9t112_reg_read(client, command);
0212 
0213     if (val < 0)
0214         return val;
0215 
0216     val &= ~mask;
0217     val |= set & mask;
0218 
0219     return __mt9t112_reg_write(client, command, val);
0220 }
0221 
0222 /* mcu access */
0223 static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
0224 {
0225     int ret;
0226 
0227     ret = __mt9t112_reg_write(client, 0x098E, command);
0228     if (ret < 0)
0229         return ret;
0230 
0231     return __mt9t112_reg_read(client, 0x0990);
0232 }
0233 
0234 static int __mt9t112_mcu_write(const struct i2c_client *client,
0235                    u16 command, u16 data)
0236 {
0237     int ret;
0238 
0239     ret = __mt9t112_reg_write(client, 0x098E, command);
0240     if (ret < 0)
0241         return ret;
0242 
0243     return __mt9t112_reg_write(client, 0x0990, data);
0244 }
0245 
0246 static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
0247                   u16  command, u16  mask, u16  set)
0248 {
0249     int val = __mt9t112_mcu_read(client, command);
0250 
0251     if (val < 0)
0252         return val;
0253 
0254     val &= ~mask;
0255     val |= set & mask;
0256 
0257     return __mt9t112_mcu_write(client, command, val);
0258 }
0259 
0260 static int mt9t112_reset(const struct i2c_client *client)
0261 {
0262     int ret;
0263 
0264     mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
0265     usleep_range(1000, 5000);
0266     mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
0267 
0268     return ret;
0269 }
0270 
0271 #ifndef EXT_CLOCK
0272 #define CLOCK_INFO(a, b)
0273 #else
0274 #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
0275 static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
0276 {
0277     int m, n, p1, p2, p3, p4, p5, p6, p7;
0278     u32 vco, clk;
0279     char *enable;
0280 
0281     ext /= 1000; /* kbyte order */
0282 
0283     mt9t112_reg_read(n, client, 0x0012);
0284     p1 = n & 0x000f;
0285     n = n >> 4;
0286     p2 = n & 0x000f;
0287     n = n >> 4;
0288     p3 = n & 0x000f;
0289 
0290     mt9t112_reg_read(n, client, 0x002a);
0291     p4 = n & 0x000f;
0292     n = n >> 4;
0293     p5 = n & 0x000f;
0294     n = n >> 4;
0295     p6 = n & 0x000f;
0296 
0297     mt9t112_reg_read(n, client, 0x002c);
0298     p7 = n & 0x000f;
0299 
0300     mt9t112_reg_read(n, client, 0x0010);
0301     m = n & 0x00ff;
0302     n = (n >> 8) & 0x003f;
0303 
0304     enable = ((ext < 6000) || (ext > 54000)) ? "X" : "";
0305     dev_dbg(&client->dev, "EXTCLK          : %10u K %s\n", ext, enable);
0306 
0307     vco = 2 * m * ext / (n + 1);
0308     enable = ((vco < 384000) || (vco > 768000)) ? "X" : "";
0309     dev_dbg(&client->dev, "VCO             : %10u K %s\n", vco, enable);
0310 
0311     clk = vco / (p1 + 1) / (p2 + 1);
0312     enable = (clk > 96000) ? "X" : "";
0313     dev_dbg(&client->dev, "PIXCLK          : %10u K %s\n", clk, enable);
0314 
0315     clk = vco / (p3 + 1);
0316     enable = (clk > 768000) ? "X" : "";
0317     dev_dbg(&client->dev, "MIPICLK         : %10u K %s\n", clk, enable);
0318 
0319     clk = vco / (p6 + 1);
0320     enable = (clk > 96000) ? "X" : "";
0321     dev_dbg(&client->dev, "MCU CLK         : %10u K %s\n", clk, enable);
0322 
0323     clk = vco / (p5 + 1);
0324     enable = (clk > 54000) ? "X" : "";
0325     dev_dbg(&client->dev, "SOC CLK         : %10u K %s\n", clk, enable);
0326 
0327     clk = vco / (p4 + 1);
0328     enable = (clk > 70000) ? "X" : "";
0329     dev_dbg(&client->dev, "Sensor CLK      : %10u K %s\n", clk, enable);
0330 
0331     clk = vco / (p7 + 1);
0332     dev_dbg(&client->dev, "External sensor : %10u K\n", clk);
0333 
0334     clk = ext / (n + 1);
0335     enable = ((clk < 2000) || (clk > 24000)) ? "X" : "";
0336     dev_dbg(&client->dev, "PFD             : %10u K %s\n", clk, enable);
0337 
0338     return 0;
0339 }
0340 #endif
0341 
0342 static int mt9t112_set_a_frame_size(const struct i2c_client *client,
0343                     u16 width, u16 height)
0344 {
0345     int ret;
0346     u16 wstart = (MAX_WIDTH - width) / 2;
0347     u16 hstart = (MAX_HEIGHT - height) / 2;
0348 
0349     /* (Context A) Image Width/Height. */
0350     mt9t112_mcu_write(ret, client, VAR(26, 0), width);
0351     mt9t112_mcu_write(ret, client, VAR(26, 2), height);
0352 
0353     /* (Context A) Output Width/Height. */
0354     mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
0355     mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
0356 
0357     /* (Context A) Start Row/Column. */
0358     mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
0359     mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
0360 
0361     /* (Context A) End Row/Column. */
0362     mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
0363     mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width  + wstart);
0364 
0365     mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
0366 
0367     return ret;
0368 }
0369 
0370 static int mt9t112_set_pll_dividers(const struct i2c_client *client,
0371                     u8 m, u8 n, u8 p1, u8 p2, u8 p3, u8 p4,
0372                     u8 p5, u8 p6, u8 p7)
0373 {
0374     int ret;
0375     u16 val;
0376 
0377     /* N/M */
0378     val = (n << 8) | (m << 0);
0379     mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
0380 
0381     /* P1/P2/P3 */
0382     val = ((p3 & 0x0F) << 8) | ((p2 & 0x0F) << 4) | ((p1 & 0x0F) << 0);
0383     mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
0384 
0385     /* P4/P5/P6 */
0386     val = (0x7 << 12) | ((p6 & 0x0F) <<  8) | ((p5 & 0x0F) <<  4) |
0387           ((p4 & 0x0F) <<  0);
0388     mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
0389 
0390     /* P7 */
0391     val = (0x1 << 12) | ((p7 & 0x0F) <<  0);
0392     mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
0393 
0394     return ret;
0395 }
0396 
0397 static int mt9t112_init_pll(const struct i2c_client *client)
0398 {
0399     struct mt9t112_priv *priv = to_mt9t112(client);
0400     int data, i, ret;
0401 
0402     mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
0403 
0404     /* PLL control: BYPASS PLL = 8517. */
0405     mt9t112_reg_write(ret, client, 0x0014, 0x2145);
0406 
0407     /* Replace these registers when new timing parameters are generated. */
0408     mt9t112_set_pll_dividers(client,
0409                  priv->info->divider.m, priv->info->divider.n,
0410                  priv->info->divider.p1, priv->info->divider.p2,
0411                  priv->info->divider.p3, priv->info->divider.p4,
0412                  priv->info->divider.p5, priv->info->divider.p6,
0413                  priv->info->divider.p7);
0414 
0415     /*
0416      * TEST_BYPASS  on
0417      * PLL_ENABLE   on
0418      * SEL_LOCK_DET on
0419      * TEST_BYPASS  off
0420      */
0421     mt9t112_reg_write(ret, client, 0x0014, 0x2525);
0422     mt9t112_reg_write(ret, client, 0x0014, 0x2527);
0423     mt9t112_reg_write(ret, client, 0x0014, 0x3427);
0424     mt9t112_reg_write(ret, client, 0x0014, 0x3027);
0425 
0426     mdelay(10);
0427 
0428     /*
0429      * PLL_BYPASS off
0430      * Reference clock count
0431      * I2C Master Clock Divider
0432      */
0433     mt9t112_reg_write(ret, client, 0x0014, 0x3046);
0434     /* JPEG initialization workaround */
0435     mt9t112_reg_write(ret, client, 0x0016, 0x0400);
0436     mt9t112_reg_write(ret, client, 0x0022, 0x0190);
0437     mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
0438 
0439     /* External sensor clock is PLL bypass. */
0440     mt9t112_reg_write(ret, client, 0x002E, 0x0500);
0441 
0442     mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
0443     mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
0444 
0445     /* MCU disabled. */
0446     mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
0447 
0448     /* Out of standby. */
0449     mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
0450 
0451     mdelay(50);
0452 
0453     /*
0454      * Standby Workaround
0455      * Disable Secondary I2C Pads
0456      */
0457     mt9t112_reg_write(ret, client, 0x0614, 0x0001);
0458     mdelay(1);
0459     mt9t112_reg_write(ret, client, 0x0614, 0x0001);
0460     mdelay(1);
0461     mt9t112_reg_write(ret, client, 0x0614, 0x0001);
0462     mdelay(1);
0463     mt9t112_reg_write(ret, client, 0x0614, 0x0001);
0464     mdelay(1);
0465     mt9t112_reg_write(ret, client, 0x0614, 0x0001);
0466     mdelay(1);
0467     mt9t112_reg_write(ret, client, 0x0614, 0x0001);
0468     mdelay(1);
0469 
0470     /* Poll to verify out of standby. Must Poll this bit. */
0471     for (i = 0; i < 100; i++) {
0472         mt9t112_reg_read(data, client, 0x0018);
0473         if (!(data & 0x4000))
0474             break;
0475 
0476         mdelay(10);
0477     }
0478 
0479     return ret;
0480 }
0481 
0482 static int mt9t112_init_setting(const struct i2c_client *client)
0483 {
0484     int ret;
0485 
0486     /* Adaptive Output Clock (A) */
0487     mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
0488 
0489     /* Read Mode (A) */
0490     mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
0491 
0492     /* Fine Correction (A) */
0493     mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
0494 
0495     /* Fine IT Min (A) */
0496     mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
0497 
0498     /* Fine IT Max Margin (A) */
0499     mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
0500 
0501     /* Base Frame Lines (A) */
0502     mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
0503 
0504     /* Min Line Length (A) */
0505     mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
0506 
0507     /* Line Length (A) */
0508     mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
0509 
0510     /* Adaptive Output Clock (B) */
0511     mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
0512 
0513     /* Row Start (B) */
0514     mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
0515 
0516     /* Column Start (B) */
0517     mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
0518 
0519     /* Row End (B) */
0520     mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
0521 
0522     /* Column End (B) */
0523     mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
0524 
0525     /* Fine Correction (B) */
0526     mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
0527 
0528     /* Fine IT Min (B) */
0529     mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
0530 
0531     /* Fine IT Max Margin (B) */
0532     mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
0533 
0534     /* Base Frame Lines (B) */
0535     mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
0536 
0537     /* Min Line Length (B) */
0538     mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
0539 
0540     /* Line Length (B) */
0541     mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
0542 
0543     /*
0544      * Flicker Detection registers.
0545      * This section should be replaced whenever new timing file is
0546      * generated. All the following registers need to be replaced.
0547      * Following registers are generated from Register Wizard but user can
0548      * modify them. For detail see auto flicker detection tuning.
0549      */
0550 
0551     /* FD_FDPERIOD_SELECT */
0552     mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
0553 
0554     /* PRI_B_CONFIG_FD_ALGO_RUN */
0555     mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
0556 
0557     /* PRI_A_CONFIG_FD_ALGO_RUN */
0558     mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
0559 
0560     /*
0561      * AFD range detection tuning registers.
0562      */
0563 
0564     /* Search_f1_50 */
0565     mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
0566 
0567     /* Search_f2_50 */
0568     mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
0569 
0570     /* Search_f1_60 */
0571     mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
0572 
0573     /* Search_f2_60 */
0574     mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
0575 
0576     /* Period_50Hz (A) */
0577     mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
0578 
0579     /* Secret register by Aptina. */
0580     /* Period_50Hz (A MSB) */
0581     mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
0582 
0583     /* Period_60Hz (A) */
0584     mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
0585 
0586     /* Secret register by Aptina. */
0587     /* Period_60Hz (A MSB) */
0588     mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
0589 
0590     /* Period_50Hz (B) */
0591     mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
0592 
0593     /* Secret register by Aptina. */
0594     /* Period_50Hz (B) MSB */
0595     mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
0596 
0597     /* Period_60Hz (B) */
0598     mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
0599 
0600     /* Secret register by Aptina. */
0601     /* Period_60Hz (B) MSB */
0602     mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
0603 
0604     /* FD Mode */
0605     mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
0606 
0607     /* Stat_min */
0608     mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
0609 
0610     /* Stat_max */
0611     mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
0612 
0613     /* Min_amplitude */
0614     mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
0615 
0616     /* RX FIFO Watermark (A) */
0617     mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
0618 
0619     /* RX FIFO Watermark (B) */
0620     mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
0621 
0622     /* MCLK: 16MHz
0623      * PCLK: 73MHz
0624      * CorePixCLK: 36.5 MHz
0625      */
0626     mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
0627     mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
0628     mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
0629     mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
0630 
0631     mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
0632     mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
0633     mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
0634     mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
0635 
0636     return ret;
0637 }
0638 
0639 static int mt9t112_auto_focus_setting(const struct i2c_client *client)
0640 {
0641     int ret;
0642 
0643     mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
0644     mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
0645     mt9t112_mcu_write(ret, client, VAR8(1, 0),  0x06);
0646 
0647     mt9t112_reg_write(ret, client, 0x0614, 0x0000);
0648 
0649     mt9t112_mcu_write(ret, client, VAR8(1, 0),  0x05);
0650     mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
0651     mt9t112_mcu_write(ret, client, VAR(12, 3),  0x0002);
0652     mt9t112_mcu_write(ret, client, VAR(17, 3),  0x8001);
0653     mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
0654     mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
0655     mt9t112_mcu_write(ret, client, VAR8(17, 33),    0x18);
0656     mt9t112_mcu_write(ret, client, VAR8(1, 0),  0x05);
0657 
0658     return ret;
0659 }
0660 
0661 static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
0662 {
0663     int ret;
0664 
0665     mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
0666 
0667     return ret;
0668 }
0669 
0670 static int mt9t112_init_camera(const struct i2c_client *client)
0671 {
0672     int ret;
0673 
0674     ECHECKER(ret, mt9t112_reset(client));
0675     ECHECKER(ret, mt9t112_init_pll(client));
0676     ECHECKER(ret, mt9t112_init_setting(client));
0677     ECHECKER(ret, mt9t112_auto_focus_setting(client));
0678 
0679     mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
0680 
0681     /* Analog setting B.*/
0682     mt9t112_reg_write(ret, client, 0x3084, 0x2409);
0683     mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
0684     mt9t112_reg_write(ret, client, 0x3094, 0x4949);
0685     mt9t112_reg_write(ret, client, 0x3096, 0x4950);
0686 
0687     /*
0688      * Disable adaptive clock.
0689      * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
0690      * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
0691      */
0692     mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
0693     mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
0694 
0695     /*
0696      * Configure Status in Status_before_length Format and enable header.
0697      * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
0698      */
0699     mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
0700 
0701     /*
0702      * Enable JPEG in context B.
0703      * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
0704      */
0705     mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
0706 
0707     /* Disable Dac_TXLO. */
0708     mt9t112_reg_write(ret, client, 0x316C, 0x350F);
0709 
0710     /* Set max slew rates. */
0711     mt9t112_reg_write(ret, client, 0x1E, 0x777);
0712 
0713     return ret;
0714 }
0715 
0716 /************************************************************************
0717  *          v4l2_subdev_core_ops
0718  ***********************************************************************/
0719 
0720 #ifdef CONFIG_VIDEO_ADV_DEBUG
0721 static int mt9t112_g_register(struct v4l2_subdev *sd,
0722                   struct v4l2_dbg_register *reg)
0723 {
0724     struct i2c_client *client = v4l2_get_subdevdata(sd);
0725     int                ret;
0726 
0727     reg->size = 2;
0728     mt9t112_reg_read(ret, client, reg->reg);
0729 
0730     reg->val = (__u64)ret;
0731 
0732     return 0;
0733 }
0734 
0735 static int mt9t112_s_register(struct v4l2_subdev *sd,
0736                   const struct v4l2_dbg_register *reg)
0737 {
0738     struct i2c_client *client = v4l2_get_subdevdata(sd);
0739     int ret;
0740 
0741     mt9t112_reg_write(ret, client, reg->reg, reg->val);
0742 
0743     return ret;
0744 }
0745 #endif
0746 
0747 static int mt9t112_power_on(struct mt9t112_priv *priv)
0748 {
0749     int ret;
0750 
0751     ret = clk_prepare_enable(priv->clk);
0752     if (ret)
0753         return ret;
0754 
0755     if (priv->standby_gpio) {
0756         gpiod_set_value(priv->standby_gpio, 0);
0757         msleep(100);
0758     }
0759 
0760     return 0;
0761 }
0762 
0763 static int mt9t112_power_off(struct mt9t112_priv *priv)
0764 {
0765     clk_disable_unprepare(priv->clk);
0766     if (priv->standby_gpio) {
0767         gpiod_set_value(priv->standby_gpio, 1);
0768         msleep(100);
0769     }
0770 
0771     return 0;
0772 }
0773 
0774 static int mt9t112_s_power(struct v4l2_subdev *sd, int on)
0775 {
0776     struct i2c_client *client = v4l2_get_subdevdata(sd);
0777     struct mt9t112_priv *priv = to_mt9t112(client);
0778 
0779     return on ? mt9t112_power_on(priv) :
0780             mt9t112_power_off(priv);
0781 }
0782 
0783 static const struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
0784 #ifdef CONFIG_VIDEO_ADV_DEBUG
0785     .g_register = mt9t112_g_register,
0786     .s_register = mt9t112_s_register,
0787 #endif
0788     .s_power    = mt9t112_s_power,
0789 };
0790 
0791 /************************************************************************
0792  *          v4l2_subdev_video_ops
0793  **********************************************************************/
0794 static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
0795 {
0796     struct i2c_client *client = v4l2_get_subdevdata(sd);
0797     struct mt9t112_priv *priv = to_mt9t112(client);
0798     int ret = 0;
0799 
0800     if (!enable) {
0801         /* FIXME
0802          *
0803          * If user selected large output size, and used it long time,
0804          * mt9t112 camera will be very warm.
0805          *
0806          * But current driver can not stop mt9t112 camera.
0807          * So, set small size here to solve this problem.
0808          */
0809         mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
0810         return ret;
0811     }
0812 
0813     if (!priv->init_done) {
0814         u16 param = MT9T112_FLAG_PCLK_RISING_EDGE & priv->info->flags ?
0815                 0x0001 : 0x0000;
0816 
0817         ECHECKER(ret, mt9t112_init_camera(client));
0818 
0819         /* Invert PCLK (Data sampled on falling edge of pixclk). */
0820         mt9t112_reg_write(ret, client, 0x3C20, param);
0821 
0822         mdelay(5);
0823 
0824         priv->init_done = true;
0825     }
0826 
0827     mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
0828     mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
0829     mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
0830 
0831     mt9t112_set_a_frame_size(client, priv->frame.width, priv->frame.height);
0832 
0833     ECHECKER(ret, mt9t112_auto_focus_trigger(client));
0834 
0835     dev_dbg(&client->dev, "format : %d\n", priv->format->code);
0836     dev_dbg(&client->dev, "size   : %d x %d\n",
0837         priv->frame.width,
0838         priv->frame.height);
0839 
0840     CLOCK_INFO(client, EXT_CLOCK);
0841 
0842     return ret;
0843 }
0844 
0845 static int mt9t112_set_params(struct mt9t112_priv *priv,
0846                   const struct v4l2_rect *rect,
0847                   u32 code)
0848 {
0849     int i;
0850 
0851     /*
0852      * get color format
0853      */
0854     for (i = 0; i < priv->num_formats; i++)
0855         if (mt9t112_cfmts[i].code == code)
0856             break;
0857 
0858     if (i == priv->num_formats)
0859         return -EINVAL;
0860 
0861     priv->frame = *rect;
0862 
0863     /*
0864      * frame size check
0865      */
0866     v4l_bound_align_image(&priv->frame.width, 0, MAX_WIDTH, 0,
0867                   &priv->frame.height, 0, MAX_HEIGHT, 0, 0);
0868 
0869     priv->format = mt9t112_cfmts + i;
0870 
0871     return 0;
0872 }
0873 
0874 static int mt9t112_get_selection(struct v4l2_subdev *sd,
0875                  struct v4l2_subdev_state *sd_state,
0876                  struct v4l2_subdev_selection *sel)
0877 {
0878     struct i2c_client *client = v4l2_get_subdevdata(sd);
0879     struct mt9t112_priv *priv = to_mt9t112(client);
0880 
0881     if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
0882         return -EINVAL;
0883 
0884     switch (sel->target) {
0885     case V4L2_SEL_TGT_CROP_BOUNDS:
0886         sel->r.left = 0;
0887         sel->r.top = 0;
0888         sel->r.width = MAX_WIDTH;
0889         sel->r.height = MAX_HEIGHT;
0890         return 0;
0891     case V4L2_SEL_TGT_CROP:
0892         sel->r = priv->frame;
0893         return 0;
0894     default:
0895         return -EINVAL;
0896     }
0897 }
0898 
0899 static int mt9t112_set_selection(struct v4l2_subdev *sd,
0900                  struct v4l2_subdev_state *sd_state,
0901                  struct v4l2_subdev_selection *sel)
0902 {
0903     struct i2c_client *client = v4l2_get_subdevdata(sd);
0904     struct mt9t112_priv *priv = to_mt9t112(client);
0905     const struct v4l2_rect *rect = &sel->r;
0906 
0907     if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
0908         sel->target != V4L2_SEL_TGT_CROP)
0909         return -EINVAL;
0910 
0911     return mt9t112_set_params(priv, rect, priv->format->code);
0912 }
0913 
0914 static int mt9t112_get_fmt(struct v4l2_subdev *sd,
0915                struct v4l2_subdev_state *sd_state,
0916                struct v4l2_subdev_format *format)
0917 {
0918     struct v4l2_mbus_framefmt *mf = &format->format;
0919     struct i2c_client *client = v4l2_get_subdevdata(sd);
0920     struct mt9t112_priv *priv = to_mt9t112(client);
0921 
0922     if (format->pad)
0923         return -EINVAL;
0924 
0925     mf->width   = priv->frame.width;
0926     mf->height  = priv->frame.height;
0927     mf->colorspace  = priv->format->colorspace;
0928     mf->code    = priv->format->code;
0929     mf->field   = V4L2_FIELD_NONE;
0930 
0931     return 0;
0932 }
0933 
0934 static int mt9t112_s_fmt(struct v4l2_subdev *sd,
0935              struct v4l2_mbus_framefmt *mf)
0936 {
0937     struct i2c_client *client = v4l2_get_subdevdata(sd);
0938     struct mt9t112_priv *priv = to_mt9t112(client);
0939     struct v4l2_rect rect = {
0940         .width = mf->width,
0941         .height = mf->height,
0942         .left = priv->frame.left,
0943         .top = priv->frame.top,
0944     };
0945     int ret;
0946 
0947     ret = mt9t112_set_params(priv, &rect, mf->code);
0948 
0949     if (!ret)
0950         mf->colorspace = priv->format->colorspace;
0951 
0952     return ret;
0953 }
0954 
0955 static int mt9t112_set_fmt(struct v4l2_subdev *sd,
0956                struct v4l2_subdev_state *sd_state,
0957                struct v4l2_subdev_format *format)
0958 {
0959     struct i2c_client *client = v4l2_get_subdevdata(sd);
0960     struct v4l2_mbus_framefmt *mf = &format->format;
0961     struct mt9t112_priv *priv = to_mt9t112(client);
0962     int i;
0963 
0964     if (format->pad)
0965         return -EINVAL;
0966 
0967     for (i = 0; i < priv->num_formats; i++)
0968         if (mt9t112_cfmts[i].code == mf->code)
0969             break;
0970 
0971     if (i == priv->num_formats) {
0972         mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
0973         mf->colorspace = V4L2_COLORSPACE_JPEG;
0974     } else {
0975         mf->colorspace = mt9t112_cfmts[i].colorspace;
0976     }
0977 
0978     v4l_bound_align_image(&mf->width, 0, MAX_WIDTH, 0,
0979                   &mf->height, 0, MAX_HEIGHT, 0, 0);
0980 
0981     mf->field = V4L2_FIELD_NONE;
0982 
0983     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
0984         return mt9t112_s_fmt(sd, mf);
0985     sd_state->pads->try_fmt = *mf;
0986 
0987     return 0;
0988 }
0989 
0990 static int mt9t112_enum_mbus_code(struct v4l2_subdev *sd,
0991                   struct v4l2_subdev_state *sd_state,
0992                   struct v4l2_subdev_mbus_code_enum *code)
0993 {
0994     struct i2c_client *client = v4l2_get_subdevdata(sd);
0995     struct mt9t112_priv *priv = to_mt9t112(client);
0996 
0997     if (code->pad || code->index >= priv->num_formats)
0998         return -EINVAL;
0999 
1000     code->code = mt9t112_cfmts[code->index].code;
1001 
1002     return 0;
1003 }
1004 
1005 static const struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
1006     .s_stream   = mt9t112_s_stream,
1007 };
1008 
1009 static const struct v4l2_subdev_pad_ops mt9t112_subdev_pad_ops = {
1010     .enum_mbus_code = mt9t112_enum_mbus_code,
1011     .get_selection  = mt9t112_get_selection,
1012     .set_selection  = mt9t112_set_selection,
1013     .get_fmt    = mt9t112_get_fmt,
1014     .set_fmt    = mt9t112_set_fmt,
1015 };
1016 
1017 /************************************************************************
1018  *          i2c driver
1019  ***********************************************************************/
1020 static const struct v4l2_subdev_ops mt9t112_subdev_ops = {
1021     .core   = &mt9t112_subdev_core_ops,
1022     .video  = &mt9t112_subdev_video_ops,
1023     .pad    = &mt9t112_subdev_pad_ops,
1024 };
1025 
1026 static int mt9t112_camera_probe(struct i2c_client *client)
1027 {
1028     struct mt9t112_priv *priv = to_mt9t112(client);
1029     const char          *devname;
1030     int                  chipid;
1031     int          ret;
1032 
1033     ret = mt9t112_s_power(&priv->subdev, 1);
1034     if (ret < 0)
1035         return ret;
1036 
1037     /* Check and show chip ID. */
1038     mt9t112_reg_read(chipid, client, 0x0000);
1039 
1040     switch (chipid) {
1041     case 0x2680:
1042         devname = "mt9t111";
1043         priv->num_formats = 1;
1044         break;
1045     case 0x2682:
1046         devname = "mt9t112";
1047         priv->num_formats = ARRAY_SIZE(mt9t112_cfmts);
1048         break;
1049     default:
1050         dev_err(&client->dev, "Product ID error %04x\n", chipid);
1051         ret = -ENODEV;
1052         goto done;
1053     }
1054 
1055     dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
1056 
1057 done:
1058     mt9t112_s_power(&priv->subdev, 0);
1059 
1060     return ret;
1061 }
1062 
1063 static int mt9t112_probe(struct i2c_client *client,
1064              const struct i2c_device_id *did)
1065 {
1066     struct mt9t112_priv *priv;
1067     int ret;
1068 
1069     if (!client->dev.platform_data) {
1070         dev_err(&client->dev, "mt9t112: missing platform data!\n");
1071         return -EINVAL;
1072     }
1073 
1074     priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1075     if (!priv)
1076         return -ENOMEM;
1077 
1078     priv->info = client->dev.platform_data;
1079     priv->init_done = false;
1080 
1081     v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
1082 
1083     priv->clk = devm_clk_get(&client->dev, "extclk");
1084     if (PTR_ERR(priv->clk) == -ENOENT) {
1085         priv->clk = NULL;
1086     } else if (IS_ERR(priv->clk)) {
1087         dev_err(&client->dev, "Unable to get clock \"extclk\"\n");
1088         return PTR_ERR(priv->clk);
1089     }
1090 
1091     priv->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1092                              GPIOD_OUT_HIGH);
1093     if (IS_ERR(priv->standby_gpio)) {
1094         dev_err(&client->dev, "Unable to get gpio \"standby\"\n");
1095         return PTR_ERR(priv->standby_gpio);
1096     }
1097 
1098     ret = mt9t112_camera_probe(client);
1099     if (ret)
1100         return ret;
1101 
1102     return v4l2_async_register_subdev(&priv->subdev);
1103 }
1104 
1105 static int mt9t112_remove(struct i2c_client *client)
1106 {
1107     struct mt9t112_priv *priv = to_mt9t112(client);
1108 
1109     clk_disable_unprepare(priv->clk);
1110     v4l2_async_unregister_subdev(&priv->subdev);
1111 
1112     return 0;
1113 }
1114 
1115 static const struct i2c_device_id mt9t112_id[] = {
1116     { "mt9t112", 0 },
1117     { }
1118 };
1119 MODULE_DEVICE_TABLE(i2c, mt9t112_id);
1120 
1121 static struct i2c_driver mt9t112_i2c_driver = {
1122     .driver = {
1123         .name = "mt9t112",
1124     },
1125     .probe    = mt9t112_probe,
1126     .remove   = mt9t112_remove,
1127     .id_table = mt9t112_id,
1128 };
1129 
1130 module_i2c_driver(mt9t112_i2c_driver);
1131 
1132 MODULE_DESCRIPTION("V4L2 driver for MT9T111/MT9T112 camera sensor");
1133 MODULE_AUTHOR("Kuninori Morimoto");
1134 MODULE_LICENSE("GPL v2");
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