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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Maxim MAX9286 GMSL Deserializer Driver
0004  *
0005  * Copyright (C) 2017-2019 Jacopo Mondi
0006  * Copyright (C) 2017-2019 Kieran Bingham
0007  * Copyright (C) 2017-2019 Laurent Pinchart
0008  * Copyright (C) 2017-2019 Niklas Söderlund
0009  * Copyright (C) 2016 Renesas Electronics Corporation
0010  * Copyright (C) 2015 Cogent Embedded, Inc.
0011  */
0012 
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/fwnode.h>
0016 #include <linux/gpio/consumer.h>
0017 #include <linux/gpio/driver.h>
0018 #include <linux/gpio/machine.h>
0019 #include <linux/i2c.h>
0020 #include <linux/i2c-mux.h>
0021 #include <linux/module.h>
0022 #include <linux/mutex.h>
0023 #include <linux/of_graph.h>
0024 #include <linux/regulator/consumer.h>
0025 #include <linux/slab.h>
0026 
0027 #include <media/v4l2-async.h>
0028 #include <media/v4l2-ctrls.h>
0029 #include <media/v4l2-device.h>
0030 #include <media/v4l2-fwnode.h>
0031 #include <media/v4l2-subdev.h>
0032 
0033 /* Register 0x00 */
0034 #define MAX9286_MSTLINKSEL_AUTO     (7 << 5)
0035 #define MAX9286_MSTLINKSEL(n)       ((n) << 5)
0036 #define MAX9286_EN_VS_GEN       BIT(4)
0037 #define MAX9286_LINKEN(n)       (1 << (n))
0038 /* Register 0x01 */
0039 #define MAX9286_FSYNCMODE_ECU       (3 << 6)
0040 #define MAX9286_FSYNCMODE_EXT       (2 << 6)
0041 #define MAX9286_FSYNCMODE_INT_OUT   (1 << 6)
0042 #define MAX9286_FSYNCMODE_INT_HIZ   (0 << 6)
0043 #define MAX9286_GPIEN           BIT(5)
0044 #define MAX9286_ENLMO_RSTFSYNC      BIT(2)
0045 #define MAX9286_FSYNCMETH_AUTO      (2 << 0)
0046 #define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0)
0047 #define MAX9286_FSYNCMETH_MANUAL    (0 << 0)
0048 #define MAX9286_REG_FSYNC_PERIOD_L  0x06
0049 #define MAX9286_REG_FSYNC_PERIOD_M  0x07
0050 #define MAX9286_REG_FSYNC_PERIOD_H  0x08
0051 /* Register 0x0a */
0052 #define MAX9286_FWDCCEN(n)      (1 << ((n) + 4))
0053 #define MAX9286_REVCCEN(n)      (1 << (n))
0054 /* Register 0x0c */
0055 #define MAX9286_HVEN            BIT(7)
0056 #define MAX9286_EDC_6BIT_HAMMING    (2 << 5)
0057 #define MAX9286_EDC_6BIT_CRC        (1 << 5)
0058 #define MAX9286_EDC_1BIT_PARITY     (0 << 5)
0059 #define MAX9286_DESEL           BIT(4)
0060 #define MAX9286_INVVS           BIT(3)
0061 #define MAX9286_INVHS           BIT(2)
0062 #define MAX9286_HVSRC_D0        (2 << 0)
0063 #define MAX9286_HVSRC_D14       (1 << 0)
0064 #define MAX9286_HVSRC_D18       (0 << 0)
0065 /* Register 0x0f */
0066 #define MAX9286_0X0F_RESERVED       BIT(3)
0067 /* Register 0x12 */
0068 #define MAX9286_CSILANECNT(n)       (((n) - 1) << 6)
0069 #define MAX9286_CSIDBL          BIT(5)
0070 #define MAX9286_DBL         BIT(4)
0071 #define MAX9286_DATATYPE_USER_8BIT  (11 << 0)
0072 #define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0)
0073 #define MAX9286_DATATYPE_USER_24BIT (9 << 0)
0074 #define MAX9286_DATATYPE_RAW14      (8 << 0)
0075 #define MAX9286_DATATYPE_RAW11      (7 << 0)
0076 #define MAX9286_DATATYPE_RAW10      (6 << 0)
0077 #define MAX9286_DATATYPE_RAW8       (5 << 0)
0078 #define MAX9286_DATATYPE_YUV422_10BIT   (4 << 0)
0079 #define MAX9286_DATATYPE_YUV422_8BIT    (3 << 0)
0080 #define MAX9286_DATATYPE_RGB555     (2 << 0)
0081 #define MAX9286_DATATYPE_RGB565     (1 << 0)
0082 #define MAX9286_DATATYPE_RGB888     (0 << 0)
0083 /* Register 0x15 */
0084 #define MAX9286_VC(n)           ((n) << 5)
0085 #define MAX9286_VCTYPE          BIT(4)
0086 #define MAX9286_CSIOUTEN        BIT(3)
0087 #define MAX9286_0X15_RESV       (3 << 0)
0088 /* Register 0x1b */
0089 #define MAX9286_SWITCHIN(n)     (1 << ((n) + 4))
0090 #define MAX9286_ENEQ(n)         (1 << (n))
0091 /* Register 0x27 */
0092 #define MAX9286_LOCKED          BIT(7)
0093 /* Register 0x31 */
0094 #define MAX9286_FSYNC_LOCKED        BIT(6)
0095 /* Register 0x34 */
0096 #define MAX9286_I2CLOCACK       BIT(7)
0097 #define MAX9286_I2CSLVSH_1046NS_469NS   (3 << 5)
0098 #define MAX9286_I2CSLVSH_938NS_352NS    (2 << 5)
0099 #define MAX9286_I2CSLVSH_469NS_234NS    (1 << 5)
0100 #define MAX9286_I2CSLVSH_352NS_117NS    (0 << 5)
0101 #define MAX9286_I2CMSTBT_837KBPS    (7 << 2)
0102 #define MAX9286_I2CMSTBT_533KBPS    (6 << 2)
0103 #define MAX9286_I2CMSTBT_339KBPS    (5 << 2)
0104 #define MAX9286_I2CMSTBT_173KBPS    (4 << 2)
0105 #define MAX9286_I2CMSTBT_105KBPS    (3 << 2)
0106 #define MAX9286_I2CMSTBT_84KBPS     (2 << 2)
0107 #define MAX9286_I2CMSTBT_28KBPS     (1 << 2)
0108 #define MAX9286_I2CMSTBT_8KBPS      (0 << 2)
0109 #define MAX9286_I2CSLVTO_NONE       (3 << 0)
0110 #define MAX9286_I2CSLVTO_1024US     (2 << 0)
0111 #define MAX9286_I2CSLVTO_256US      (1 << 0)
0112 #define MAX9286_I2CSLVTO_64US       (0 << 0)
0113 /* Register 0x3b */
0114 #define MAX9286_REV_TRF(n)      ((n) << 4)
0115 #define MAX9286_REV_AMP(n)      ((((n) - 30) / 10) << 1) /* in mV */
0116 #define MAX9286_REV_AMP_X       BIT(0)
0117 #define MAX9286_REV_AMP_HIGH        170
0118 /* Register 0x3f */
0119 #define MAX9286_EN_REV_CFG      BIT(6)
0120 #define MAX9286_REV_FLEN(n)     ((n) - 20)
0121 /* Register 0x49 */
0122 #define MAX9286_VIDEO_DETECT_MASK   0x0f
0123 /* Register 0x69 */
0124 #define MAX9286_LFLTBMONMASKED      BIT(7)
0125 #define MAX9286_LOCKMONMASKED       BIT(6)
0126 #define MAX9286_AUTOCOMBACKEN       BIT(5)
0127 #define MAX9286_AUTOMASKEN      BIT(4)
0128 #define MAX9286_MASKLINK(n)     ((n) << 0)
0129 
0130 /*
0131  * The sink and source pads are created to match the OF graph port numbers so
0132  * that their indexes can be used interchangeably.
0133  */
0134 #define MAX9286_NUM_GMSL        4
0135 #define MAX9286_N_SINKS         4
0136 #define MAX9286_N_PADS          5
0137 #define MAX9286_SRC_PAD         4
0138 
0139 struct max9286_source {
0140     struct v4l2_subdev *sd;
0141     struct fwnode_handle *fwnode;
0142 };
0143 
0144 struct max9286_asd {
0145     struct v4l2_async_subdev base;
0146     struct max9286_source *source;
0147 };
0148 
0149 static inline struct max9286_asd *to_max9286_asd(struct v4l2_async_subdev *asd)
0150 {
0151     return container_of(asd, struct max9286_asd, base);
0152 }
0153 
0154 struct max9286_priv {
0155     struct i2c_client *client;
0156     struct gpio_desc *gpiod_pwdn;
0157     struct v4l2_subdev sd;
0158     struct media_pad pads[MAX9286_N_PADS];
0159     struct regulator *regulator;
0160 
0161     struct gpio_chip gpio;
0162     u8 gpio_state;
0163 
0164     struct i2c_mux_core *mux;
0165     unsigned int mux_channel;
0166     bool mux_open;
0167 
0168     /* The initial reverse control channel amplitude. */
0169     u32 init_rev_chan_mv;
0170     u32 rev_chan_mv;
0171 
0172     u32 gpio_poc[2];
0173 
0174     struct v4l2_ctrl_handler ctrls;
0175     struct v4l2_ctrl *pixelrate;
0176 
0177     struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS];
0178 
0179     /* Protects controls and fmt structures */
0180     struct mutex mutex;
0181 
0182     unsigned int nsources;
0183     unsigned int source_mask;
0184     unsigned int route_mask;
0185     unsigned int bound_sources;
0186     unsigned int csi2_data_lanes;
0187     struct max9286_source sources[MAX9286_NUM_GMSL];
0188     struct v4l2_async_notifier notifier;
0189 };
0190 
0191 static struct max9286_source *next_source(struct max9286_priv *priv,
0192                       struct max9286_source *source)
0193 {
0194     if (!source)
0195         source = &priv->sources[0];
0196     else
0197         source++;
0198 
0199     for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) {
0200         if (source->fwnode)
0201             return source;
0202     }
0203 
0204     return NULL;
0205 }
0206 
0207 #define for_each_source(priv, source) \
0208     for ((source) = NULL; ((source) = next_source((priv), (source))); )
0209 
0210 #define to_index(priv, source) ((source) - &(priv)->sources[0])
0211 
0212 static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd)
0213 {
0214     return container_of(sd, struct max9286_priv, sd);
0215 }
0216 
0217 /* -----------------------------------------------------------------------------
0218  * I2C IO
0219  */
0220 
0221 static int max9286_read(struct max9286_priv *priv, u8 reg)
0222 {
0223     int ret;
0224 
0225     ret = i2c_smbus_read_byte_data(priv->client, reg);
0226     if (ret < 0)
0227         dev_err(&priv->client->dev,
0228             "%s: register 0x%02x read failed (%d)\n",
0229             __func__, reg, ret);
0230 
0231     return ret;
0232 }
0233 
0234 static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val)
0235 {
0236     int ret;
0237 
0238     ret = i2c_smbus_write_byte_data(priv->client, reg, val);
0239     if (ret < 0)
0240         dev_err(&priv->client->dev,
0241             "%s: register 0x%02x write failed (%d)\n",
0242             __func__, reg, ret);
0243 
0244     return ret;
0245 }
0246 
0247 /* -----------------------------------------------------------------------------
0248  * I2C Multiplexer
0249  */
0250 
0251 static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf)
0252 {
0253     max9286_write(priv, 0x0a, conf);
0254 
0255     /*
0256      * We must sleep after any change to the forward or reverse channel
0257      * configuration.
0258      */
0259     usleep_range(3000, 5000);
0260 }
0261 
0262 static void max9286_i2c_mux_open(struct max9286_priv *priv)
0263 {
0264     /* Open all channels on the MAX9286 */
0265     max9286_i2c_mux_configure(priv, 0xff);
0266 
0267     priv->mux_open = true;
0268 }
0269 
0270 static void max9286_i2c_mux_close(struct max9286_priv *priv)
0271 {
0272     /*
0273      * Ensure that both the forward and reverse channel are disabled on the
0274      * mux, and that the channel ID is invalidated to ensure we reconfigure
0275      * on the next max9286_i2c_mux_select() call.
0276      */
0277     max9286_i2c_mux_configure(priv, 0x00);
0278 
0279     priv->mux_open = false;
0280     priv->mux_channel = -1;
0281 }
0282 
0283 static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)
0284 {
0285     struct max9286_priv *priv = i2c_mux_priv(muxc);
0286 
0287     /* Channel select is disabled when configured in the opened state. */
0288     if (priv->mux_open)
0289         return 0;
0290 
0291     if (priv->mux_channel == chan)
0292         return 0;
0293 
0294     priv->mux_channel = chan;
0295 
0296     max9286_i2c_mux_configure(priv, MAX9286_FWDCCEN(chan) |
0297                     MAX9286_REVCCEN(chan));
0298 
0299     return 0;
0300 }
0301 
0302 static int max9286_i2c_mux_init(struct max9286_priv *priv)
0303 {
0304     struct max9286_source *source;
0305     int ret;
0306 
0307     if (!i2c_check_functionality(priv->client->adapter,
0308                      I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
0309         return -ENODEV;
0310 
0311     priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
0312                   priv->nsources, 0, I2C_MUX_LOCKED,
0313                   max9286_i2c_mux_select, NULL);
0314     if (!priv->mux)
0315         return -ENOMEM;
0316 
0317     priv->mux->priv = priv;
0318 
0319     for_each_source(priv, source) {
0320         unsigned int index = to_index(priv, source);
0321 
0322         ret = i2c_mux_add_adapter(priv->mux, 0, index, 0);
0323         if (ret < 0)
0324             goto error;
0325     }
0326 
0327     return 0;
0328 
0329 error:
0330     i2c_mux_del_adapters(priv->mux);
0331     return ret;
0332 }
0333 
0334 static void max9286_configure_i2c(struct max9286_priv *priv, bool localack)
0335 {
0336     u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US |
0337             MAX9286_I2CMSTBT_105KBPS;
0338 
0339     if (localack)
0340         config |= MAX9286_I2CLOCACK;
0341 
0342     max9286_write(priv, 0x34, config);
0343     usleep_range(3000, 5000);
0344 }
0345 
0346 static void max9286_reverse_channel_setup(struct max9286_priv *priv,
0347                       unsigned int chan_amplitude)
0348 {
0349     u8 chan_config;
0350 
0351     if (priv->rev_chan_mv == chan_amplitude)
0352         return;
0353 
0354     priv->rev_chan_mv = chan_amplitude;
0355 
0356     /* Reverse channel transmission time: default to 1. */
0357     chan_config = MAX9286_REV_TRF(1);
0358 
0359     /*
0360      * Reverse channel setup.
0361      *
0362      * - Enable custom reverse channel configuration (through register 0x3f)
0363      *   and set the first pulse length to 35 clock cycles.
0364      * - Adjust reverse channel amplitude: values > 130 are programmed
0365      *   using the additional +100mV REV_AMP_X boost flag
0366      */
0367     max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35));
0368 
0369     if (chan_amplitude > 100) {
0370         /* It is not possible to express values (100 < x < 130) */
0371         chan_amplitude = max(30U, chan_amplitude - 100);
0372         chan_config |= MAX9286_REV_AMP_X;
0373     }
0374     max9286_write(priv, 0x3b, chan_config | MAX9286_REV_AMP(chan_amplitude));
0375     usleep_range(2000, 2500);
0376 }
0377 
0378 /*
0379  * max9286_check_video_links() - Make sure video links are detected and locked
0380  *
0381  * Performs safety checks on video link status. Make sure they are detected
0382  * and all enabled links are locked.
0383  *
0384  * Returns 0 for success, -EIO for errors.
0385  */
0386 static int max9286_check_video_links(struct max9286_priv *priv)
0387 {
0388     unsigned int i;
0389     int ret;
0390 
0391     /*
0392      * Make sure valid video links are detected.
0393      * The delay is not characterized in de-serializer manual, wait up
0394      * to 5 ms.
0395      */
0396     for (i = 0; i < 10; i++) {
0397         ret = max9286_read(priv, 0x49);
0398         if (ret < 0)
0399             return -EIO;
0400 
0401         if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask)
0402             break;
0403 
0404         usleep_range(350, 500);
0405     }
0406 
0407     if (i == 10) {
0408         dev_err(&priv->client->dev,
0409             "Unable to detect video links: 0x%02x\n", ret);
0410         return -EIO;
0411     }
0412 
0413     /* Make sure all enabled links are locked (4ms max). */
0414     for (i = 0; i < 10; i++) {
0415         ret = max9286_read(priv, 0x27);
0416         if (ret < 0)
0417             return -EIO;
0418 
0419         if (ret & MAX9286_LOCKED)
0420             break;
0421 
0422         usleep_range(350, 450);
0423     }
0424 
0425     if (i == 10) {
0426         dev_err(&priv->client->dev, "Not all enabled links locked\n");
0427         return -EIO;
0428     }
0429 
0430     return 0;
0431 }
0432 
0433 /*
0434  * max9286_check_config_link() - Detect and wait for configuration links
0435  *
0436  * Determine if the configuration channel is up and settled for a link.
0437  *
0438  * Returns 0 for success, -EIO for errors.
0439  */
0440 static int max9286_check_config_link(struct max9286_priv *priv,
0441                      unsigned int source_mask)
0442 {
0443     unsigned int conflink_mask = (source_mask & 0x0f) << 4;
0444     unsigned int i;
0445     int ret;
0446 
0447     /*
0448      * Make sure requested configuration links are detected.
0449      * The delay is not characterized in the chip manual: wait up
0450      * to 5 milliseconds.
0451      */
0452     for (i = 0; i < 10; i++) {
0453         ret = max9286_read(priv, 0x49);
0454         if (ret < 0)
0455             return -EIO;
0456 
0457         ret &= 0xf0;
0458         if (ret == conflink_mask)
0459             break;
0460 
0461         usleep_range(350, 500);
0462     }
0463 
0464     if (ret != conflink_mask) {
0465         dev_err(&priv->client->dev,
0466             "Unable to detect configuration links: 0x%02x expected 0x%02x\n",
0467             ret, conflink_mask);
0468         return -EIO;
0469     }
0470 
0471     dev_info(&priv->client->dev,
0472          "Successfully detected configuration links after %u loops: 0x%02x\n",
0473          i, conflink_mask);
0474 
0475     return 0;
0476 }
0477 
0478 /* -----------------------------------------------------------------------------
0479  * V4L2 Subdev
0480  */
0481 
0482 static int max9286_set_pixelrate(struct max9286_priv *priv)
0483 {
0484     struct max9286_source *source = NULL;
0485     u64 pixelrate = 0;
0486 
0487     for_each_source(priv, source) {
0488         struct v4l2_ctrl *ctrl;
0489         u64 source_rate = 0;
0490 
0491         /* Pixel rate is mandatory to be reported by sources. */
0492         ctrl = v4l2_ctrl_find(source->sd->ctrl_handler,
0493                       V4L2_CID_PIXEL_RATE);
0494         if (!ctrl) {
0495             pixelrate = 0;
0496             break;
0497         }
0498 
0499         /* All source must report the same pixel rate. */
0500         source_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
0501         if (!pixelrate) {
0502             pixelrate = source_rate;
0503         } else if (pixelrate != source_rate) {
0504             dev_err(&priv->client->dev,
0505                 "Unable to calculate pixel rate\n");
0506             return -EINVAL;
0507         }
0508     }
0509 
0510     if (!pixelrate) {
0511         dev_err(&priv->client->dev,
0512             "No pixel rate control available in sources\n");
0513         return -EINVAL;
0514     }
0515 
0516     /*
0517      * The CSI-2 transmitter pixel rate is the single source rate multiplied
0518      * by the number of available sources.
0519      */
0520     return v4l2_ctrl_s_ctrl_int64(priv->pixelrate,
0521                       pixelrate * priv->nsources);
0522 }
0523 
0524 static int max9286_notify_bound(struct v4l2_async_notifier *notifier,
0525                 struct v4l2_subdev *subdev,
0526                 struct v4l2_async_subdev *asd)
0527 {
0528     struct max9286_priv *priv = sd_to_max9286(notifier->sd);
0529     struct max9286_source *source = to_max9286_asd(asd)->source;
0530     unsigned int index = to_index(priv, source);
0531     unsigned int src_pad;
0532     int ret;
0533 
0534     ret = media_entity_get_fwnode_pad(&subdev->entity,
0535                       source->fwnode,
0536                       MEDIA_PAD_FL_SOURCE);
0537     if (ret < 0) {
0538         dev_err(&priv->client->dev,
0539             "Failed to find pad for %s\n", subdev->name);
0540         return ret;
0541     }
0542 
0543     priv->bound_sources |= BIT(index);
0544     source->sd = subdev;
0545     src_pad = ret;
0546 
0547     ret = media_create_pad_link(&source->sd->entity, src_pad,
0548                     &priv->sd.entity, index,
0549                     MEDIA_LNK_FL_ENABLED |
0550                     MEDIA_LNK_FL_IMMUTABLE);
0551     if (ret) {
0552         dev_err(&priv->client->dev,
0553             "Unable to link %s:%u -> %s:%u\n",
0554             source->sd->name, src_pad, priv->sd.name, index);
0555         return ret;
0556     }
0557 
0558     dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n",
0559         subdev->name, src_pad, index);
0560 
0561     /*
0562      * As we register a subdev notifiers we won't get a .complete() callback
0563      * here, so we have to use bound_sources to identify when all remote
0564      * serializers have probed.
0565      */
0566     if (priv->bound_sources != priv->source_mask)
0567         return 0;
0568 
0569     /*
0570      * All enabled sources have probed and enabled their reverse control
0571      * channels:
0572      *
0573      * - Increase the reverse channel amplitude to compensate for the
0574      *   remote ends high threshold
0575      * - Verify all configuration links are properly detected
0576      * - Disable auto-ack as communication on the control channel are now
0577      *   stable.
0578      */
0579     max9286_reverse_channel_setup(priv, MAX9286_REV_AMP_HIGH);
0580     max9286_check_config_link(priv, priv->source_mask);
0581     max9286_configure_i2c(priv, false);
0582 
0583     return max9286_set_pixelrate(priv);
0584 }
0585 
0586 static void max9286_notify_unbind(struct v4l2_async_notifier *notifier,
0587                   struct v4l2_subdev *subdev,
0588                   struct v4l2_async_subdev *asd)
0589 {
0590     struct max9286_priv *priv = sd_to_max9286(notifier->sd);
0591     struct max9286_source *source = to_max9286_asd(asd)->source;
0592     unsigned int index = to_index(priv, source);
0593 
0594     source->sd = NULL;
0595     priv->bound_sources &= ~BIT(index);
0596 }
0597 
0598 static const struct v4l2_async_notifier_operations max9286_notify_ops = {
0599     .bound = max9286_notify_bound,
0600     .unbind = max9286_notify_unbind,
0601 };
0602 
0603 static int max9286_v4l2_notifier_register(struct max9286_priv *priv)
0604 {
0605     struct device *dev = &priv->client->dev;
0606     struct max9286_source *source = NULL;
0607     int ret;
0608 
0609     if (!priv->nsources)
0610         return 0;
0611 
0612     v4l2_async_nf_init(&priv->notifier);
0613 
0614     for_each_source(priv, source) {
0615         unsigned int i = to_index(priv, source);
0616         struct max9286_asd *mas;
0617 
0618         mas = v4l2_async_nf_add_fwnode(&priv->notifier, source->fwnode,
0619                            struct max9286_asd);
0620         if (IS_ERR(mas)) {
0621             dev_err(dev, "Failed to add subdev for source %u: %ld",
0622                 i, PTR_ERR(mas));
0623             v4l2_async_nf_cleanup(&priv->notifier);
0624             return PTR_ERR(mas);
0625         }
0626 
0627         mas->source = source;
0628     }
0629 
0630     priv->notifier.ops = &max9286_notify_ops;
0631 
0632     ret = v4l2_async_subdev_nf_register(&priv->sd, &priv->notifier);
0633     if (ret) {
0634         dev_err(dev, "Failed to register subdev_notifier");
0635         v4l2_async_nf_cleanup(&priv->notifier);
0636         return ret;
0637     }
0638 
0639     return 0;
0640 }
0641 
0642 static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv)
0643 {
0644     if (!priv->nsources)
0645         return;
0646 
0647     v4l2_async_nf_unregister(&priv->notifier);
0648     v4l2_async_nf_cleanup(&priv->notifier);
0649 }
0650 
0651 static int max9286_s_stream(struct v4l2_subdev *sd, int enable)
0652 {
0653     struct max9286_priv *priv = sd_to_max9286(sd);
0654     struct max9286_source *source;
0655     unsigned int i;
0656     bool sync = false;
0657     int ret;
0658 
0659     if (enable) {
0660         /*
0661          * The frame sync between cameras is transmitted across the
0662          * reverse channel as GPIO. We must open all channels while
0663          * streaming to allow this synchronisation signal to be shared.
0664          */
0665         max9286_i2c_mux_open(priv);
0666 
0667         /* Start all cameras. */
0668         for_each_source(priv, source) {
0669             ret = v4l2_subdev_call(source->sd, video, s_stream, 1);
0670             if (ret)
0671                 return ret;
0672         }
0673 
0674         ret = max9286_check_video_links(priv);
0675         if (ret)
0676             return ret;
0677 
0678         /*
0679          * Wait until frame synchronization is locked.
0680          *
0681          * Manual says frame sync locking should take ~6 VTS.
0682          * From practical experience at least 8 are required. Give
0683          * 12 complete frames time (~400ms at 30 fps) to achieve frame
0684          * locking before returning error.
0685          */
0686         for (i = 0; i < 40; i++) {
0687             if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) {
0688                 sync = true;
0689                 break;
0690             }
0691             usleep_range(9000, 11000);
0692         }
0693 
0694         if (!sync) {
0695             dev_err(&priv->client->dev,
0696                 "Failed to get frame synchronization\n");
0697             return -EXDEV; /* Invalid cross-device link */
0698         }
0699 
0700         /*
0701          * Enable CSI output, VC set according to link number.
0702          * Bit 7 must be set (chip manual says it's 0 and reserved).
0703          */
0704         max9286_write(priv, 0x15, 0x80 | MAX9286_VCTYPE |
0705                   MAX9286_CSIOUTEN | MAX9286_0X15_RESV);
0706     } else {
0707         max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
0708 
0709         /* Stop all cameras. */
0710         for_each_source(priv, source)
0711             v4l2_subdev_call(source->sd, video, s_stream, 0);
0712 
0713         max9286_i2c_mux_close(priv);
0714     }
0715 
0716     return 0;
0717 }
0718 
0719 static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
0720                   struct v4l2_subdev_state *sd_state,
0721                   struct v4l2_subdev_mbus_code_enum *code)
0722 {
0723     if (code->pad || code->index > 0)
0724         return -EINVAL;
0725 
0726     code->code = MEDIA_BUS_FMT_UYVY8_1X16;
0727 
0728     return 0;
0729 }
0730 
0731 static struct v4l2_mbus_framefmt *
0732 max9286_get_pad_format(struct max9286_priv *priv,
0733                struct v4l2_subdev_state *sd_state,
0734                unsigned int pad, u32 which)
0735 {
0736     switch (which) {
0737     case V4L2_SUBDEV_FORMAT_TRY:
0738         return v4l2_subdev_get_try_format(&priv->sd, sd_state, pad);
0739     case V4L2_SUBDEV_FORMAT_ACTIVE:
0740         return &priv->fmt[pad];
0741     default:
0742         return NULL;
0743     }
0744 }
0745 
0746 static int max9286_set_fmt(struct v4l2_subdev *sd,
0747                struct v4l2_subdev_state *sd_state,
0748                struct v4l2_subdev_format *format)
0749 {
0750     struct max9286_priv *priv = sd_to_max9286(sd);
0751     struct v4l2_mbus_framefmt *cfg_fmt;
0752 
0753     if (format->pad == MAX9286_SRC_PAD)
0754         return -EINVAL;
0755 
0756     /* Refuse non YUV422 formats as we hardcode DT to 8 bit YUV422 */
0757     switch (format->format.code) {
0758     case MEDIA_BUS_FMT_UYVY8_1X16:
0759     case MEDIA_BUS_FMT_VYUY8_1X16:
0760     case MEDIA_BUS_FMT_YUYV8_1X16:
0761     case MEDIA_BUS_FMT_YVYU8_1X16:
0762         break;
0763     default:
0764         format->format.code = MEDIA_BUS_FMT_UYVY8_1X16;
0765         break;
0766     }
0767 
0768     cfg_fmt = max9286_get_pad_format(priv, sd_state, format->pad,
0769                      format->which);
0770     if (!cfg_fmt)
0771         return -EINVAL;
0772 
0773     mutex_lock(&priv->mutex);
0774     *cfg_fmt = format->format;
0775     mutex_unlock(&priv->mutex);
0776 
0777     return 0;
0778 }
0779 
0780 static int max9286_get_fmt(struct v4l2_subdev *sd,
0781                struct v4l2_subdev_state *sd_state,
0782                struct v4l2_subdev_format *format)
0783 {
0784     struct max9286_priv *priv = sd_to_max9286(sd);
0785     struct v4l2_mbus_framefmt *cfg_fmt;
0786     unsigned int pad = format->pad;
0787 
0788     /*
0789      * Multiplexed Stream Support: Support link validation by returning the
0790      * format of the first bound link. All links must have the same format,
0791      * as we do not support mixing and matching of cameras connected to the
0792      * max9286.
0793      */
0794     if (pad == MAX9286_SRC_PAD)
0795         pad = __ffs(priv->bound_sources);
0796 
0797     cfg_fmt = max9286_get_pad_format(priv, sd_state, pad, format->which);
0798     if (!cfg_fmt)
0799         return -EINVAL;
0800 
0801     mutex_lock(&priv->mutex);
0802     format->format = *cfg_fmt;
0803     mutex_unlock(&priv->mutex);
0804 
0805     return 0;
0806 }
0807 
0808 static const struct v4l2_subdev_video_ops max9286_video_ops = {
0809     .s_stream   = max9286_s_stream,
0810 };
0811 
0812 static const struct v4l2_subdev_pad_ops max9286_pad_ops = {
0813     .enum_mbus_code = max9286_enum_mbus_code,
0814     .get_fmt    = max9286_get_fmt,
0815     .set_fmt    = max9286_set_fmt,
0816 };
0817 
0818 static const struct v4l2_subdev_ops max9286_subdev_ops = {
0819     .video      = &max9286_video_ops,
0820     .pad        = &max9286_pad_ops,
0821 };
0822 
0823 static void max9286_init_format(struct v4l2_mbus_framefmt *fmt)
0824 {
0825     fmt->width      = 1280;
0826     fmt->height     = 800;
0827     fmt->code       = MEDIA_BUS_FMT_UYVY8_1X16;
0828     fmt->colorspace     = V4L2_COLORSPACE_SRGB;
0829     fmt->field      = V4L2_FIELD_NONE;
0830     fmt->ycbcr_enc      = V4L2_YCBCR_ENC_DEFAULT;
0831     fmt->quantization   = V4L2_QUANTIZATION_DEFAULT;
0832     fmt->xfer_func      = V4L2_XFER_FUNC_DEFAULT;
0833 }
0834 
0835 static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
0836 {
0837     struct v4l2_mbus_framefmt *format;
0838     unsigned int i;
0839 
0840     for (i = 0; i < MAX9286_N_SINKS; i++) {
0841         format = v4l2_subdev_get_try_format(subdev, fh->state, i);
0842         max9286_init_format(format);
0843     }
0844 
0845     return 0;
0846 }
0847 
0848 static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = {
0849     .open = max9286_open,
0850 };
0851 
0852 static const struct media_entity_operations max9286_media_ops = {
0853     .link_validate = v4l2_subdev_link_validate
0854 };
0855 
0856 static int max9286_s_ctrl(struct v4l2_ctrl *ctrl)
0857 {
0858     switch (ctrl->id) {
0859     case V4L2_CID_PIXEL_RATE:
0860         return 0;
0861     default:
0862         return -EINVAL;
0863     }
0864 }
0865 
0866 static const struct v4l2_ctrl_ops max9286_ctrl_ops = {
0867     .s_ctrl = max9286_s_ctrl,
0868 };
0869 
0870 static int max9286_v4l2_register(struct max9286_priv *priv)
0871 {
0872     struct device *dev = &priv->client->dev;
0873     struct fwnode_handle *ep;
0874     int ret;
0875     int i;
0876 
0877     /* Register v4l2 async notifiers for connected Camera subdevices */
0878     ret = max9286_v4l2_notifier_register(priv);
0879     if (ret) {
0880         dev_err(dev, "Unable to register V4L2 async notifiers\n");
0881         return ret;
0882     }
0883 
0884     /* Configure V4L2 for the MAX9286 itself */
0885 
0886     for (i = 0; i < MAX9286_N_SINKS; i++)
0887         max9286_init_format(&priv->fmt[i]);
0888 
0889     v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops);
0890     priv->sd.internal_ops = &max9286_subdev_internal_ops;
0891     priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
0892 
0893     v4l2_ctrl_handler_init(&priv->ctrls, 1);
0894     priv->pixelrate = v4l2_ctrl_new_std(&priv->ctrls,
0895                         &max9286_ctrl_ops,
0896                         V4L2_CID_PIXEL_RATE,
0897                         1, INT_MAX, 1, 50000000);
0898 
0899     priv->sd.ctrl_handler = &priv->ctrls;
0900     ret = priv->ctrls.error;
0901     if (ret)
0902         goto err_async;
0903 
0904     priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
0905     priv->sd.entity.ops = &max9286_media_ops;
0906 
0907     priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE;
0908     for (i = 0; i < MAX9286_SRC_PAD; i++)
0909         priv->pads[i].flags = MEDIA_PAD_FL_SINK;
0910     ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS,
0911                      priv->pads);
0912     if (ret)
0913         goto err_async;
0914 
0915     ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), MAX9286_SRC_PAD,
0916                          0, 0);
0917     if (!ep) {
0918         dev_err(dev, "Unable to retrieve endpoint on \"port@4\"\n");
0919         ret = -ENOENT;
0920         goto err_async;
0921     }
0922     priv->sd.fwnode = ep;
0923 
0924     ret = v4l2_async_register_subdev(&priv->sd);
0925     if (ret < 0) {
0926         dev_err(dev, "Unable to register subdevice\n");
0927         goto err_put_node;
0928     }
0929 
0930     return 0;
0931 
0932 err_put_node:
0933     fwnode_handle_put(ep);
0934 err_async:
0935     max9286_v4l2_notifier_unregister(priv);
0936 
0937     return ret;
0938 }
0939 
0940 static void max9286_v4l2_unregister(struct max9286_priv *priv)
0941 {
0942     fwnode_handle_put(priv->sd.fwnode);
0943     v4l2_async_unregister_subdev(&priv->sd);
0944     max9286_v4l2_notifier_unregister(priv);
0945 }
0946 
0947 /* -----------------------------------------------------------------------------
0948  * Probe/Remove
0949  */
0950 
0951 static int max9286_setup(struct max9286_priv *priv)
0952 {
0953     /*
0954      * Link ordering values for all enabled links combinations. Orders must
0955      * be assigned sequentially from 0 to the number of enabled links
0956      * without leaving any hole for disabled links. We thus assign orders to
0957      * enabled links first, and use the remaining order values for disabled
0958      * links are all links must have a different order value;
0959      */
0960     static const u8 link_order[] = {
0961         (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */
0962         (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */
0963         (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */
0964         (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */
0965         (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */
0966         (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */
0967         (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */
0968         (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */
0969         (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */
0970         (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */
0971         (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */
0972         (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */
0973         (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */
0974         (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */
0975         (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */
0976         (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */
0977     };
0978 
0979     /*
0980      * Set the I2C bus speed.
0981      *
0982      * Enable I2C Local Acknowledge during the probe sequences of the camera
0983      * only. This should be disabled after the mux is initialised.
0984      */
0985     max9286_configure_i2c(priv, true);
0986     max9286_reverse_channel_setup(priv, priv->init_rev_chan_mv);
0987 
0988     /*
0989      * Enable GMSL links, mask unused ones and autodetect link
0990      * used as CSI clock source.
0991      */
0992     max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);
0993     max9286_write(priv, 0x0b, link_order[priv->route_mask]);
0994     max9286_write(priv, 0x69, (0xf & ~priv->route_mask));
0995 
0996     /*
0997      * Video format setup:
0998      * Disable CSI output, VC is set according to Link number.
0999      */
1000     max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
1001 
1002     /* Enable CSI-2 Lane D0-D3 only, DBL mode, YUV422 8-bit. */
1003     max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |
1004               MAX9286_CSILANECNT(priv->csi2_data_lanes) |
1005               MAX9286_DATATYPE_YUV422_8BIT);
1006 
1007     /* Automatic: FRAMESYNC taken from the slowest Link. */
1008     max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |
1009               MAX9286_FSYNCMETH_AUTO);
1010 
1011     /* Enable HS/VS encoding, use D14/15 for HS/VS, invert VS. */
1012     max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_INVVS |
1013               MAX9286_HVSRC_D14);
1014 
1015     /*
1016      * The overlap window seems to provide additional validation by tracking
1017      * the delay between vsync and frame sync, generating an error if the
1018      * delay is bigger than the programmed window, though it's not yet clear
1019      * what value should be set.
1020      *
1021      * As it's an optional value and can be disabled, we do so by setting
1022      * a 0 overlap value.
1023      */
1024     max9286_write(priv, 0x63, 0);
1025     max9286_write(priv, 0x64, 0);
1026 
1027     /*
1028      * Wait for 2ms to allow the link to resynchronize after the
1029      * configuration change.
1030      */
1031     usleep_range(2000, 5000);
1032 
1033     return 0;
1034 }
1035 
1036 static int max9286_gpio_set(struct max9286_priv *priv, unsigned int offset,
1037                 int value)
1038 {
1039     if (value)
1040         priv->gpio_state |= BIT(offset);
1041     else
1042         priv->gpio_state &= ~BIT(offset);
1043 
1044     return max9286_write(priv, 0x0f,
1045                  MAX9286_0X0F_RESERVED | priv->gpio_state);
1046 }
1047 
1048 static void max9286_gpiochip_set(struct gpio_chip *chip,
1049                  unsigned int offset, int value)
1050 {
1051     struct max9286_priv *priv = gpiochip_get_data(chip);
1052 
1053     max9286_gpio_set(priv, offset, value);
1054 }
1055 
1056 static int max9286_gpiochip_get(struct gpio_chip *chip, unsigned int offset)
1057 {
1058     struct max9286_priv *priv = gpiochip_get_data(chip);
1059 
1060     return priv->gpio_state & BIT(offset);
1061 }
1062 
1063 static int max9286_register_gpio(struct max9286_priv *priv)
1064 {
1065     struct device *dev = &priv->client->dev;
1066     struct gpio_chip *gpio = &priv->gpio;
1067     int ret;
1068 
1069     /* Configure the GPIO */
1070     gpio->label = dev_name(dev);
1071     gpio->parent = dev;
1072     gpio->owner = THIS_MODULE;
1073     gpio->ngpio = 2;
1074     gpio->base = -1;
1075     gpio->set = max9286_gpiochip_set;
1076     gpio->get = max9286_gpiochip_get;
1077     gpio->can_sleep = true;
1078 
1079     ret = devm_gpiochip_add_data(dev, gpio, priv);
1080     if (ret)
1081         dev_err(dev, "Unable to create gpio_chip\n");
1082 
1083     return ret;
1084 }
1085 
1086 static int max9286_parse_gpios(struct max9286_priv *priv)
1087 {
1088     struct device *dev = &priv->client->dev;
1089     int ret;
1090 
1091     /* GPIO values default to high */
1092     priv->gpio_state = BIT(0) | BIT(1);
1093 
1094     /*
1095      * Parse the "gpio-poc" vendor property. If the property is not
1096      * specified the camera power is controlled by a regulator.
1097      */
1098     ret = of_property_read_u32_array(dev->of_node, "maxim,gpio-poc",
1099                      priv->gpio_poc, 2);
1100     if (ret == -EINVAL) {
1101         /*
1102          * If gpio lines are not used for the camera power, register
1103          * a gpio controller for consumers.
1104          */
1105         ret = max9286_register_gpio(priv);
1106         if (ret)
1107             return ret;
1108 
1109         priv->regulator = devm_regulator_get(dev, "poc");
1110         if (IS_ERR(priv->regulator)) {
1111             return dev_err_probe(dev, PTR_ERR(priv->regulator),
1112                          "Unable to get PoC regulator (%ld)\n",
1113                          PTR_ERR(priv->regulator));
1114         }
1115 
1116         return 0;
1117     }
1118 
1119     /* If the property is specified make sure it is well formed. */
1120     if (ret || priv->gpio_poc[0] > 1 ||
1121         (priv->gpio_poc[1] != GPIO_ACTIVE_HIGH &&
1122          priv->gpio_poc[1] != GPIO_ACTIVE_LOW)) {
1123         dev_err(dev, "Invalid 'gpio-poc' property\n");
1124         return -EINVAL;
1125     }
1126 
1127     return 0;
1128 }
1129 
1130 static int max9286_poc_enable(struct max9286_priv *priv, bool enable)
1131 {
1132     int ret;
1133 
1134     /* If the regulator is not available, use gpio to control power. */
1135     if (!priv->regulator)
1136         ret = max9286_gpio_set(priv, priv->gpio_poc[0],
1137                        enable ^ priv->gpio_poc[1]);
1138     else if (enable)
1139         ret = regulator_enable(priv->regulator);
1140     else
1141         ret = regulator_disable(priv->regulator);
1142 
1143     if (ret < 0)
1144         dev_err(&priv->client->dev, "Unable to turn power %s\n",
1145             enable ? "on" : "off");
1146 
1147     return ret;
1148 }
1149 
1150 static int max9286_init(struct max9286_priv *priv)
1151 {
1152     struct i2c_client *client = priv->client;
1153     int ret;
1154 
1155     ret = max9286_poc_enable(priv, true);
1156     if (ret)
1157         return ret;
1158 
1159     ret = max9286_setup(priv);
1160     if (ret) {
1161         dev_err(&client->dev, "Unable to setup max9286\n");
1162         goto err_poc_disable;
1163     }
1164 
1165     /*
1166      * Register all V4L2 interactions for the MAX9286 and notifiers for
1167      * any subdevices connected.
1168      */
1169     ret = max9286_v4l2_register(priv);
1170     if (ret) {
1171         dev_err(&client->dev, "Failed to register with V4L2\n");
1172         goto err_poc_disable;
1173     }
1174 
1175     ret = max9286_i2c_mux_init(priv);
1176     if (ret) {
1177         dev_err(&client->dev, "Unable to initialize I2C multiplexer\n");
1178         goto err_v4l2_register;
1179     }
1180 
1181     /* Leave the mux channels disabled until they are selected. */
1182     max9286_i2c_mux_close(priv);
1183 
1184     return 0;
1185 
1186 err_v4l2_register:
1187     max9286_v4l2_unregister(priv);
1188 err_poc_disable:
1189     max9286_poc_enable(priv, false);
1190 
1191     return ret;
1192 }
1193 
1194 static void max9286_cleanup_dt(struct max9286_priv *priv)
1195 {
1196     struct max9286_source *source;
1197 
1198     for_each_source(priv, source) {
1199         fwnode_handle_put(source->fwnode);
1200         source->fwnode = NULL;
1201     }
1202 }
1203 
1204 static int max9286_parse_dt(struct max9286_priv *priv)
1205 {
1206     struct device *dev = &priv->client->dev;
1207     struct device_node *i2c_mux;
1208     struct device_node *node = NULL;
1209     unsigned int i2c_mux_mask = 0;
1210     u32 reverse_channel_microvolt;
1211 
1212     /* Balance the of_node_put() performed by of_find_node_by_name(). */
1213     of_node_get(dev->of_node);
1214     i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
1215     if (!i2c_mux) {
1216         dev_err(dev, "Failed to find i2c-mux node\n");
1217         return -EINVAL;
1218     }
1219 
1220     /* Identify which i2c-mux channels are enabled */
1221     for_each_child_of_node(i2c_mux, node) {
1222         u32 id = 0;
1223 
1224         of_property_read_u32(node, "reg", &id);
1225         if (id >= MAX9286_NUM_GMSL)
1226             continue;
1227 
1228         if (!of_device_is_available(node)) {
1229             dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
1230             continue;
1231         }
1232 
1233         i2c_mux_mask |= BIT(id);
1234     }
1235     of_node_put(node);
1236     of_node_put(i2c_mux);
1237 
1238     /* Parse the endpoints */
1239     for_each_endpoint_of_node(dev->of_node, node) {
1240         struct max9286_source *source;
1241         struct of_endpoint ep;
1242 
1243         of_graph_parse_endpoint(node, &ep);
1244         dev_dbg(dev, "Endpoint %pOF on port %d",
1245             ep.local_node, ep.port);
1246 
1247         if (ep.port > MAX9286_NUM_GMSL) {
1248             dev_err(dev, "Invalid endpoint %s on port %d",
1249                 of_node_full_name(ep.local_node), ep.port);
1250             continue;
1251         }
1252 
1253         /* For the source endpoint just parse the bus configuration. */
1254         if (ep.port == MAX9286_SRC_PAD) {
1255             struct v4l2_fwnode_endpoint vep = {
1256                 .bus_type = V4L2_MBUS_CSI2_DPHY
1257             };
1258             int ret;
1259 
1260             ret = v4l2_fwnode_endpoint_parse(
1261                     of_fwnode_handle(node), &vep);
1262             if (ret) {
1263                 of_node_put(node);
1264                 return ret;
1265             }
1266 
1267             priv->csi2_data_lanes =
1268                 vep.bus.mipi_csi2.num_data_lanes;
1269 
1270             continue;
1271         }
1272 
1273         /* Skip if the corresponding GMSL link is unavailable. */
1274         if (!(i2c_mux_mask & BIT(ep.port)))
1275             continue;
1276 
1277         if (priv->sources[ep.port].fwnode) {
1278             dev_err(dev,
1279                 "Multiple port endpoints are not supported: %d",
1280                 ep.port);
1281 
1282             continue;
1283         }
1284 
1285         source = &priv->sources[ep.port];
1286         source->fwnode = fwnode_graph_get_remote_endpoint(
1287                         of_fwnode_handle(node));
1288         if (!source->fwnode) {
1289             dev_err(dev,
1290                 "Endpoint %pOF has no remote endpoint connection\n",
1291                 ep.local_node);
1292 
1293             continue;
1294         }
1295 
1296         priv->source_mask |= BIT(ep.port);
1297         priv->nsources++;
1298     }
1299     of_node_put(node);
1300 
1301     /*
1302      * Parse the initial value of the reverse channel amplitude from
1303      * the firmware interface and convert it to millivolts.
1304      *
1305      * Default it to 170mV for backward compatibility with DTBs that do not
1306      * provide the property.
1307      */
1308     if (of_property_read_u32(dev->of_node,
1309                  "maxim,reverse-channel-microvolt",
1310                  &reverse_channel_microvolt))
1311         priv->init_rev_chan_mv = 170;
1312     else
1313         priv->init_rev_chan_mv = reverse_channel_microvolt / 1000U;
1314 
1315     priv->route_mask = priv->source_mask;
1316 
1317     return 0;
1318 }
1319 
1320 static int max9286_probe(struct i2c_client *client)
1321 {
1322     struct max9286_priv *priv;
1323     int ret;
1324 
1325     priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1326     if (!priv)
1327         return -ENOMEM;
1328 
1329     mutex_init(&priv->mutex);
1330 
1331     priv->client = client;
1332 
1333     priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
1334                            GPIOD_OUT_HIGH);
1335     if (IS_ERR(priv->gpiod_pwdn))
1336         return PTR_ERR(priv->gpiod_pwdn);
1337 
1338     gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn");
1339     gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
1340 
1341     /* Wait at least 4ms before the I2C lines latch to the address */
1342     if (priv->gpiod_pwdn)
1343         usleep_range(4000, 5000);
1344 
1345     /*
1346      * The MAX9286 starts by default with all ports enabled, we disable all
1347      * ports early to ensure that all channels are disabled if we error out
1348      * and keep the bus consistent.
1349      */
1350     max9286_i2c_mux_close(priv);
1351 
1352     /*
1353      * The MAX9286 initialises with auto-acknowledge enabled by default.
1354      * This can be invasive to other transactions on the same bus, so
1355      * disable it early. It will be enabled only as and when needed.
1356      */
1357     max9286_configure_i2c(priv, false);
1358 
1359     ret = max9286_parse_gpios(priv);
1360     if (ret)
1361         goto err_powerdown;
1362 
1363     ret = max9286_parse_dt(priv);
1364     if (ret)
1365         goto err_powerdown;
1366 
1367     ret = max9286_init(priv);
1368     if (ret < 0)
1369         goto err_cleanup_dt;
1370 
1371     return 0;
1372 
1373 err_cleanup_dt:
1374     max9286_cleanup_dt(priv);
1375 err_powerdown:
1376     gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1377 
1378     return ret;
1379 }
1380 
1381 static int max9286_remove(struct i2c_client *client)
1382 {
1383     struct max9286_priv *priv = sd_to_max9286(i2c_get_clientdata(client));
1384 
1385     i2c_mux_del_adapters(priv->mux);
1386 
1387     max9286_v4l2_unregister(priv);
1388 
1389     max9286_poc_enable(priv, false);
1390 
1391     gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1392 
1393     max9286_cleanup_dt(priv);
1394 
1395     return 0;
1396 }
1397 
1398 static const struct of_device_id max9286_dt_ids[] = {
1399     { .compatible = "maxim,max9286" },
1400     {},
1401 };
1402 MODULE_DEVICE_TABLE(of, max9286_dt_ids);
1403 
1404 static struct i2c_driver max9286_i2c_driver = {
1405     .driver = {
1406         .name       = "max9286",
1407         .of_match_table = of_match_ptr(max9286_dt_ids),
1408     },
1409     .probe_new  = max9286_probe,
1410     .remove     = max9286_remove,
1411 };
1412 
1413 module_i2c_driver(max9286_i2c_driver);
1414 
1415 MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver");
1416 MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov");
1417 MODULE_LICENSE("GPL");
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