0001
0002
0003
0004
0005
0006
0007 #include <asm/unaligned.h>
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/i2c.h>
0012 #include <linux/module.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/regulator/consumer.h>
0015
0016 #include <media/v4l2-ctrls.h>
0017 #include <media/v4l2-fwnode.h>
0018 #include <media/v4l2-subdev.h>
0019
0020
0021 #define IMX412_REG_MODE_SELECT 0x0100
0022 #define IMX412_MODE_STANDBY 0x00
0023 #define IMX412_MODE_STREAMING 0x01
0024
0025
0026 #define IMX412_REG_LPFR 0x0340
0027
0028
0029 #define IMX412_REG_ID 0x0016
0030 #define IMX412_ID 0x577
0031
0032
0033 #define IMX412_REG_EXPOSURE_CIT 0x0202
0034 #define IMX412_EXPOSURE_MIN 8
0035 #define IMX412_EXPOSURE_OFFSET 22
0036 #define IMX412_EXPOSURE_STEP 1
0037 #define IMX412_EXPOSURE_DEFAULT 0x0648
0038
0039
0040 #define IMX412_REG_AGAIN 0x0204
0041 #define IMX412_AGAIN_MIN 0
0042 #define IMX412_AGAIN_MAX 978
0043 #define IMX412_AGAIN_STEP 1
0044 #define IMX412_AGAIN_DEFAULT 0
0045
0046
0047 #define IMX412_REG_HOLD 0x0104
0048
0049
0050 #define IMX412_INCLK_RATE 24000000
0051
0052
0053 #define IMX412_LINK_FREQ 600000000
0054 #define IMX412_NUM_DATA_LANES 4
0055
0056 #define IMX412_REG_MIN 0x00
0057 #define IMX412_REG_MAX 0xffff
0058
0059
0060
0061
0062
0063
0064 struct imx412_reg {
0065 u16 address;
0066 u8 val;
0067 };
0068
0069
0070
0071
0072
0073
0074 struct imx412_reg_list {
0075 u32 num_of_regs;
0076 const struct imx412_reg *regs;
0077 };
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092 struct imx412_mode {
0093 u32 width;
0094 u32 height;
0095 u32 code;
0096 u32 hblank;
0097 u32 vblank;
0098 u32 vblank_min;
0099 u32 vblank_max;
0100 u64 pclk;
0101 u32 link_freq_idx;
0102 struct imx412_reg_list reg_list;
0103 };
0104
0105 static const char * const imx412_supply_names[] = {
0106 "dovdd",
0107 "avdd",
0108 "dvdd",
0109 };
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132 struct imx412 {
0133 struct device *dev;
0134 struct i2c_client *client;
0135 struct v4l2_subdev sd;
0136 struct media_pad pad;
0137 struct gpio_desc *reset_gpio;
0138 struct clk *inclk;
0139 struct regulator_bulk_data supplies[ARRAY_SIZE(imx412_supply_names)];
0140 struct v4l2_ctrl_handler ctrl_handler;
0141 struct v4l2_ctrl *link_freq_ctrl;
0142 struct v4l2_ctrl *pclk_ctrl;
0143 struct v4l2_ctrl *hblank_ctrl;
0144 struct v4l2_ctrl *vblank_ctrl;
0145 struct {
0146 struct v4l2_ctrl *exp_ctrl;
0147 struct v4l2_ctrl *again_ctrl;
0148 };
0149 u32 vblank;
0150 const struct imx412_mode *cur_mode;
0151 struct mutex mutex;
0152 bool streaming;
0153 };
0154
0155 static const s64 link_freq[] = {
0156 IMX412_LINK_FREQ,
0157 };
0158
0159
0160 static const struct imx412_reg mode_4056x3040_regs[] = {
0161 {0x0136, 0x18},
0162 {0x0137, 0x00},
0163 {0x3c7e, 0x08},
0164 {0x3c7f, 0x02},
0165 {0x38a8, 0x1f},
0166 {0x38a9, 0xff},
0167 {0x38aa, 0x1f},
0168 {0x38ab, 0xff},
0169 {0x55d4, 0x00},
0170 {0x55d5, 0x00},
0171 {0x55d6, 0x07},
0172 {0x55d7, 0xff},
0173 {0x55e8, 0x07},
0174 {0x55e9, 0xff},
0175 {0x55ea, 0x00},
0176 {0x55eb, 0x00},
0177 {0x575c, 0x07},
0178 {0x575d, 0xff},
0179 {0x575e, 0x00},
0180 {0x575f, 0x00},
0181 {0x5764, 0x00},
0182 {0x5765, 0x00},
0183 {0x5766, 0x07},
0184 {0x5767, 0xff},
0185 {0x5974, 0x04},
0186 {0x5975, 0x01},
0187 {0x5f10, 0x09},
0188 {0x5f11, 0x92},
0189 {0x5f12, 0x32},
0190 {0x5f13, 0x72},
0191 {0x5f14, 0x16},
0192 {0x5f15, 0xba},
0193 {0x5f17, 0x13},
0194 {0x5f18, 0x24},
0195 {0x5f19, 0x60},
0196 {0x5f1a, 0xe3},
0197 {0x5f1b, 0xad},
0198 {0x5f1c, 0x74},
0199 {0x5f2d, 0x25},
0200 {0x5f5c, 0xd0},
0201 {0x6a22, 0x00},
0202 {0x6a23, 0x1d},
0203 {0x7ba8, 0x00},
0204 {0x7ba9, 0x00},
0205 {0x886b, 0x00},
0206 {0x9002, 0x0a},
0207 {0x9004, 0x1a},
0208 {0x9214, 0x93},
0209 {0x9215, 0x69},
0210 {0x9216, 0x93},
0211 {0x9217, 0x6b},
0212 {0x9218, 0x93},
0213 {0x9219, 0x6d},
0214 {0x921a, 0x57},
0215 {0x921b, 0x58},
0216 {0x921c, 0x57},
0217 {0x921d, 0x59},
0218 {0x921e, 0x57},
0219 {0x921f, 0x5a},
0220 {0x9220, 0x57},
0221 {0x9221, 0x5b},
0222 {0x9222, 0x93},
0223 {0x9223, 0x02},
0224 {0x9224, 0x93},
0225 {0x9225, 0x03},
0226 {0x9226, 0x93},
0227 {0x9227, 0x04},
0228 {0x9228, 0x93},
0229 {0x9229, 0x05},
0230 {0x922a, 0x98},
0231 {0x922b, 0x21},
0232 {0x922c, 0xb2},
0233 {0x922d, 0xdb},
0234 {0x922e, 0xb2},
0235 {0x922f, 0xdc},
0236 {0x9230, 0xb2},
0237 {0x9231, 0xdd},
0238 {0x9232, 0xe2},
0239 {0x9233, 0xe1},
0240 {0x9234, 0xb2},
0241 {0x9235, 0xe2},
0242 {0x9236, 0xb2},
0243 {0x9237, 0xe3},
0244 {0x9238, 0xb7},
0245 {0x9239, 0xb9},
0246 {0x923a, 0xb7},
0247 {0x923b, 0xbb},
0248 {0x923c, 0xb7},
0249 {0x923d, 0xbc},
0250 {0x923e, 0xb7},
0251 {0x923f, 0xc5},
0252 {0x9240, 0xb7},
0253 {0x9241, 0xc7},
0254 {0x9242, 0xb7},
0255 {0x9243, 0xc9},
0256 {0x9244, 0x98},
0257 {0x9245, 0x56},
0258 {0x9246, 0x98},
0259 {0x9247, 0x55},
0260 {0x9380, 0x00},
0261 {0x9381, 0x62},
0262 {0x9382, 0x00},
0263 {0x9383, 0x56},
0264 {0x9384, 0x00},
0265 {0x9385, 0x52},
0266 {0x9388, 0x00},
0267 {0x9389, 0x55},
0268 {0x938a, 0x00},
0269 {0x938b, 0x55},
0270 {0x938c, 0x00},
0271 {0x938d, 0x41},
0272 {0x5078, 0x01},
0273 {0x0112, 0x0a},
0274 {0x0113, 0x0a},
0275 {0x0114, 0x03},
0276 {0x0342, 0x11},
0277 {0x0343, 0xa0},
0278 {0x0340, 0x0d},
0279 {0x0341, 0xda},
0280 {0x3210, 0x00},
0281 {0x0344, 0x00},
0282 {0x0345, 0x00},
0283 {0x0346, 0x00},
0284 {0x0347, 0x00},
0285 {0x0348, 0x0f},
0286 {0x0349, 0xd7},
0287 {0x034a, 0x0b},
0288 {0x034b, 0xdf},
0289 {0x00e3, 0x00},
0290 {0x00e4, 0x00},
0291 {0x00e5, 0x01},
0292 {0x00fc, 0x0a},
0293 {0x00fd, 0x0a},
0294 {0x00fe, 0x0a},
0295 {0x00ff, 0x0a},
0296 {0xe013, 0x00},
0297 {0x0220, 0x00},
0298 {0x0221, 0x11},
0299 {0x0381, 0x01},
0300 {0x0383, 0x01},
0301 {0x0385, 0x01},
0302 {0x0387, 0x01},
0303 {0x0900, 0x00},
0304 {0x0901, 0x11},
0305 {0x0902, 0x00},
0306 {0x3140, 0x02},
0307 {0x3241, 0x11},
0308 {0x3250, 0x03},
0309 {0x3e10, 0x00},
0310 {0x3e11, 0x00},
0311 {0x3f0d, 0x00},
0312 {0x3f42, 0x00},
0313 {0x3f43, 0x00},
0314 {0x0401, 0x00},
0315 {0x0404, 0x00},
0316 {0x0405, 0x10},
0317 {0x0408, 0x00},
0318 {0x0409, 0x00},
0319 {0x040a, 0x00},
0320 {0x040b, 0x00},
0321 {0x040c, 0x0f},
0322 {0x040d, 0xd8},
0323 {0x040e, 0x0b},
0324 {0x040f, 0xe0},
0325 {0x034c, 0x0f},
0326 {0x034d, 0xd8},
0327 {0x034e, 0x0b},
0328 {0x034f, 0xe0},
0329 {0x0301, 0x05},
0330 {0x0303, 0x02},
0331 {0x0305, 0x04},
0332 {0x0306, 0x00},
0333 {0x0307, 0xc8},
0334 {0x0309, 0x0a},
0335 {0x030b, 0x01},
0336 {0x030d, 0x02},
0337 {0x030e, 0x01},
0338 {0x030f, 0x5e},
0339 {0x0310, 0x00},
0340 {0x0820, 0x12},
0341 {0x0821, 0xc0},
0342 {0x0822, 0x00},
0343 {0x0823, 0x00},
0344 {0x3e20, 0x01},
0345 {0x3e37, 0x00},
0346 {0x3f50, 0x00},
0347 {0x3f56, 0x00},
0348 {0x3f57, 0xe2},
0349 {0x3c0a, 0x5a},
0350 {0x3c0b, 0x55},
0351 {0x3c0c, 0x28},
0352 {0x3c0d, 0x07},
0353 {0x3c0e, 0xff},
0354 {0x3c0f, 0x00},
0355 {0x3c10, 0x00},
0356 {0x3c11, 0x02},
0357 {0x3c12, 0x00},
0358 {0x3c13, 0x03},
0359 {0x3c14, 0x00},
0360 {0x3c15, 0x00},
0361 {0x3c16, 0x0c},
0362 {0x3c17, 0x0c},
0363 {0x3c18, 0x0c},
0364 {0x3c19, 0x0a},
0365 {0x3c1a, 0x0a},
0366 {0x3c1b, 0x0a},
0367 {0x3c1c, 0x00},
0368 {0x3c1d, 0x00},
0369 {0x3c1e, 0x00},
0370 {0x3c1f, 0x00},
0371 {0x3c20, 0x00},
0372 {0x3c21, 0x00},
0373 {0x3c22, 0x3f},
0374 {0x3c23, 0x0a},
0375 {0x3e35, 0x01},
0376 {0x3f4a, 0x03},
0377 {0x3f4b, 0xbf},
0378 {0x3f26, 0x00},
0379 {0x0202, 0x0d},
0380 {0x0203, 0xc4},
0381 {0x0204, 0x00},
0382 {0x0205, 0x00},
0383 {0x020e, 0x01},
0384 {0x020f, 0x00},
0385 {0x0210, 0x01},
0386 {0x0211, 0x00},
0387 {0x0212, 0x01},
0388 {0x0213, 0x00},
0389 {0x0214, 0x01},
0390 {0x0215, 0x00},
0391 {0xbcf1, 0x00},
0392 };
0393
0394
0395 static const struct imx412_mode supported_mode = {
0396 .width = 4056,
0397 .height = 3040,
0398 .hblank = 456,
0399 .vblank = 506,
0400 .vblank_min = 506,
0401 .vblank_max = 32420,
0402 .pclk = 480000000,
0403 .link_freq_idx = 0,
0404 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
0405 .reg_list = {
0406 .num_of_regs = ARRAY_SIZE(mode_4056x3040_regs),
0407 .regs = mode_4056x3040_regs,
0408 },
0409 };
0410
0411
0412
0413
0414
0415
0416
0417 static inline struct imx412 *to_imx412(struct v4l2_subdev *subdev)
0418 {
0419 return container_of(subdev, struct imx412, sd);
0420 }
0421
0422
0423
0424
0425
0426
0427
0428
0429
0430
0431 static int imx412_read_reg(struct imx412 *imx412, u16 reg, u32 len, u32 *val)
0432 {
0433 struct i2c_client *client = v4l2_get_subdevdata(&imx412->sd);
0434 struct i2c_msg msgs[2] = {0};
0435 u8 addr_buf[2] = {0};
0436 u8 data_buf[4] = {0};
0437 int ret;
0438
0439 if (WARN_ON(len > 4))
0440 return -EINVAL;
0441
0442 put_unaligned_be16(reg, addr_buf);
0443
0444
0445 msgs[0].addr = client->addr;
0446 msgs[0].flags = 0;
0447 msgs[0].len = ARRAY_SIZE(addr_buf);
0448 msgs[0].buf = addr_buf;
0449
0450
0451 msgs[1].addr = client->addr;
0452 msgs[1].flags = I2C_M_RD;
0453 msgs[1].len = len;
0454 msgs[1].buf = &data_buf[4 - len];
0455
0456 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0457 if (ret != ARRAY_SIZE(msgs))
0458 return -EIO;
0459
0460 *val = get_unaligned_be32(data_buf);
0461
0462 return 0;
0463 }
0464
0465
0466
0467
0468
0469
0470
0471
0472
0473
0474 static int imx412_write_reg(struct imx412 *imx412, u16 reg, u32 len, u32 val)
0475 {
0476 struct i2c_client *client = v4l2_get_subdevdata(&imx412->sd);
0477 u8 buf[6] = {0};
0478
0479 if (WARN_ON(len > 4))
0480 return -EINVAL;
0481
0482 put_unaligned_be16(reg, buf);
0483 put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
0484 if (i2c_master_send(client, buf, len + 2) != len + 2)
0485 return -EIO;
0486
0487 return 0;
0488 }
0489
0490
0491
0492
0493
0494
0495
0496
0497
0498 static int imx412_write_regs(struct imx412 *imx412,
0499 const struct imx412_reg *regs, u32 len)
0500 {
0501 unsigned int i;
0502 int ret;
0503
0504 for (i = 0; i < len; i++) {
0505 ret = imx412_write_reg(imx412, regs[i].address, 1, regs[i].val);
0506 if (ret)
0507 return ret;
0508 }
0509
0510 return 0;
0511 }
0512
0513
0514
0515
0516
0517
0518
0519
0520 static int imx412_update_controls(struct imx412 *imx412,
0521 const struct imx412_mode *mode)
0522 {
0523 int ret;
0524
0525 ret = __v4l2_ctrl_s_ctrl(imx412->link_freq_ctrl, mode->link_freq_idx);
0526 if (ret)
0527 return ret;
0528
0529 ret = __v4l2_ctrl_s_ctrl(imx412->hblank_ctrl, mode->hblank);
0530 if (ret)
0531 return ret;
0532
0533 return __v4l2_ctrl_modify_range(imx412->vblank_ctrl, mode->vblank_min,
0534 mode->vblank_max, 1, mode->vblank);
0535 }
0536
0537
0538
0539
0540
0541
0542
0543
0544
0545 static int imx412_update_exp_gain(struct imx412 *imx412, u32 exposure, u32 gain)
0546 {
0547 u32 lpfr, shutter;
0548 int ret;
0549
0550 lpfr = imx412->vblank + imx412->cur_mode->height;
0551 shutter = lpfr - exposure;
0552
0553 dev_dbg(imx412->dev, "Set exp %u, analog gain %u, shutter %u, lpfr %u",
0554 exposure, gain, shutter, lpfr);
0555
0556 ret = imx412_write_reg(imx412, IMX412_REG_HOLD, 1, 1);
0557 if (ret)
0558 return ret;
0559
0560 ret = imx412_write_reg(imx412, IMX412_REG_LPFR, 2, lpfr);
0561 if (ret)
0562 goto error_release_group_hold;
0563
0564 ret = imx412_write_reg(imx412, IMX412_REG_EXPOSURE_CIT, 2, shutter);
0565 if (ret)
0566 goto error_release_group_hold;
0567
0568 ret = imx412_write_reg(imx412, IMX412_REG_AGAIN, 2, gain);
0569
0570 error_release_group_hold:
0571 imx412_write_reg(imx412, IMX412_REG_HOLD, 1, 0);
0572
0573 return ret;
0574 }
0575
0576
0577
0578
0579
0580
0581
0582
0583
0584
0585
0586
0587
0588 static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
0589 {
0590 struct imx412 *imx412 =
0591 container_of(ctrl->handler, struct imx412, ctrl_handler);
0592 u32 analog_gain;
0593 u32 exposure;
0594 int ret;
0595
0596 switch (ctrl->id) {
0597 case V4L2_CID_VBLANK:
0598 imx412->vblank = imx412->vblank_ctrl->val;
0599
0600 dev_dbg(imx412->dev, "Received vblank %u, new lpfr %u",
0601 imx412->vblank,
0602 imx412->vblank + imx412->cur_mode->height);
0603
0604 ret = __v4l2_ctrl_modify_range(imx412->exp_ctrl,
0605 IMX412_EXPOSURE_MIN,
0606 imx412->vblank +
0607 imx412->cur_mode->height -
0608 IMX412_EXPOSURE_OFFSET,
0609 1, IMX412_EXPOSURE_DEFAULT);
0610 break;
0611 case V4L2_CID_EXPOSURE:
0612
0613 if (!pm_runtime_get_if_in_use(imx412->dev))
0614 return 0;
0615
0616 exposure = ctrl->val;
0617 analog_gain = imx412->again_ctrl->val;
0618
0619 dev_dbg(imx412->dev, "Received exp %u, analog gain %u",
0620 exposure, analog_gain);
0621
0622 ret = imx412_update_exp_gain(imx412, exposure, analog_gain);
0623
0624 pm_runtime_put(imx412->dev);
0625
0626 break;
0627 default:
0628 dev_err(imx412->dev, "Invalid control %d", ctrl->id);
0629 ret = -EINVAL;
0630 }
0631
0632 return ret;
0633 }
0634
0635
0636 static const struct v4l2_ctrl_ops imx412_ctrl_ops = {
0637 .s_ctrl = imx412_set_ctrl,
0638 };
0639
0640
0641
0642
0643
0644
0645
0646
0647
0648 static int imx412_enum_mbus_code(struct v4l2_subdev *sd,
0649 struct v4l2_subdev_state *sd_state,
0650 struct v4l2_subdev_mbus_code_enum *code)
0651 {
0652 if (code->index > 0)
0653 return -EINVAL;
0654
0655 code->code = supported_mode.code;
0656
0657 return 0;
0658 }
0659
0660
0661
0662
0663
0664
0665
0666
0667
0668 static int imx412_enum_frame_size(struct v4l2_subdev *sd,
0669 struct v4l2_subdev_state *sd_state,
0670 struct v4l2_subdev_frame_size_enum *fsize)
0671 {
0672 if (fsize->index > 0)
0673 return -EINVAL;
0674
0675 if (fsize->code != supported_mode.code)
0676 return -EINVAL;
0677
0678 fsize->min_width = supported_mode.width;
0679 fsize->max_width = fsize->min_width;
0680 fsize->min_height = supported_mode.height;
0681 fsize->max_height = fsize->min_height;
0682
0683 return 0;
0684 }
0685
0686
0687
0688
0689
0690
0691
0692
0693 static void imx412_fill_pad_format(struct imx412 *imx412,
0694 const struct imx412_mode *mode,
0695 struct v4l2_subdev_format *fmt)
0696 {
0697 fmt->format.width = mode->width;
0698 fmt->format.height = mode->height;
0699 fmt->format.code = mode->code;
0700 fmt->format.field = V4L2_FIELD_NONE;
0701 fmt->format.colorspace = V4L2_COLORSPACE_RAW;
0702 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
0703 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT;
0704 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
0705 }
0706
0707
0708
0709
0710
0711
0712
0713
0714
0715 static int imx412_get_pad_format(struct v4l2_subdev *sd,
0716 struct v4l2_subdev_state *sd_state,
0717 struct v4l2_subdev_format *fmt)
0718 {
0719 struct imx412 *imx412 = to_imx412(sd);
0720
0721 mutex_lock(&imx412->mutex);
0722
0723 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0724 struct v4l2_mbus_framefmt *framefmt;
0725
0726 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0727 fmt->format = *framefmt;
0728 } else {
0729 imx412_fill_pad_format(imx412, imx412->cur_mode, fmt);
0730 }
0731
0732 mutex_unlock(&imx412->mutex);
0733
0734 return 0;
0735 }
0736
0737
0738
0739
0740
0741
0742
0743
0744
0745 static int imx412_set_pad_format(struct v4l2_subdev *sd,
0746 struct v4l2_subdev_state *sd_state,
0747 struct v4l2_subdev_format *fmt)
0748 {
0749 struct imx412 *imx412 = to_imx412(sd);
0750 const struct imx412_mode *mode;
0751 int ret = 0;
0752
0753 mutex_lock(&imx412->mutex);
0754
0755 mode = &supported_mode;
0756 imx412_fill_pad_format(imx412, mode, fmt);
0757
0758 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0759 struct v4l2_mbus_framefmt *framefmt;
0760
0761 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0762 *framefmt = fmt->format;
0763 } else {
0764 ret = imx412_update_controls(imx412, mode);
0765 if (!ret)
0766 imx412->cur_mode = mode;
0767 }
0768
0769 mutex_unlock(&imx412->mutex);
0770
0771 return ret;
0772 }
0773
0774
0775
0776
0777
0778
0779
0780
0781 static int imx412_init_pad_cfg(struct v4l2_subdev *sd,
0782 struct v4l2_subdev_state *sd_state)
0783 {
0784 struct imx412 *imx412 = to_imx412(sd);
0785 struct v4l2_subdev_format fmt = { 0 };
0786
0787 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
0788 imx412_fill_pad_format(imx412, &supported_mode, &fmt);
0789
0790 return imx412_set_pad_format(sd, sd_state, &fmt);
0791 }
0792
0793
0794
0795
0796
0797
0798
0799 static int imx412_start_streaming(struct imx412 *imx412)
0800 {
0801 const struct imx412_reg_list *reg_list;
0802 int ret;
0803
0804
0805 reg_list = &imx412->cur_mode->reg_list;
0806 ret = imx412_write_regs(imx412, reg_list->regs,
0807 reg_list->num_of_regs);
0808 if (ret) {
0809 dev_err(imx412->dev, "fail to write initial registers");
0810 return ret;
0811 }
0812
0813
0814 ret = __v4l2_ctrl_handler_setup(imx412->sd.ctrl_handler);
0815 if (ret) {
0816 dev_err(imx412->dev, "fail to setup handler");
0817 return ret;
0818 }
0819
0820
0821 usleep_range(7400, 8000);
0822
0823
0824 ret = imx412_write_reg(imx412, IMX412_REG_MODE_SELECT,
0825 1, IMX412_MODE_STREAMING);
0826 if (ret) {
0827 dev_err(imx412->dev, "fail to start streaming");
0828 return ret;
0829 }
0830
0831 return 0;
0832 }
0833
0834
0835
0836
0837
0838
0839
0840 static int imx412_stop_streaming(struct imx412 *imx412)
0841 {
0842 return imx412_write_reg(imx412, IMX412_REG_MODE_SELECT,
0843 1, IMX412_MODE_STANDBY);
0844 }
0845
0846
0847
0848
0849
0850
0851
0852
0853 static int imx412_set_stream(struct v4l2_subdev *sd, int enable)
0854 {
0855 struct imx412 *imx412 = to_imx412(sd);
0856 int ret;
0857
0858 mutex_lock(&imx412->mutex);
0859
0860 if (imx412->streaming == enable) {
0861 mutex_unlock(&imx412->mutex);
0862 return 0;
0863 }
0864
0865 if (enable) {
0866 ret = pm_runtime_resume_and_get(imx412->dev);
0867 if (ret)
0868 goto error_unlock;
0869
0870 ret = imx412_start_streaming(imx412);
0871 if (ret)
0872 goto error_power_off;
0873 } else {
0874 imx412_stop_streaming(imx412);
0875 pm_runtime_put(imx412->dev);
0876 }
0877
0878 imx412->streaming = enable;
0879
0880 mutex_unlock(&imx412->mutex);
0881
0882 return 0;
0883
0884 error_power_off:
0885 pm_runtime_put(imx412->dev);
0886 error_unlock:
0887 mutex_unlock(&imx412->mutex);
0888
0889 return ret;
0890 }
0891
0892
0893
0894
0895
0896
0897
0898 static int imx412_detect(struct imx412 *imx412)
0899 {
0900 int ret;
0901 u32 val;
0902
0903 ret = imx412_read_reg(imx412, IMX412_REG_ID, 2, &val);
0904 if (ret)
0905 return ret;
0906
0907 if (val != IMX412_ID) {
0908 dev_err(imx412->dev, "chip id mismatch: %x!=%x",
0909 IMX412_ID, val);
0910 return -ENXIO;
0911 }
0912
0913 return 0;
0914 }
0915
0916
0917
0918
0919
0920
0921
0922 static int imx412_parse_hw_config(struct imx412 *imx412)
0923 {
0924 struct fwnode_handle *fwnode = dev_fwnode(imx412->dev);
0925 struct v4l2_fwnode_endpoint bus_cfg = {
0926 .bus_type = V4L2_MBUS_CSI2_DPHY
0927 };
0928 struct fwnode_handle *ep;
0929 unsigned long rate;
0930 unsigned int i;
0931 int ret;
0932
0933 if (!fwnode)
0934 return -ENXIO;
0935
0936
0937 imx412->reset_gpio = devm_gpiod_get_optional(imx412->dev, "reset",
0938 GPIOD_OUT_LOW);
0939 if (IS_ERR(imx412->reset_gpio)) {
0940 dev_err(imx412->dev, "failed to get reset gpio %ld",
0941 PTR_ERR(imx412->reset_gpio));
0942 return PTR_ERR(imx412->reset_gpio);
0943 }
0944
0945
0946 imx412->inclk = devm_clk_get(imx412->dev, NULL);
0947 if (IS_ERR(imx412->inclk)) {
0948 dev_err(imx412->dev, "could not get inclk");
0949 return PTR_ERR(imx412->inclk);
0950 }
0951
0952 rate = clk_get_rate(imx412->inclk);
0953 if (rate != IMX412_INCLK_RATE) {
0954 dev_err(imx412->dev, "inclk frequency mismatch");
0955 return -EINVAL;
0956 }
0957
0958
0959 for (i = 0; i < ARRAY_SIZE(imx412_supply_names); i++)
0960 imx412->supplies[i].supply = imx412_supply_names[i];
0961
0962 ret = devm_regulator_bulk_get(imx412->dev,
0963 ARRAY_SIZE(imx412_supply_names),
0964 imx412->supplies);
0965 if (ret)
0966 return ret;
0967
0968 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
0969 if (!ep)
0970 return -ENXIO;
0971
0972 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
0973 fwnode_handle_put(ep);
0974 if (ret)
0975 return ret;
0976
0977 if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX412_NUM_DATA_LANES) {
0978 dev_err(imx412->dev,
0979 "number of CSI2 data lanes %d is not supported",
0980 bus_cfg.bus.mipi_csi2.num_data_lanes);
0981 ret = -EINVAL;
0982 goto done_endpoint_free;
0983 }
0984
0985 if (!bus_cfg.nr_of_link_frequencies) {
0986 dev_err(imx412->dev, "no link frequencies defined");
0987 ret = -EINVAL;
0988 goto done_endpoint_free;
0989 }
0990
0991 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++)
0992 if (bus_cfg.link_frequencies[i] == IMX412_LINK_FREQ)
0993 goto done_endpoint_free;
0994
0995 ret = -EINVAL;
0996
0997 done_endpoint_free:
0998 v4l2_fwnode_endpoint_free(&bus_cfg);
0999
1000 return ret;
1001 }
1002
1003
1004 static const struct v4l2_subdev_video_ops imx412_video_ops = {
1005 .s_stream = imx412_set_stream,
1006 };
1007
1008 static const struct v4l2_subdev_pad_ops imx412_pad_ops = {
1009 .init_cfg = imx412_init_pad_cfg,
1010 .enum_mbus_code = imx412_enum_mbus_code,
1011 .enum_frame_size = imx412_enum_frame_size,
1012 .get_fmt = imx412_get_pad_format,
1013 .set_fmt = imx412_set_pad_format,
1014 };
1015
1016 static const struct v4l2_subdev_ops imx412_subdev_ops = {
1017 .video = &imx412_video_ops,
1018 .pad = &imx412_pad_ops,
1019 };
1020
1021
1022
1023
1024
1025
1026
1027 static int imx412_power_on(struct device *dev)
1028 {
1029 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1030 struct imx412 *imx412 = to_imx412(sd);
1031 int ret;
1032
1033 ret = regulator_bulk_enable(ARRAY_SIZE(imx412_supply_names),
1034 imx412->supplies);
1035 if (ret < 0) {
1036 dev_err(dev, "failed to enable regulators\n");
1037 return ret;
1038 }
1039
1040 gpiod_set_value_cansleep(imx412->reset_gpio, 0);
1041
1042 ret = clk_prepare_enable(imx412->inclk);
1043 if (ret) {
1044 dev_err(imx412->dev, "fail to enable inclk");
1045 goto error_reset;
1046 }
1047
1048 usleep_range(1000, 1200);
1049
1050 return 0;
1051
1052 error_reset:
1053 gpiod_set_value_cansleep(imx412->reset_gpio, 1);
1054 regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names),
1055 imx412->supplies);
1056
1057 return ret;
1058 }
1059
1060
1061
1062
1063
1064
1065
1066 static int imx412_power_off(struct device *dev)
1067 {
1068 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1069 struct imx412 *imx412 = to_imx412(sd);
1070
1071 clk_disable_unprepare(imx412->inclk);
1072
1073 gpiod_set_value_cansleep(imx412->reset_gpio, 1);
1074
1075 regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names),
1076 imx412->supplies);
1077
1078 return 0;
1079 }
1080
1081
1082
1083
1084
1085
1086
1087 static int imx412_init_controls(struct imx412 *imx412)
1088 {
1089 struct v4l2_ctrl_handler *ctrl_hdlr = &imx412->ctrl_handler;
1090 const struct imx412_mode *mode = imx412->cur_mode;
1091 u32 lpfr;
1092 int ret;
1093
1094 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 6);
1095 if (ret)
1096 return ret;
1097
1098
1099 ctrl_hdlr->lock = &imx412->mutex;
1100
1101
1102 lpfr = mode->vblank + mode->height;
1103 imx412->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1104 &imx412_ctrl_ops,
1105 V4L2_CID_EXPOSURE,
1106 IMX412_EXPOSURE_MIN,
1107 lpfr - IMX412_EXPOSURE_OFFSET,
1108 IMX412_EXPOSURE_STEP,
1109 IMX412_EXPOSURE_DEFAULT);
1110
1111 imx412->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1112 &imx412_ctrl_ops,
1113 V4L2_CID_ANALOGUE_GAIN,
1114 IMX412_AGAIN_MIN,
1115 IMX412_AGAIN_MAX,
1116 IMX412_AGAIN_STEP,
1117 IMX412_AGAIN_DEFAULT);
1118
1119 v4l2_ctrl_cluster(2, &imx412->exp_ctrl);
1120
1121 imx412->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1122 &imx412_ctrl_ops,
1123 V4L2_CID_VBLANK,
1124 mode->vblank_min,
1125 mode->vblank_max,
1126 1, mode->vblank);
1127
1128
1129 imx412->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1130 &imx412_ctrl_ops,
1131 V4L2_CID_PIXEL_RATE,
1132 mode->pclk, mode->pclk,
1133 1, mode->pclk);
1134
1135 imx412->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1136 &imx412_ctrl_ops,
1137 V4L2_CID_LINK_FREQ,
1138 ARRAY_SIZE(link_freq) -
1139 1,
1140 mode->link_freq_idx,
1141 link_freq);
1142 if (imx412->link_freq_ctrl)
1143 imx412->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1144
1145 imx412->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1146 &imx412_ctrl_ops,
1147 V4L2_CID_HBLANK,
1148 IMX412_REG_MIN,
1149 IMX412_REG_MAX,
1150 1, mode->hblank);
1151 if (imx412->hblank_ctrl)
1152 imx412->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1153
1154 if (ctrl_hdlr->error) {
1155 dev_err(imx412->dev, "control init failed: %d",
1156 ctrl_hdlr->error);
1157 v4l2_ctrl_handler_free(ctrl_hdlr);
1158 return ctrl_hdlr->error;
1159 }
1160
1161 imx412->sd.ctrl_handler = ctrl_hdlr;
1162
1163 return 0;
1164 }
1165
1166
1167
1168
1169
1170
1171
1172 static int imx412_probe(struct i2c_client *client)
1173 {
1174 struct imx412 *imx412;
1175 int ret;
1176
1177 imx412 = devm_kzalloc(&client->dev, sizeof(*imx412), GFP_KERNEL);
1178 if (!imx412)
1179 return -ENOMEM;
1180
1181 imx412->dev = &client->dev;
1182
1183
1184 v4l2_i2c_subdev_init(&imx412->sd, client, &imx412_subdev_ops);
1185
1186 ret = imx412_parse_hw_config(imx412);
1187 if (ret) {
1188 dev_err(imx412->dev, "HW configuration is not supported");
1189 return ret;
1190 }
1191
1192 mutex_init(&imx412->mutex);
1193
1194 ret = imx412_power_on(imx412->dev);
1195 if (ret) {
1196 dev_err(imx412->dev, "failed to power-on the sensor");
1197 goto error_mutex_destroy;
1198 }
1199
1200
1201 ret = imx412_detect(imx412);
1202 if (ret) {
1203 dev_err(imx412->dev, "failed to find sensor: %d", ret);
1204 goto error_power_off;
1205 }
1206
1207
1208 imx412->cur_mode = &supported_mode;
1209 imx412->vblank = imx412->cur_mode->vblank;
1210
1211 ret = imx412_init_controls(imx412);
1212 if (ret) {
1213 dev_err(imx412->dev, "failed to init controls: %d", ret);
1214 goto error_power_off;
1215 }
1216
1217
1218 imx412->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1219 imx412->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1220
1221
1222 imx412->pad.flags = MEDIA_PAD_FL_SOURCE;
1223 ret = media_entity_pads_init(&imx412->sd.entity, 1, &imx412->pad);
1224 if (ret) {
1225 dev_err(imx412->dev, "failed to init entity pads: %d", ret);
1226 goto error_handler_free;
1227 }
1228
1229 ret = v4l2_async_register_subdev_sensor(&imx412->sd);
1230 if (ret < 0) {
1231 dev_err(imx412->dev,
1232 "failed to register async subdev: %d", ret);
1233 goto error_media_entity;
1234 }
1235
1236 pm_runtime_set_active(imx412->dev);
1237 pm_runtime_enable(imx412->dev);
1238 pm_runtime_idle(imx412->dev);
1239
1240 return 0;
1241
1242 error_media_entity:
1243 media_entity_cleanup(&imx412->sd.entity);
1244 error_handler_free:
1245 v4l2_ctrl_handler_free(imx412->sd.ctrl_handler);
1246 error_power_off:
1247 imx412_power_off(imx412->dev);
1248 error_mutex_destroy:
1249 mutex_destroy(&imx412->mutex);
1250
1251 return ret;
1252 }
1253
1254
1255
1256
1257
1258
1259
1260 static int imx412_remove(struct i2c_client *client)
1261 {
1262 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1263 struct imx412 *imx412 = to_imx412(sd);
1264
1265 v4l2_async_unregister_subdev(sd);
1266 media_entity_cleanup(&sd->entity);
1267 v4l2_ctrl_handler_free(sd->ctrl_handler);
1268
1269 pm_runtime_disable(&client->dev);
1270 if (!pm_runtime_status_suspended(&client->dev))
1271 imx412_power_off(&client->dev);
1272 pm_runtime_set_suspended(&client->dev);
1273
1274 mutex_destroy(&imx412->mutex);
1275
1276 return 0;
1277 }
1278
1279 static const struct dev_pm_ops imx412_pm_ops = {
1280 SET_RUNTIME_PM_OPS(imx412_power_off, imx412_power_on, NULL)
1281 };
1282
1283 static const struct of_device_id imx412_of_match[] = {
1284 { .compatible = "sony,imx412" },
1285 { }
1286 };
1287
1288 MODULE_DEVICE_TABLE(of, imx412_of_match);
1289
1290 static struct i2c_driver imx412_driver = {
1291 .probe_new = imx412_probe,
1292 .remove = imx412_remove,
1293 .driver = {
1294 .name = "imx412",
1295 .pm = &imx412_pm_ops,
1296 .of_match_table = imx412_of_match,
1297 },
1298 };
1299
1300 module_i2c_driver(imx412_driver);
1301
1302 MODULE_DESCRIPTION("Sony imx412 sensor driver");
1303 MODULE_LICENSE("GPL");