0001
0002
0003
0004
0005
0006
0007 #include <asm/unaligned.h>
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/i2c.h>
0012 #include <linux/module.h>
0013 #include <linux/pm_runtime.h>
0014
0015 #include <media/v4l2-ctrls.h>
0016 #include <media/v4l2-fwnode.h>
0017 #include <media/v4l2-subdev.h>
0018
0019
0020 #define IMX334_REG_MODE_SELECT 0x3000
0021 #define IMX334_MODE_STANDBY 0x01
0022 #define IMX334_MODE_STREAMING 0x00
0023
0024
0025 #define IMX334_REG_LPFR 0x3030
0026
0027
0028 #define IMX334_REG_ID 0x3044
0029 #define IMX334_ID 0x1e
0030
0031
0032 #define IMX334_REG_SHUTTER 0x3058
0033 #define IMX334_EXPOSURE_MIN 1
0034 #define IMX334_EXPOSURE_OFFSET 5
0035 #define IMX334_EXPOSURE_STEP 1
0036 #define IMX334_EXPOSURE_DEFAULT 0x0648
0037
0038
0039 #define IMX334_REG_AGAIN 0x30e8
0040 #define IMX334_AGAIN_MIN 0
0041 #define IMX334_AGAIN_MAX 240
0042 #define IMX334_AGAIN_STEP 1
0043 #define IMX334_AGAIN_DEFAULT 0
0044
0045
0046 #define IMX334_REG_HOLD 0x3001
0047
0048
0049 #define IMX334_INCLK_RATE 24000000
0050
0051
0052 #define IMX334_LINK_FREQ 891000000
0053 #define IMX334_NUM_DATA_LANES 4
0054
0055 #define IMX334_REG_MIN 0x00
0056 #define IMX334_REG_MAX 0xfffff
0057
0058
0059
0060
0061
0062
0063 struct imx334_reg {
0064 u16 address;
0065 u8 val;
0066 };
0067
0068
0069
0070
0071
0072
0073 struct imx334_reg_list {
0074 u32 num_of_regs;
0075 const struct imx334_reg *regs;
0076 };
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091 struct imx334_mode {
0092 u32 width;
0093 u32 height;
0094 u32 code;
0095 u32 hblank;
0096 u32 vblank;
0097 u32 vblank_min;
0098 u32 vblank_max;
0099 u64 pclk;
0100 u32 link_freq_idx;
0101 struct imx334_reg_list reg_list;
0102 };
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124 struct imx334 {
0125 struct device *dev;
0126 struct i2c_client *client;
0127 struct v4l2_subdev sd;
0128 struct media_pad pad;
0129 struct gpio_desc *reset_gpio;
0130 struct clk *inclk;
0131 struct v4l2_ctrl_handler ctrl_handler;
0132 struct v4l2_ctrl *link_freq_ctrl;
0133 struct v4l2_ctrl *pclk_ctrl;
0134 struct v4l2_ctrl *hblank_ctrl;
0135 struct v4l2_ctrl *vblank_ctrl;
0136 struct {
0137 struct v4l2_ctrl *exp_ctrl;
0138 struct v4l2_ctrl *again_ctrl;
0139 };
0140 u32 vblank;
0141 const struct imx334_mode *cur_mode;
0142 struct mutex mutex;
0143 bool streaming;
0144 };
0145
0146 static const s64 link_freq[] = {
0147 IMX334_LINK_FREQ,
0148 };
0149
0150
0151 static const struct imx334_reg mode_3840x2160_regs[] = {
0152 {0x3000, 0x01},
0153 {0x3002, 0x00},
0154 {0x3018, 0x04},
0155 {0x37b0, 0x36},
0156 {0x304c, 0x00},
0157 {0x300c, 0x3b},
0158 {0x300d, 0x2a},
0159 {0x3034, 0x26},
0160 {0x3035, 0x02},
0161 {0x314c, 0x29},
0162 {0x314d, 0x01},
0163 {0x315a, 0x02},
0164 {0x3168, 0xa0},
0165 {0x316a, 0x7e},
0166 {0x3288, 0x21},
0167 {0x328a, 0x02},
0168 {0x302c, 0x3c},
0169 {0x302e, 0x00},
0170 {0x302f, 0x0f},
0171 {0x3076, 0x70},
0172 {0x3077, 0x08},
0173 {0x3090, 0x70},
0174 {0x3091, 0x08},
0175 {0x30d8, 0x20},
0176 {0x30d9, 0x12},
0177 {0x3308, 0x70},
0178 {0x3309, 0x08},
0179 {0x3414, 0x05},
0180 {0x3416, 0x18},
0181 {0x35ac, 0x0e},
0182 {0x3648, 0x01},
0183 {0x364a, 0x04},
0184 {0x364c, 0x04},
0185 {0x3678, 0x01},
0186 {0x367c, 0x31},
0187 {0x367e, 0x31},
0188 {0x3708, 0x02},
0189 {0x3714, 0x01},
0190 {0x3715, 0x02},
0191 {0x3716, 0x02},
0192 {0x3717, 0x02},
0193 {0x371c, 0x3d},
0194 {0x371d, 0x3f},
0195 {0x372c, 0x00},
0196 {0x372d, 0x00},
0197 {0x372e, 0x46},
0198 {0x372f, 0x00},
0199 {0x3730, 0x89},
0200 {0x3731, 0x00},
0201 {0x3732, 0x08},
0202 {0x3733, 0x01},
0203 {0x3734, 0xfe},
0204 {0x3735, 0x05},
0205 {0x375d, 0x00},
0206 {0x375e, 0x00},
0207 {0x375f, 0x61},
0208 {0x3760, 0x06},
0209 {0x3768, 0x1b},
0210 {0x3769, 0x1b},
0211 {0x376a, 0x1a},
0212 {0x376b, 0x19},
0213 {0x376c, 0x18},
0214 {0x376d, 0x14},
0215 {0x376e, 0x0f},
0216 {0x3776, 0x00},
0217 {0x3777, 0x00},
0218 {0x3778, 0x46},
0219 {0x3779, 0x00},
0220 {0x377a, 0x08},
0221 {0x377b, 0x01},
0222 {0x377c, 0x45},
0223 {0x377d, 0x01},
0224 {0x377e, 0x23},
0225 {0x377f, 0x02},
0226 {0x3780, 0xd9},
0227 {0x3781, 0x03},
0228 {0x3782, 0xf5},
0229 {0x3783, 0x06},
0230 {0x3784, 0xa5},
0231 {0x3788, 0x0f},
0232 {0x378a, 0xd9},
0233 {0x378b, 0x03},
0234 {0x378c, 0xeb},
0235 {0x378d, 0x05},
0236 {0x378e, 0x87},
0237 {0x378f, 0x06},
0238 {0x3790, 0xf5},
0239 {0x3792, 0x43},
0240 {0x3794, 0x7a},
0241 {0x3796, 0xa1},
0242 {0x3e04, 0x0e},
0243 {0x3a00, 0x01},
0244 };
0245
0246
0247 static const struct imx334_mode supported_mode = {
0248 .width = 3840,
0249 .height = 2160,
0250 .hblank = 560,
0251 .vblank = 2340,
0252 .vblank_min = 90,
0253 .vblank_max = 132840,
0254 .pclk = 594000000,
0255 .link_freq_idx = 0,
0256 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
0257 .reg_list = {
0258 .num_of_regs = ARRAY_SIZE(mode_3840x2160_regs),
0259 .regs = mode_3840x2160_regs,
0260 },
0261 };
0262
0263
0264
0265
0266
0267
0268
0269 static inline struct imx334 *to_imx334(struct v4l2_subdev *subdev)
0270 {
0271 return container_of(subdev, struct imx334, sd);
0272 }
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285 static int imx334_read_reg(struct imx334 *imx334, u16 reg, u32 len, u32 *val)
0286 {
0287 struct i2c_client *client = v4l2_get_subdevdata(&imx334->sd);
0288 struct i2c_msg msgs[2] = {0};
0289 u8 addr_buf[2] = {0};
0290 u8 data_buf[4] = {0};
0291 int ret;
0292
0293 if (WARN_ON(len > 4))
0294 return -EINVAL;
0295
0296 put_unaligned_be16(reg, addr_buf);
0297
0298
0299 msgs[0].addr = client->addr;
0300 msgs[0].flags = 0;
0301 msgs[0].len = ARRAY_SIZE(addr_buf);
0302 msgs[0].buf = addr_buf;
0303
0304
0305 msgs[1].addr = client->addr;
0306 msgs[1].flags = I2C_M_RD;
0307 msgs[1].len = len;
0308 msgs[1].buf = data_buf;
0309
0310 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0311 if (ret != ARRAY_SIZE(msgs))
0312 return -EIO;
0313
0314 *val = get_unaligned_le32(data_buf);
0315
0316 return 0;
0317 }
0318
0319
0320
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330 static int imx334_write_reg(struct imx334 *imx334, u16 reg, u32 len, u32 val)
0331 {
0332 struct i2c_client *client = v4l2_get_subdevdata(&imx334->sd);
0333 u8 buf[6] = {0};
0334
0335 if (WARN_ON(len > 4))
0336 return -EINVAL;
0337
0338 put_unaligned_be16(reg, buf);
0339 put_unaligned_le32(val, buf + 2);
0340 if (i2c_master_send(client, buf, len + 2) != len + 2)
0341 return -EIO;
0342
0343 return 0;
0344 }
0345
0346
0347
0348
0349
0350
0351
0352
0353
0354 static int imx334_write_regs(struct imx334 *imx334,
0355 const struct imx334_reg *regs, u32 len)
0356 {
0357 unsigned int i;
0358 int ret;
0359
0360 for (i = 0; i < len; i++) {
0361 ret = imx334_write_reg(imx334, regs[i].address, 1, regs[i].val);
0362 if (ret)
0363 return ret;
0364 }
0365
0366 return 0;
0367 }
0368
0369
0370
0371
0372
0373
0374
0375
0376 static int imx334_update_controls(struct imx334 *imx334,
0377 const struct imx334_mode *mode)
0378 {
0379 int ret;
0380
0381 ret = __v4l2_ctrl_s_ctrl(imx334->link_freq_ctrl, mode->link_freq_idx);
0382 if (ret)
0383 return ret;
0384
0385 ret = __v4l2_ctrl_s_ctrl(imx334->hblank_ctrl, mode->hblank);
0386 if (ret)
0387 return ret;
0388
0389 return __v4l2_ctrl_modify_range(imx334->vblank_ctrl, mode->vblank_min,
0390 mode->vblank_max, 1, mode->vblank);
0391 }
0392
0393
0394
0395
0396
0397
0398
0399
0400
0401 static int imx334_update_exp_gain(struct imx334 *imx334, u32 exposure, u32 gain)
0402 {
0403 u32 lpfr, shutter;
0404 int ret;
0405
0406 lpfr = imx334->vblank + imx334->cur_mode->height;
0407 shutter = lpfr - exposure;
0408
0409 dev_dbg(imx334->dev, "Set long exp %u analog gain %u sh0 %u lpfr %u",
0410 exposure, gain, shutter, lpfr);
0411
0412 ret = imx334_write_reg(imx334, IMX334_REG_HOLD, 1, 1);
0413 if (ret)
0414 return ret;
0415
0416 ret = imx334_write_reg(imx334, IMX334_REG_LPFR, 3, lpfr);
0417 if (ret)
0418 goto error_release_group_hold;
0419
0420 ret = imx334_write_reg(imx334, IMX334_REG_SHUTTER, 3, shutter);
0421 if (ret)
0422 goto error_release_group_hold;
0423
0424 ret = imx334_write_reg(imx334, IMX334_REG_AGAIN, 1, gain);
0425
0426 error_release_group_hold:
0427 imx334_write_reg(imx334, IMX334_REG_HOLD, 1, 0);
0428
0429 return ret;
0430 }
0431
0432
0433
0434
0435
0436
0437
0438
0439
0440
0441
0442
0443
0444 static int imx334_set_ctrl(struct v4l2_ctrl *ctrl)
0445 {
0446 struct imx334 *imx334 =
0447 container_of(ctrl->handler, struct imx334, ctrl_handler);
0448 u32 analog_gain;
0449 u32 exposure;
0450 int ret;
0451
0452 switch (ctrl->id) {
0453 case V4L2_CID_VBLANK:
0454 imx334->vblank = imx334->vblank_ctrl->val;
0455
0456 dev_dbg(imx334->dev, "Received vblank %u, new lpfr %u",
0457 imx334->vblank,
0458 imx334->vblank + imx334->cur_mode->height);
0459
0460 ret = __v4l2_ctrl_modify_range(imx334->exp_ctrl,
0461 IMX334_EXPOSURE_MIN,
0462 imx334->vblank +
0463 imx334->cur_mode->height -
0464 IMX334_EXPOSURE_OFFSET,
0465 1, IMX334_EXPOSURE_DEFAULT);
0466 break;
0467 case V4L2_CID_EXPOSURE:
0468
0469
0470 if (!pm_runtime_get_if_in_use(imx334->dev))
0471 return 0;
0472
0473 exposure = ctrl->val;
0474 analog_gain = imx334->again_ctrl->val;
0475
0476 dev_dbg(imx334->dev, "Received exp %u analog gain %u",
0477 exposure, analog_gain);
0478
0479 ret = imx334_update_exp_gain(imx334, exposure, analog_gain);
0480
0481 pm_runtime_put(imx334->dev);
0482
0483 break;
0484 default:
0485 dev_err(imx334->dev, "Invalid control %d", ctrl->id);
0486 ret = -EINVAL;
0487 }
0488
0489 return ret;
0490 }
0491
0492
0493 static const struct v4l2_ctrl_ops imx334_ctrl_ops = {
0494 .s_ctrl = imx334_set_ctrl,
0495 };
0496
0497
0498
0499
0500
0501
0502
0503
0504
0505 static int imx334_enum_mbus_code(struct v4l2_subdev *sd,
0506 struct v4l2_subdev_state *sd_state,
0507 struct v4l2_subdev_mbus_code_enum *code)
0508 {
0509 if (code->index > 0)
0510 return -EINVAL;
0511
0512 code->code = supported_mode.code;
0513
0514 return 0;
0515 }
0516
0517
0518
0519
0520
0521
0522
0523
0524
0525 static int imx334_enum_frame_size(struct v4l2_subdev *sd,
0526 struct v4l2_subdev_state *sd_state,
0527 struct v4l2_subdev_frame_size_enum *fsize)
0528 {
0529 if (fsize->index > 0)
0530 return -EINVAL;
0531
0532 if (fsize->code != supported_mode.code)
0533 return -EINVAL;
0534
0535 fsize->min_width = supported_mode.width;
0536 fsize->max_width = fsize->min_width;
0537 fsize->min_height = supported_mode.height;
0538 fsize->max_height = fsize->min_height;
0539
0540 return 0;
0541 }
0542
0543
0544
0545
0546
0547
0548
0549
0550 static void imx334_fill_pad_format(struct imx334 *imx334,
0551 const struct imx334_mode *mode,
0552 struct v4l2_subdev_format *fmt)
0553 {
0554 fmt->format.width = mode->width;
0555 fmt->format.height = mode->height;
0556 fmt->format.code = mode->code;
0557 fmt->format.field = V4L2_FIELD_NONE;
0558 fmt->format.colorspace = V4L2_COLORSPACE_RAW;
0559 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
0560 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT;
0561 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
0562 }
0563
0564
0565
0566
0567
0568
0569
0570
0571
0572 static int imx334_get_pad_format(struct v4l2_subdev *sd,
0573 struct v4l2_subdev_state *sd_state,
0574 struct v4l2_subdev_format *fmt)
0575 {
0576 struct imx334 *imx334 = to_imx334(sd);
0577
0578 mutex_lock(&imx334->mutex);
0579
0580 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0581 struct v4l2_mbus_framefmt *framefmt;
0582
0583 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0584 fmt->format = *framefmt;
0585 } else {
0586 imx334_fill_pad_format(imx334, imx334->cur_mode, fmt);
0587 }
0588
0589 mutex_unlock(&imx334->mutex);
0590
0591 return 0;
0592 }
0593
0594
0595
0596
0597
0598
0599
0600
0601
0602 static int imx334_set_pad_format(struct v4l2_subdev *sd,
0603 struct v4l2_subdev_state *sd_state,
0604 struct v4l2_subdev_format *fmt)
0605 {
0606 struct imx334 *imx334 = to_imx334(sd);
0607 const struct imx334_mode *mode;
0608 int ret = 0;
0609
0610 mutex_lock(&imx334->mutex);
0611
0612 mode = &supported_mode;
0613 imx334_fill_pad_format(imx334, mode, fmt);
0614
0615 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0616 struct v4l2_mbus_framefmt *framefmt;
0617
0618 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0619 *framefmt = fmt->format;
0620 } else {
0621 ret = imx334_update_controls(imx334, mode);
0622 if (!ret)
0623 imx334->cur_mode = mode;
0624 }
0625
0626 mutex_unlock(&imx334->mutex);
0627
0628 return ret;
0629 }
0630
0631
0632
0633
0634
0635
0636
0637
0638 static int imx334_init_pad_cfg(struct v4l2_subdev *sd,
0639 struct v4l2_subdev_state *sd_state)
0640 {
0641 struct imx334 *imx334 = to_imx334(sd);
0642 struct v4l2_subdev_format fmt = { 0 };
0643
0644 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
0645 imx334_fill_pad_format(imx334, &supported_mode, &fmt);
0646
0647 return imx334_set_pad_format(sd, sd_state, &fmt);
0648 }
0649
0650
0651
0652
0653
0654
0655
0656 static int imx334_start_streaming(struct imx334 *imx334)
0657 {
0658 const struct imx334_reg_list *reg_list;
0659 int ret;
0660
0661
0662 reg_list = &imx334->cur_mode->reg_list;
0663 ret = imx334_write_regs(imx334, reg_list->regs,
0664 reg_list->num_of_regs);
0665 if (ret) {
0666 dev_err(imx334->dev, "fail to write initial registers");
0667 return ret;
0668 }
0669
0670
0671 ret = __v4l2_ctrl_handler_setup(imx334->sd.ctrl_handler);
0672 if (ret) {
0673 dev_err(imx334->dev, "fail to setup handler");
0674 return ret;
0675 }
0676
0677
0678 ret = imx334_write_reg(imx334, IMX334_REG_MODE_SELECT,
0679 1, IMX334_MODE_STREAMING);
0680 if (ret) {
0681 dev_err(imx334->dev, "fail to start streaming");
0682 return ret;
0683 }
0684
0685 return 0;
0686 }
0687
0688
0689
0690
0691
0692
0693
0694 static int imx334_stop_streaming(struct imx334 *imx334)
0695 {
0696 return imx334_write_reg(imx334, IMX334_REG_MODE_SELECT,
0697 1, IMX334_MODE_STANDBY);
0698 }
0699
0700
0701
0702
0703
0704
0705
0706
0707 static int imx334_set_stream(struct v4l2_subdev *sd, int enable)
0708 {
0709 struct imx334 *imx334 = to_imx334(sd);
0710 int ret;
0711
0712 mutex_lock(&imx334->mutex);
0713
0714 if (imx334->streaming == enable) {
0715 mutex_unlock(&imx334->mutex);
0716 return 0;
0717 }
0718
0719 if (enable) {
0720 ret = pm_runtime_resume_and_get(imx334->dev);
0721 if (ret < 0)
0722 goto error_unlock;
0723
0724 ret = imx334_start_streaming(imx334);
0725 if (ret)
0726 goto error_power_off;
0727 } else {
0728 imx334_stop_streaming(imx334);
0729 pm_runtime_put(imx334->dev);
0730 }
0731
0732 imx334->streaming = enable;
0733
0734 mutex_unlock(&imx334->mutex);
0735
0736 return 0;
0737
0738 error_power_off:
0739 pm_runtime_put(imx334->dev);
0740 error_unlock:
0741 mutex_unlock(&imx334->mutex);
0742
0743 return ret;
0744 }
0745
0746
0747
0748
0749
0750
0751
0752 static int imx334_detect(struct imx334 *imx334)
0753 {
0754 int ret;
0755 u32 val;
0756
0757 ret = imx334_read_reg(imx334, IMX334_REG_ID, 2, &val);
0758 if (ret)
0759 return ret;
0760
0761 if (val != IMX334_ID) {
0762 dev_err(imx334->dev, "chip id mismatch: %x!=%x",
0763 IMX334_ID, val);
0764 return -ENXIO;
0765 }
0766
0767 return 0;
0768 }
0769
0770
0771
0772
0773
0774
0775
0776 static int imx334_parse_hw_config(struct imx334 *imx334)
0777 {
0778 struct fwnode_handle *fwnode = dev_fwnode(imx334->dev);
0779 struct v4l2_fwnode_endpoint bus_cfg = {
0780 .bus_type = V4L2_MBUS_CSI2_DPHY
0781 };
0782 struct fwnode_handle *ep;
0783 unsigned long rate;
0784 int ret;
0785 int i;
0786
0787 if (!fwnode)
0788 return -ENXIO;
0789
0790
0791 imx334->reset_gpio = devm_gpiod_get_optional(imx334->dev, "reset",
0792 GPIOD_OUT_LOW);
0793 if (IS_ERR(imx334->reset_gpio)) {
0794 dev_err(imx334->dev, "failed to get reset gpio %ld",
0795 PTR_ERR(imx334->reset_gpio));
0796 return PTR_ERR(imx334->reset_gpio);
0797 }
0798
0799
0800 imx334->inclk = devm_clk_get(imx334->dev, NULL);
0801 if (IS_ERR(imx334->inclk)) {
0802 dev_err(imx334->dev, "could not get inclk");
0803 return PTR_ERR(imx334->inclk);
0804 }
0805
0806 rate = clk_get_rate(imx334->inclk);
0807 if (rate != IMX334_INCLK_RATE) {
0808 dev_err(imx334->dev, "inclk frequency mismatch");
0809 return -EINVAL;
0810 }
0811
0812 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
0813 if (!ep)
0814 return -ENXIO;
0815
0816 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
0817 fwnode_handle_put(ep);
0818 if (ret)
0819 return ret;
0820
0821 if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX334_NUM_DATA_LANES) {
0822 dev_err(imx334->dev,
0823 "number of CSI2 data lanes %d is not supported",
0824 bus_cfg.bus.mipi_csi2.num_data_lanes);
0825 ret = -EINVAL;
0826 goto done_endpoint_free;
0827 }
0828
0829 if (!bus_cfg.nr_of_link_frequencies) {
0830 dev_err(imx334->dev, "no link frequencies defined");
0831 ret = -EINVAL;
0832 goto done_endpoint_free;
0833 }
0834
0835 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++)
0836 if (bus_cfg.link_frequencies[i] == IMX334_LINK_FREQ)
0837 goto done_endpoint_free;
0838
0839 ret = -EINVAL;
0840
0841 done_endpoint_free:
0842 v4l2_fwnode_endpoint_free(&bus_cfg);
0843
0844 return ret;
0845 }
0846
0847
0848 static const struct v4l2_subdev_video_ops imx334_video_ops = {
0849 .s_stream = imx334_set_stream,
0850 };
0851
0852 static const struct v4l2_subdev_pad_ops imx334_pad_ops = {
0853 .init_cfg = imx334_init_pad_cfg,
0854 .enum_mbus_code = imx334_enum_mbus_code,
0855 .enum_frame_size = imx334_enum_frame_size,
0856 .get_fmt = imx334_get_pad_format,
0857 .set_fmt = imx334_set_pad_format,
0858 };
0859
0860 static const struct v4l2_subdev_ops imx334_subdev_ops = {
0861 .video = &imx334_video_ops,
0862 .pad = &imx334_pad_ops,
0863 };
0864
0865
0866
0867
0868
0869
0870
0871 static int imx334_power_on(struct device *dev)
0872 {
0873 struct v4l2_subdev *sd = dev_get_drvdata(dev);
0874 struct imx334 *imx334 = to_imx334(sd);
0875 int ret;
0876
0877 gpiod_set_value_cansleep(imx334->reset_gpio, 1);
0878
0879 ret = clk_prepare_enable(imx334->inclk);
0880 if (ret) {
0881 dev_err(imx334->dev, "fail to enable inclk");
0882 goto error_reset;
0883 }
0884
0885 usleep_range(18000, 20000);
0886
0887 return 0;
0888
0889 error_reset:
0890 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
0891
0892 return ret;
0893 }
0894
0895
0896
0897
0898
0899
0900
0901 static int imx334_power_off(struct device *dev)
0902 {
0903 struct v4l2_subdev *sd = dev_get_drvdata(dev);
0904 struct imx334 *imx334 = to_imx334(sd);
0905
0906 gpiod_set_value_cansleep(imx334->reset_gpio, 0);
0907
0908 clk_disable_unprepare(imx334->inclk);
0909
0910 return 0;
0911 }
0912
0913
0914
0915
0916
0917
0918
0919 static int imx334_init_controls(struct imx334 *imx334)
0920 {
0921 struct v4l2_ctrl_handler *ctrl_hdlr = &imx334->ctrl_handler;
0922 const struct imx334_mode *mode = imx334->cur_mode;
0923 u32 lpfr;
0924 int ret;
0925
0926 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 6);
0927 if (ret)
0928 return ret;
0929
0930
0931 ctrl_hdlr->lock = &imx334->mutex;
0932
0933
0934 lpfr = mode->vblank + mode->height;
0935 imx334->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0936 &imx334_ctrl_ops,
0937 V4L2_CID_EXPOSURE,
0938 IMX334_EXPOSURE_MIN,
0939 lpfr - IMX334_EXPOSURE_OFFSET,
0940 IMX334_EXPOSURE_STEP,
0941 IMX334_EXPOSURE_DEFAULT);
0942
0943 imx334->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0944 &imx334_ctrl_ops,
0945 V4L2_CID_ANALOGUE_GAIN,
0946 IMX334_AGAIN_MIN,
0947 IMX334_AGAIN_MAX,
0948 IMX334_AGAIN_STEP,
0949 IMX334_AGAIN_DEFAULT);
0950
0951 v4l2_ctrl_cluster(2, &imx334->exp_ctrl);
0952
0953 imx334->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0954 &imx334_ctrl_ops,
0955 V4L2_CID_VBLANK,
0956 mode->vblank_min,
0957 mode->vblank_max,
0958 1, mode->vblank);
0959
0960
0961 imx334->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0962 &imx334_ctrl_ops,
0963 V4L2_CID_PIXEL_RATE,
0964 mode->pclk, mode->pclk,
0965 1, mode->pclk);
0966
0967 imx334->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr,
0968 &imx334_ctrl_ops,
0969 V4L2_CID_LINK_FREQ,
0970 ARRAY_SIZE(link_freq) -
0971 1,
0972 mode->link_freq_idx,
0973 link_freq);
0974 if (imx334->link_freq_ctrl)
0975 imx334->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0976
0977 imx334->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
0978 &imx334_ctrl_ops,
0979 V4L2_CID_HBLANK,
0980 IMX334_REG_MIN,
0981 IMX334_REG_MAX,
0982 1, mode->hblank);
0983 if (imx334->hblank_ctrl)
0984 imx334->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
0985
0986 if (ctrl_hdlr->error) {
0987 dev_err(imx334->dev, "control init failed: %d",
0988 ctrl_hdlr->error);
0989 v4l2_ctrl_handler_free(ctrl_hdlr);
0990 return ctrl_hdlr->error;
0991 }
0992
0993 imx334->sd.ctrl_handler = ctrl_hdlr;
0994
0995 return 0;
0996 }
0997
0998
0999
1000
1001
1002
1003
1004 static int imx334_probe(struct i2c_client *client)
1005 {
1006 struct imx334 *imx334;
1007 int ret;
1008
1009 imx334 = devm_kzalloc(&client->dev, sizeof(*imx334), GFP_KERNEL);
1010 if (!imx334)
1011 return -ENOMEM;
1012
1013 imx334->dev = &client->dev;
1014
1015
1016 v4l2_i2c_subdev_init(&imx334->sd, client, &imx334_subdev_ops);
1017
1018 ret = imx334_parse_hw_config(imx334);
1019 if (ret) {
1020 dev_err(imx334->dev, "HW configuration is not supported");
1021 return ret;
1022 }
1023
1024 mutex_init(&imx334->mutex);
1025
1026 ret = imx334_power_on(imx334->dev);
1027 if (ret) {
1028 dev_err(imx334->dev, "failed to power-on the sensor");
1029 goto error_mutex_destroy;
1030 }
1031
1032
1033 ret = imx334_detect(imx334);
1034 if (ret) {
1035 dev_err(imx334->dev, "failed to find sensor: %d", ret);
1036 goto error_power_off;
1037 }
1038
1039
1040 imx334->cur_mode = &supported_mode;
1041 imx334->vblank = imx334->cur_mode->vblank;
1042
1043 ret = imx334_init_controls(imx334);
1044 if (ret) {
1045 dev_err(imx334->dev, "failed to init controls: %d", ret);
1046 goto error_power_off;
1047 }
1048
1049
1050 imx334->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1051 imx334->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1052
1053
1054 imx334->pad.flags = MEDIA_PAD_FL_SOURCE;
1055 ret = media_entity_pads_init(&imx334->sd.entity, 1, &imx334->pad);
1056 if (ret) {
1057 dev_err(imx334->dev, "failed to init entity pads: %d", ret);
1058 goto error_handler_free;
1059 }
1060
1061 ret = v4l2_async_register_subdev_sensor(&imx334->sd);
1062 if (ret < 0) {
1063 dev_err(imx334->dev,
1064 "failed to register async subdev: %d", ret);
1065 goto error_media_entity;
1066 }
1067
1068 pm_runtime_set_active(imx334->dev);
1069 pm_runtime_enable(imx334->dev);
1070 pm_runtime_idle(imx334->dev);
1071
1072 return 0;
1073
1074 error_media_entity:
1075 media_entity_cleanup(&imx334->sd.entity);
1076 error_handler_free:
1077 v4l2_ctrl_handler_free(imx334->sd.ctrl_handler);
1078 error_power_off:
1079 imx334_power_off(imx334->dev);
1080 error_mutex_destroy:
1081 mutex_destroy(&imx334->mutex);
1082
1083 return ret;
1084 }
1085
1086
1087
1088
1089
1090
1091
1092 static int imx334_remove(struct i2c_client *client)
1093 {
1094 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1095 struct imx334 *imx334 = to_imx334(sd);
1096
1097 v4l2_async_unregister_subdev(sd);
1098 media_entity_cleanup(&sd->entity);
1099 v4l2_ctrl_handler_free(sd->ctrl_handler);
1100
1101 pm_runtime_disable(&client->dev);
1102 pm_runtime_suspended(&client->dev);
1103
1104 mutex_destroy(&imx334->mutex);
1105
1106 return 0;
1107 }
1108
1109 static const struct dev_pm_ops imx334_pm_ops = {
1110 SET_RUNTIME_PM_OPS(imx334_power_off, imx334_power_on, NULL)
1111 };
1112
1113 static const struct of_device_id imx334_of_match[] = {
1114 { .compatible = "sony,imx334" },
1115 { }
1116 };
1117
1118 MODULE_DEVICE_TABLE(of, imx334_of_match);
1119
1120 static struct i2c_driver imx334_driver = {
1121 .probe_new = imx334_probe,
1122 .remove = imx334_remove,
1123 .driver = {
1124 .name = "imx334",
1125 .pm = &imx334_pm_ops,
1126 .of_match_table = imx334_of_match,
1127 },
1128 };
1129
1130 module_i2c_driver(imx334_driver);
1131
1132 MODULE_DESCRIPTION("Sony imx334 sensor driver");
1133 MODULE_LICENSE("GPL");