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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Sony IMX290 CMOS Image Sensor Driver
0004  *
0005  * Copyright (C) 2019 FRAMOS GmbH.
0006  *
0007  * Copyright (C) 2019 Linaro Ltd.
0008  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0009  */
0010 
0011 #include <linux/clk.h>
0012 #include <linux/delay.h>
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/i2c.h>
0015 #include <linux/module.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/regmap.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <media/media-entity.h>
0020 #include <media/v4l2-ctrls.h>
0021 #include <media/v4l2-device.h>
0022 #include <media/v4l2-fwnode.h>
0023 #include <media/v4l2-subdev.h>
0024 
0025 #define IMX290_STANDBY 0x3000
0026 #define IMX290_REGHOLD 0x3001
0027 #define IMX290_XMSTA 0x3002
0028 #define IMX290_FR_FDG_SEL 0x3009
0029 #define IMX290_BLKLEVEL_LOW 0x300a
0030 #define IMX290_BLKLEVEL_HIGH 0x300b
0031 #define IMX290_GAIN 0x3014
0032 #define IMX290_HMAX_LOW 0x301c
0033 #define IMX290_HMAX_HIGH 0x301d
0034 #define IMX290_PGCTRL 0x308c
0035 #define IMX290_PHY_LANE_NUM 0x3407
0036 #define IMX290_CSI_LANE_MODE 0x3443
0037 
0038 #define IMX290_PGCTRL_REGEN BIT(0)
0039 #define IMX290_PGCTRL_THRU BIT(1)
0040 #define IMX290_PGCTRL_MODE(n) ((n) << 4)
0041 
0042 static const char * const imx290_supply_name[] = {
0043     "vdda",
0044     "vddd",
0045     "vdddo",
0046 };
0047 
0048 #define IMX290_NUM_SUPPLIES ARRAY_SIZE(imx290_supply_name)
0049 
0050 struct imx290_regval {
0051     u16 reg;
0052     u8 val;
0053 };
0054 
0055 struct imx290_mode {
0056     u32 width;
0057     u32 height;
0058     u32 hmax;
0059     u8 link_freq_index;
0060 
0061     const struct imx290_regval *data;
0062     u32 data_size;
0063 };
0064 
0065 struct imx290 {
0066     struct device *dev;
0067     struct clk *xclk;
0068     struct regmap *regmap;
0069     u8 nlanes;
0070     u8 bpp;
0071 
0072     struct v4l2_subdev sd;
0073     struct media_pad pad;
0074     struct v4l2_mbus_framefmt current_format;
0075     const struct imx290_mode *current_mode;
0076 
0077     struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES];
0078     struct gpio_desc *rst_gpio;
0079 
0080     struct v4l2_ctrl_handler ctrls;
0081     struct v4l2_ctrl *link_freq;
0082     struct v4l2_ctrl *pixel_rate;
0083 
0084     struct mutex lock;
0085 };
0086 
0087 struct imx290_pixfmt {
0088     u32 code;
0089     u8 bpp;
0090 };
0091 
0092 static const struct imx290_pixfmt imx290_formats[] = {
0093     { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
0094     { MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
0095 };
0096 
0097 static const struct regmap_config imx290_regmap_config = {
0098     .reg_bits = 16,
0099     .val_bits = 8,
0100     .cache_type = REGCACHE_RBTREE,
0101 };
0102 
0103 static const char * const imx290_test_pattern_menu[] = {
0104     "Disabled",
0105     "Sequence Pattern 1",
0106     "Horizontal Color-bar Chart",
0107     "Vertical Color-bar Chart",
0108     "Sequence Pattern 2",
0109     "Gradation Pattern 1",
0110     "Gradation Pattern 2",
0111     "000/555h Toggle Pattern",
0112 };
0113 
0114 static const struct imx290_regval imx290_global_init_settings[] = {
0115     { 0x3007, 0x00 },
0116     { 0x3018, 0x65 },
0117     { 0x3019, 0x04 },
0118     { 0x301a, 0x00 },
0119     { 0x3444, 0x20 },
0120     { 0x3445, 0x25 },
0121     { 0x303a, 0x0c },
0122     { 0x3040, 0x00 },
0123     { 0x3041, 0x00 },
0124     { 0x303c, 0x00 },
0125     { 0x303d, 0x00 },
0126     { 0x3042, 0x9c },
0127     { 0x3043, 0x07 },
0128     { 0x303e, 0x49 },
0129     { 0x303f, 0x04 },
0130     { 0x304b, 0x0a },
0131     { 0x300f, 0x00 },
0132     { 0x3010, 0x21 },
0133     { 0x3012, 0x64 },
0134     { 0x3016, 0x09 },
0135     { 0x3070, 0x02 },
0136     { 0x3071, 0x11 },
0137     { 0x309b, 0x10 },
0138     { 0x309c, 0x22 },
0139     { 0x30a2, 0x02 },
0140     { 0x30a6, 0x20 },
0141     { 0x30a8, 0x20 },
0142     { 0x30aa, 0x20 },
0143     { 0x30ac, 0x20 },
0144     { 0x30b0, 0x43 },
0145     { 0x3119, 0x9e },
0146     { 0x311c, 0x1e },
0147     { 0x311e, 0x08 },
0148     { 0x3128, 0x05 },
0149     { 0x313d, 0x83 },
0150     { 0x3150, 0x03 },
0151     { 0x317e, 0x00 },
0152     { 0x32b8, 0x50 },
0153     { 0x32b9, 0x10 },
0154     { 0x32ba, 0x00 },
0155     { 0x32bb, 0x04 },
0156     { 0x32c8, 0x50 },
0157     { 0x32c9, 0x10 },
0158     { 0x32ca, 0x00 },
0159     { 0x32cb, 0x04 },
0160     { 0x332c, 0xd3 },
0161     { 0x332d, 0x10 },
0162     { 0x332e, 0x0d },
0163     { 0x3358, 0x06 },
0164     { 0x3359, 0xe1 },
0165     { 0x335a, 0x11 },
0166     { 0x3360, 0x1e },
0167     { 0x3361, 0x61 },
0168     { 0x3362, 0x10 },
0169     { 0x33b0, 0x50 },
0170     { 0x33b2, 0x1a },
0171     { 0x33b3, 0x04 },
0172 };
0173 
0174 static const struct imx290_regval imx290_1080p_settings[] = {
0175     /* mode settings */
0176     { 0x3007, 0x00 },
0177     { 0x303a, 0x0c },
0178     { 0x3414, 0x0a },
0179     { 0x3472, 0x80 },
0180     { 0x3473, 0x07 },
0181     { 0x3418, 0x38 },
0182     { 0x3419, 0x04 },
0183     { 0x3012, 0x64 },
0184     { 0x3013, 0x00 },
0185     { 0x305c, 0x18 },
0186     { 0x305d, 0x03 },
0187     { 0x305e, 0x20 },
0188     { 0x305f, 0x01 },
0189     { 0x315e, 0x1a },
0190     { 0x3164, 0x1a },
0191     { 0x3480, 0x49 },
0192     /* data rate settings */
0193     { 0x3405, 0x10 },
0194     { 0x3446, 0x57 },
0195     { 0x3447, 0x00 },
0196     { 0x3448, 0x37 },
0197     { 0x3449, 0x00 },
0198     { 0x344a, 0x1f },
0199     { 0x344b, 0x00 },
0200     { 0x344c, 0x1f },
0201     { 0x344d, 0x00 },
0202     { 0x344e, 0x1f },
0203     { 0x344f, 0x00 },
0204     { 0x3450, 0x77 },
0205     { 0x3451, 0x00 },
0206     { 0x3452, 0x1f },
0207     { 0x3453, 0x00 },
0208     { 0x3454, 0x17 },
0209     { 0x3455, 0x00 },
0210 };
0211 
0212 static const struct imx290_regval imx290_720p_settings[] = {
0213     /* mode settings */
0214     { 0x3007, 0x10 },
0215     { 0x303a, 0x06 },
0216     { 0x3414, 0x04 },
0217     { 0x3472, 0x00 },
0218     { 0x3473, 0x05 },
0219     { 0x3418, 0xd0 },
0220     { 0x3419, 0x02 },
0221     { 0x3012, 0x64 },
0222     { 0x3013, 0x00 },
0223     { 0x305c, 0x20 },
0224     { 0x305d, 0x00 },
0225     { 0x305e, 0x20 },
0226     { 0x305f, 0x01 },
0227     { 0x315e, 0x1a },
0228     { 0x3164, 0x1a },
0229     { 0x3480, 0x49 },
0230     /* data rate settings */
0231     { 0x3405, 0x10 },
0232     { 0x3446, 0x4f },
0233     { 0x3447, 0x00 },
0234     { 0x3448, 0x2f },
0235     { 0x3449, 0x00 },
0236     { 0x344a, 0x17 },
0237     { 0x344b, 0x00 },
0238     { 0x344c, 0x17 },
0239     { 0x344d, 0x00 },
0240     { 0x344e, 0x17 },
0241     { 0x344f, 0x00 },
0242     { 0x3450, 0x57 },
0243     { 0x3451, 0x00 },
0244     { 0x3452, 0x17 },
0245     { 0x3453, 0x00 },
0246     { 0x3454, 0x17 },
0247     { 0x3455, 0x00 },
0248 };
0249 
0250 static const struct imx290_regval imx290_10bit_settings[] = {
0251     { 0x3005, 0x00},
0252     { 0x3046, 0x00},
0253     { 0x3129, 0x1d},
0254     { 0x317c, 0x12},
0255     { 0x31ec, 0x37},
0256     { 0x3441, 0x0a},
0257     { 0x3442, 0x0a},
0258     { 0x300a, 0x3c},
0259     { 0x300b, 0x00},
0260 };
0261 
0262 static const struct imx290_regval imx290_12bit_settings[] = {
0263     { 0x3005, 0x01 },
0264     { 0x3046, 0x01 },
0265     { 0x3129, 0x00 },
0266     { 0x317c, 0x00 },
0267     { 0x31ec, 0x0e },
0268     { 0x3441, 0x0c },
0269     { 0x3442, 0x0c },
0270     { 0x300a, 0xf0 },
0271     { 0x300b, 0x00 },
0272 };
0273 
0274 /* supported link frequencies */
0275 #define FREQ_INDEX_1080P    0
0276 #define FREQ_INDEX_720P     1
0277 static const s64 imx290_link_freq_2lanes[] = {
0278     [FREQ_INDEX_1080P] = 445500000,
0279     [FREQ_INDEX_720P] = 297000000,
0280 };
0281 static const s64 imx290_link_freq_4lanes[] = {
0282     [FREQ_INDEX_1080P] = 222750000,
0283     [FREQ_INDEX_720P] = 148500000,
0284 };
0285 
0286 /*
0287  * In this function and in the similar ones below We rely on imx290_probe()
0288  * to ensure that nlanes is either 2 or 4.
0289  */
0290 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
0291 {
0292     if (imx290->nlanes == 2)
0293         return imx290_link_freq_2lanes;
0294     else
0295         return imx290_link_freq_4lanes;
0296 }
0297 
0298 static inline int imx290_link_freqs_num(const struct imx290 *imx290)
0299 {
0300     if (imx290->nlanes == 2)
0301         return ARRAY_SIZE(imx290_link_freq_2lanes);
0302     else
0303         return ARRAY_SIZE(imx290_link_freq_4lanes);
0304 }
0305 
0306 /* Mode configs */
0307 static const struct imx290_mode imx290_modes_2lanes[] = {
0308     {
0309         .width = 1920,
0310         .height = 1080,
0311         .hmax = 0x1130,
0312         .link_freq_index = FREQ_INDEX_1080P,
0313         .data = imx290_1080p_settings,
0314         .data_size = ARRAY_SIZE(imx290_1080p_settings),
0315     },
0316     {
0317         .width = 1280,
0318         .height = 720,
0319         .hmax = 0x19c8,
0320         .link_freq_index = FREQ_INDEX_720P,
0321         .data = imx290_720p_settings,
0322         .data_size = ARRAY_SIZE(imx290_720p_settings),
0323     },
0324 };
0325 
0326 static const struct imx290_mode imx290_modes_4lanes[] = {
0327     {
0328         .width = 1920,
0329         .height = 1080,
0330         .hmax = 0x0898,
0331         .link_freq_index = FREQ_INDEX_1080P,
0332         .data = imx290_1080p_settings,
0333         .data_size = ARRAY_SIZE(imx290_1080p_settings),
0334     },
0335     {
0336         .width = 1280,
0337         .height = 720,
0338         .hmax = 0x0ce4,
0339         .link_freq_index = FREQ_INDEX_720P,
0340         .data = imx290_720p_settings,
0341         .data_size = ARRAY_SIZE(imx290_720p_settings),
0342     },
0343 };
0344 
0345 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
0346 {
0347     if (imx290->nlanes == 2)
0348         return imx290_modes_2lanes;
0349     else
0350         return imx290_modes_4lanes;
0351 }
0352 
0353 static inline int imx290_modes_num(const struct imx290 *imx290)
0354 {
0355     if (imx290->nlanes == 2)
0356         return ARRAY_SIZE(imx290_modes_2lanes);
0357     else
0358         return ARRAY_SIZE(imx290_modes_4lanes);
0359 }
0360 
0361 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
0362 {
0363     return container_of(_sd, struct imx290, sd);
0364 }
0365 
0366 static inline int __always_unused imx290_read_reg(struct imx290 *imx290, u16 addr, u8 *value)
0367 {
0368     unsigned int regval;
0369     int ret;
0370 
0371     ret = regmap_read(imx290->regmap, addr, &regval);
0372     if (ret) {
0373         dev_err(imx290->dev, "I2C read failed for addr: %x\n", addr);
0374         return ret;
0375     }
0376 
0377     *value = regval & 0xff;
0378 
0379     return 0;
0380 }
0381 
0382 static int imx290_write_reg(struct imx290 *imx290, u16 addr, u8 value)
0383 {
0384     int ret;
0385 
0386     ret = regmap_write(imx290->regmap, addr, value);
0387     if (ret) {
0388         dev_err(imx290->dev, "I2C write failed for addr: %x\n", addr);
0389         return ret;
0390     }
0391 
0392     return ret;
0393 }
0394 
0395 static int imx290_set_register_array(struct imx290 *imx290,
0396                      const struct imx290_regval *settings,
0397                      unsigned int num_settings)
0398 {
0399     unsigned int i;
0400     int ret;
0401 
0402     for (i = 0; i < num_settings; ++i, ++settings) {
0403         ret = imx290_write_reg(imx290, settings->reg, settings->val);
0404         if (ret < 0)
0405             return ret;
0406     }
0407 
0408     /* Provide 10ms settle time */
0409     usleep_range(10000, 11000);
0410 
0411     return 0;
0412 }
0413 
0414 static int imx290_write_buffered_reg(struct imx290 *imx290, u16 address_low,
0415                      u8 nr_regs, u32 value)
0416 {
0417     unsigned int i;
0418     int ret;
0419 
0420     ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x01);
0421     if (ret) {
0422         dev_err(imx290->dev, "Error setting hold register\n");
0423         return ret;
0424     }
0425 
0426     for (i = 0; i < nr_regs; i++) {
0427         ret = imx290_write_reg(imx290, address_low + i,
0428                        (u8)(value >> (i * 8)));
0429         if (ret) {
0430             dev_err(imx290->dev, "Error writing buffered registers\n");
0431             return ret;
0432         }
0433     }
0434 
0435     ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x00);
0436     if (ret) {
0437         dev_err(imx290->dev, "Error setting hold register\n");
0438         return ret;
0439     }
0440 
0441     return ret;
0442 }
0443 
0444 static int imx290_set_gain(struct imx290 *imx290, u32 value)
0445 {
0446     int ret;
0447 
0448     ret = imx290_write_buffered_reg(imx290, IMX290_GAIN, 1, value);
0449     if (ret)
0450         dev_err(imx290->dev, "Unable to write gain\n");
0451 
0452     return ret;
0453 }
0454 
0455 /* Stop streaming */
0456 static int imx290_stop_streaming(struct imx290 *imx290)
0457 {
0458     int ret;
0459 
0460     ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x01);
0461     if (ret < 0)
0462         return ret;
0463 
0464     msleep(30);
0465 
0466     return imx290_write_reg(imx290, IMX290_XMSTA, 0x01);
0467 }
0468 
0469 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
0470 {
0471     struct imx290 *imx290 = container_of(ctrl->handler,
0472                          struct imx290, ctrls);
0473     int ret = 0;
0474 
0475     /* V4L2 controls values will be applied only when power is already up */
0476     if (!pm_runtime_get_if_in_use(imx290->dev))
0477         return 0;
0478 
0479     switch (ctrl->id) {
0480     case V4L2_CID_GAIN:
0481         ret = imx290_set_gain(imx290, ctrl->val);
0482         break;
0483     case V4L2_CID_TEST_PATTERN:
0484         if (ctrl->val) {
0485             imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);
0486             imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
0487             usleep_range(10000, 11000);
0488             imx290_write_reg(imx290, IMX290_PGCTRL,
0489                      (u8)(IMX290_PGCTRL_REGEN |
0490                      IMX290_PGCTRL_THRU |
0491                      IMX290_PGCTRL_MODE(ctrl->val)));
0492         } else {
0493             imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);
0494             usleep_range(10000, 11000);
0495             if (imx290->bpp == 10)
0496                 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
0497                          0x3c);
0498             else /* 12 bits per pixel */
0499                 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
0500                          0xf0);
0501             imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
0502         }
0503         break;
0504     default:
0505         ret = -EINVAL;
0506         break;
0507     }
0508 
0509     pm_runtime_put(imx290->dev);
0510 
0511     return ret;
0512 }
0513 
0514 static const struct v4l2_ctrl_ops imx290_ctrl_ops = {
0515     .s_ctrl = imx290_set_ctrl,
0516 };
0517 
0518 static int imx290_enum_mbus_code(struct v4l2_subdev *sd,
0519                  struct v4l2_subdev_state *sd_state,
0520                  struct v4l2_subdev_mbus_code_enum *code)
0521 {
0522     if (code->index >= ARRAY_SIZE(imx290_formats))
0523         return -EINVAL;
0524 
0525     code->code = imx290_formats[code->index].code;
0526 
0527     return 0;
0528 }
0529 
0530 static int imx290_enum_frame_size(struct v4l2_subdev *sd,
0531                   struct v4l2_subdev_state *sd_state,
0532                   struct v4l2_subdev_frame_size_enum *fse)
0533 {
0534     const struct imx290 *imx290 = to_imx290(sd);
0535     const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);
0536 
0537     if ((fse->code != imx290_formats[0].code) &&
0538         (fse->code != imx290_formats[1].code))
0539         return -EINVAL;
0540 
0541     if (fse->index >= imx290_modes_num(imx290))
0542         return -EINVAL;
0543 
0544     fse->min_width = imx290_modes[fse->index].width;
0545     fse->max_width = imx290_modes[fse->index].width;
0546     fse->min_height = imx290_modes[fse->index].height;
0547     fse->max_height = imx290_modes[fse->index].height;
0548 
0549     return 0;
0550 }
0551 
0552 static int imx290_get_fmt(struct v4l2_subdev *sd,
0553               struct v4l2_subdev_state *sd_state,
0554               struct v4l2_subdev_format *fmt)
0555 {
0556     struct imx290 *imx290 = to_imx290(sd);
0557     struct v4l2_mbus_framefmt *framefmt;
0558 
0559     mutex_lock(&imx290->lock);
0560 
0561     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
0562         framefmt = v4l2_subdev_get_try_format(&imx290->sd, sd_state,
0563                               fmt->pad);
0564     else
0565         framefmt = &imx290->current_format;
0566 
0567     fmt->format = *framefmt;
0568 
0569     mutex_unlock(&imx290->lock);
0570 
0571     return 0;
0572 }
0573 
0574 static inline u8 imx290_get_link_freq_index(struct imx290 *imx290)
0575 {
0576     return imx290->current_mode->link_freq_index;
0577 }
0578 
0579 static s64 imx290_get_link_freq(struct imx290 *imx290)
0580 {
0581     u8 index = imx290_get_link_freq_index(imx290);
0582 
0583     return *(imx290_link_freqs_ptr(imx290) + index);
0584 }
0585 
0586 static u64 imx290_calc_pixel_rate(struct imx290 *imx290)
0587 {
0588     s64 link_freq = imx290_get_link_freq(imx290);
0589     u8 nlanes = imx290->nlanes;
0590     u64 pixel_rate;
0591 
0592     /* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
0593     pixel_rate = link_freq * 2 * nlanes;
0594     do_div(pixel_rate, imx290->bpp);
0595     return pixel_rate;
0596 }
0597 
0598 static int imx290_set_fmt(struct v4l2_subdev *sd,
0599               struct v4l2_subdev_state *sd_state,
0600               struct v4l2_subdev_format *fmt)
0601 {
0602     struct imx290 *imx290 = to_imx290(sd);
0603     const struct imx290_mode *mode;
0604     struct v4l2_mbus_framefmt *format;
0605     unsigned int i;
0606 
0607     mutex_lock(&imx290->lock);
0608 
0609     mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290),
0610                       imx290_modes_num(imx290), width, height,
0611                       fmt->format.width, fmt->format.height);
0612 
0613     fmt->format.width = mode->width;
0614     fmt->format.height = mode->height;
0615 
0616     for (i = 0; i < ARRAY_SIZE(imx290_formats); i++)
0617         if (imx290_formats[i].code == fmt->format.code)
0618             break;
0619 
0620     if (i >= ARRAY_SIZE(imx290_formats))
0621         i = 0;
0622 
0623     fmt->format.code = imx290_formats[i].code;
0624     fmt->format.field = V4L2_FIELD_NONE;
0625 
0626     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0627         format = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0628     } else {
0629         format = &imx290->current_format;
0630         imx290->current_mode = mode;
0631         imx290->bpp = imx290_formats[i].bpp;
0632 
0633         if (imx290->link_freq)
0634             __v4l2_ctrl_s_ctrl(imx290->link_freq,
0635                        imx290_get_link_freq_index(imx290));
0636         if (imx290->pixel_rate)
0637             __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate,
0638                          imx290_calc_pixel_rate(imx290));
0639     }
0640 
0641     *format = fmt->format;
0642 
0643     mutex_unlock(&imx290->lock);
0644 
0645     return 0;
0646 }
0647 
0648 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev,
0649                   struct v4l2_subdev_state *sd_state)
0650 {
0651     struct v4l2_subdev_format fmt = { 0 };
0652 
0653     fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
0654     fmt.format.width = 1920;
0655     fmt.format.height = 1080;
0656 
0657     imx290_set_fmt(subdev, sd_state, &fmt);
0658 
0659     return 0;
0660 }
0661 
0662 static int imx290_write_current_format(struct imx290 *imx290)
0663 {
0664     int ret;
0665 
0666     switch (imx290->current_format.code) {
0667     case MEDIA_BUS_FMT_SRGGB10_1X10:
0668         ret = imx290_set_register_array(imx290, imx290_10bit_settings,
0669                         ARRAY_SIZE(
0670                             imx290_10bit_settings));
0671         if (ret < 0) {
0672             dev_err(imx290->dev, "Could not set format registers\n");
0673             return ret;
0674         }
0675         break;
0676     case MEDIA_BUS_FMT_SRGGB12_1X12:
0677         ret = imx290_set_register_array(imx290, imx290_12bit_settings,
0678                         ARRAY_SIZE(
0679                             imx290_12bit_settings));
0680         if (ret < 0) {
0681             dev_err(imx290->dev, "Could not set format registers\n");
0682             return ret;
0683         }
0684         break;
0685     default:
0686         dev_err(imx290->dev, "Unknown pixel format\n");
0687         return -EINVAL;
0688     }
0689 
0690     return 0;
0691 }
0692 
0693 static int imx290_set_hmax(struct imx290 *imx290, u32 val)
0694 {
0695     int ret;
0696 
0697     ret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (val & 0xff));
0698     if (ret) {
0699         dev_err(imx290->dev, "Error setting HMAX register\n");
0700         return ret;
0701     }
0702 
0703     ret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((val >> 8) & 0xff));
0704     if (ret) {
0705         dev_err(imx290->dev, "Error setting HMAX register\n");
0706         return ret;
0707     }
0708 
0709     return 0;
0710 }
0711 
0712 /* Start streaming */
0713 static int imx290_start_streaming(struct imx290 *imx290)
0714 {
0715     int ret;
0716 
0717     /* Set init register settings */
0718     ret = imx290_set_register_array(imx290, imx290_global_init_settings,
0719                     ARRAY_SIZE(
0720                         imx290_global_init_settings));
0721     if (ret < 0) {
0722         dev_err(imx290->dev, "Could not set init registers\n");
0723         return ret;
0724     }
0725 
0726     /* Apply the register values related to current frame format */
0727     ret = imx290_write_current_format(imx290);
0728     if (ret < 0) {
0729         dev_err(imx290->dev, "Could not set frame format\n");
0730         return ret;
0731     }
0732 
0733     /* Apply default values of current mode */
0734     ret = imx290_set_register_array(imx290, imx290->current_mode->data,
0735                     imx290->current_mode->data_size);
0736     if (ret < 0) {
0737         dev_err(imx290->dev, "Could not set current mode\n");
0738         return ret;
0739     }
0740     ret = imx290_set_hmax(imx290, imx290->current_mode->hmax);
0741     if (ret < 0)
0742         return ret;
0743 
0744     /* Apply customized values from user */
0745     ret = v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);
0746     if (ret) {
0747         dev_err(imx290->dev, "Could not sync v4l2 controls\n");
0748         return ret;
0749     }
0750 
0751     ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x00);
0752     if (ret < 0)
0753         return ret;
0754 
0755     msleep(30);
0756 
0757     /* Start streaming */
0758     return imx290_write_reg(imx290, IMX290_XMSTA, 0x00);
0759 }
0760 
0761 static int imx290_set_stream(struct v4l2_subdev *sd, int enable)
0762 {
0763     struct imx290 *imx290 = to_imx290(sd);
0764     int ret = 0;
0765 
0766     if (enable) {
0767         ret = pm_runtime_resume_and_get(imx290->dev);
0768         if (ret < 0)
0769             goto unlock_and_return;
0770 
0771         ret = imx290_start_streaming(imx290);
0772         if (ret) {
0773             dev_err(imx290->dev, "Start stream failed\n");
0774             pm_runtime_put(imx290->dev);
0775             goto unlock_and_return;
0776         }
0777     } else {
0778         imx290_stop_streaming(imx290);
0779         pm_runtime_put(imx290->dev);
0780     }
0781 
0782 unlock_and_return:
0783 
0784     return ret;
0785 }
0786 
0787 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290)
0788 {
0789     unsigned int i;
0790 
0791     for (i = 0; i < IMX290_NUM_SUPPLIES; i++)
0792         imx290->supplies[i].supply = imx290_supply_name[i];
0793 
0794     return devm_regulator_bulk_get(dev, IMX290_NUM_SUPPLIES,
0795                        imx290->supplies);
0796 }
0797 
0798 static int imx290_set_data_lanes(struct imx290 *imx290)
0799 {
0800     int ret = 0, laneval, frsel;
0801 
0802     switch (imx290->nlanes) {
0803     case 2:
0804         laneval = 0x01;
0805         frsel = 0x02;
0806         break;
0807     case 4:
0808         laneval = 0x03;
0809         frsel = 0x01;
0810         break;
0811     default:
0812         /*
0813          * We should never hit this since the data lane count is
0814          * validated in probe itself
0815          */
0816         dev_err(imx290->dev, "Lane configuration not supported\n");
0817         ret = -EINVAL;
0818         goto exit;
0819     }
0820 
0821     ret = imx290_write_reg(imx290, IMX290_PHY_LANE_NUM, laneval);
0822     if (ret) {
0823         dev_err(imx290->dev, "Error setting Physical Lane number register\n");
0824         goto exit;
0825     }
0826 
0827     ret = imx290_write_reg(imx290, IMX290_CSI_LANE_MODE, laneval);
0828     if (ret) {
0829         dev_err(imx290->dev, "Error setting CSI Lane mode register\n");
0830         goto exit;
0831     }
0832 
0833     ret = imx290_write_reg(imx290, IMX290_FR_FDG_SEL, frsel);
0834     if (ret)
0835         dev_err(imx290->dev, "Error setting FR/FDG SEL register\n");
0836 
0837 exit:
0838     return ret;
0839 }
0840 
0841 static int imx290_power_on(struct device *dev)
0842 {
0843     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0844     struct imx290 *imx290 = to_imx290(sd);
0845     int ret;
0846 
0847     ret = clk_prepare_enable(imx290->xclk);
0848     if (ret) {
0849         dev_err(dev, "Failed to enable clock\n");
0850         return ret;
0851     }
0852 
0853     ret = regulator_bulk_enable(IMX290_NUM_SUPPLIES, imx290->supplies);
0854     if (ret) {
0855         dev_err(dev, "Failed to enable regulators\n");
0856         clk_disable_unprepare(imx290->xclk);
0857         return ret;
0858     }
0859 
0860     usleep_range(1, 2);
0861     gpiod_set_value_cansleep(imx290->rst_gpio, 0);
0862     usleep_range(30000, 31000);
0863 
0864     /* Set data lane count */
0865     imx290_set_data_lanes(imx290);
0866 
0867     return 0;
0868 }
0869 
0870 static int imx290_power_off(struct device *dev)
0871 {
0872     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0873     struct imx290 *imx290 = to_imx290(sd);
0874 
0875     clk_disable_unprepare(imx290->xclk);
0876     gpiod_set_value_cansleep(imx290->rst_gpio, 1);
0877     regulator_bulk_disable(IMX290_NUM_SUPPLIES, imx290->supplies);
0878 
0879     return 0;
0880 }
0881 
0882 static const struct dev_pm_ops imx290_pm_ops = {
0883     SET_RUNTIME_PM_OPS(imx290_power_off, imx290_power_on, NULL)
0884 };
0885 
0886 static const struct v4l2_subdev_video_ops imx290_video_ops = {
0887     .s_stream = imx290_set_stream,
0888 };
0889 
0890 static const struct v4l2_subdev_pad_ops imx290_pad_ops = {
0891     .init_cfg = imx290_entity_init_cfg,
0892     .enum_mbus_code = imx290_enum_mbus_code,
0893     .enum_frame_size = imx290_enum_frame_size,
0894     .get_fmt = imx290_get_fmt,
0895     .set_fmt = imx290_set_fmt,
0896 };
0897 
0898 static const struct v4l2_subdev_ops imx290_subdev_ops = {
0899     .video = &imx290_video_ops,
0900     .pad = &imx290_pad_ops,
0901 };
0902 
0903 static const struct media_entity_operations imx290_subdev_entity_ops = {
0904     .link_validate = v4l2_subdev_link_validate,
0905 };
0906 
0907 /*
0908  * Returns 0 if all link frequencies used by the driver for the given number
0909  * of MIPI data lanes are mentioned in the device tree, or the value of the
0910  * first missing frequency otherwise.
0911  */
0912 static s64 imx290_check_link_freqs(const struct imx290 *imx290,
0913                    const struct v4l2_fwnode_endpoint *ep)
0914 {
0915     int i, j;
0916     const s64 *freqs = imx290_link_freqs_ptr(imx290);
0917     int freqs_count = imx290_link_freqs_num(imx290);
0918 
0919     for (i = 0; i < freqs_count; i++) {
0920         for (j = 0; j < ep->nr_of_link_frequencies; j++)
0921             if (freqs[i] == ep->link_frequencies[j])
0922                 break;
0923         if (j == ep->nr_of_link_frequencies)
0924             return freqs[i];
0925     }
0926     return 0;
0927 }
0928 
0929 static int imx290_probe(struct i2c_client *client)
0930 {
0931     struct device *dev = &client->dev;
0932     struct fwnode_handle *endpoint;
0933     /* Only CSI2 is supported for now: */
0934     struct v4l2_fwnode_endpoint ep = {
0935         .bus_type = V4L2_MBUS_CSI2_DPHY
0936     };
0937     struct imx290 *imx290;
0938     u32 xclk_freq;
0939     s64 fq;
0940     int ret;
0941 
0942     imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL);
0943     if (!imx290)
0944         return -ENOMEM;
0945 
0946     imx290->dev = dev;
0947     imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config);
0948     if (IS_ERR(imx290->regmap)) {
0949         dev_err(dev, "Unable to initialize I2C\n");
0950         return -ENODEV;
0951     }
0952 
0953     endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
0954     if (!endpoint) {
0955         dev_err(dev, "Endpoint node not found\n");
0956         return -EINVAL;
0957     }
0958 
0959     ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
0960     fwnode_handle_put(endpoint);
0961     if (ret == -ENXIO) {
0962         dev_err(dev, "Unsupported bus type, should be CSI2\n");
0963         goto free_err;
0964     } else if (ret) {
0965         dev_err(dev, "Parsing endpoint node failed\n");
0966         goto free_err;
0967     }
0968 
0969     /* Get number of data lanes */
0970     imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes;
0971     if (imx290->nlanes != 2 && imx290->nlanes != 4) {
0972         dev_err(dev, "Invalid data lanes: %d\n", imx290->nlanes);
0973         ret = -EINVAL;
0974         goto free_err;
0975     }
0976 
0977     dev_dbg(dev, "Using %u data lanes\n", imx290->nlanes);
0978 
0979     if (!ep.nr_of_link_frequencies) {
0980         dev_err(dev, "link-frequency property not found in DT\n");
0981         ret = -EINVAL;
0982         goto free_err;
0983     }
0984 
0985     /* Check that link frequences for all the modes are in device tree */
0986     fq = imx290_check_link_freqs(imx290, &ep);
0987     if (fq) {
0988         dev_err(dev, "Link frequency of %lld is not supported\n", fq);
0989         ret = -EINVAL;
0990         goto free_err;
0991     }
0992 
0993     /* get system clock (xclk) */
0994     imx290->xclk = devm_clk_get(dev, "xclk");
0995     if (IS_ERR(imx290->xclk)) {
0996         dev_err(dev, "Could not get xclk");
0997         ret = PTR_ERR(imx290->xclk);
0998         goto free_err;
0999     }
1000 
1001     ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1002                        &xclk_freq);
1003     if (ret) {
1004         dev_err(dev, "Could not get xclk frequency\n");
1005         goto free_err;
1006     }
1007 
1008     /* external clock must be 37.125 MHz */
1009     if (xclk_freq != 37125000) {
1010         dev_err(dev, "External clock frequency %u is not supported\n",
1011             xclk_freq);
1012         ret = -EINVAL;
1013         goto free_err;
1014     }
1015 
1016     ret = clk_set_rate(imx290->xclk, xclk_freq);
1017     if (ret) {
1018         dev_err(dev, "Could not set xclk frequency\n");
1019         goto free_err;
1020     }
1021 
1022     ret = imx290_get_regulators(dev, imx290);
1023     if (ret < 0) {
1024         dev_err(dev, "Cannot get regulators\n");
1025         goto free_err;
1026     }
1027 
1028     imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset",
1029                            GPIOD_OUT_HIGH);
1030     if (IS_ERR(imx290->rst_gpio)) {
1031         dev_err(dev, "Cannot get reset gpio\n");
1032         ret = PTR_ERR(imx290->rst_gpio);
1033         goto free_err;
1034     }
1035 
1036     mutex_init(&imx290->lock);
1037 
1038     /*
1039      * Initialize the frame format. In particular, imx290->current_mode
1040      * and imx290->bpp are set to defaults: imx290_calc_pixel_rate() call
1041      * below relies on these fields.
1042      */
1043     imx290_entity_init_cfg(&imx290->sd, NULL);
1044 
1045     v4l2_ctrl_handler_init(&imx290->ctrls, 4);
1046 
1047     v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1048               V4L2_CID_GAIN, 0, 72, 1, 0);
1049 
1050     imx290->link_freq =
1051         v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
1052                        V4L2_CID_LINK_FREQ,
1053                        imx290_link_freqs_num(imx290) - 1, 0,
1054                        imx290_link_freqs_ptr(imx290));
1055     if (imx290->link_freq)
1056         imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1057 
1058     imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1059                            V4L2_CID_PIXEL_RATE,
1060                            1, INT_MAX, 1,
1061                            imx290_calc_pixel_rate(imx290));
1062 
1063     v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
1064                      V4L2_CID_TEST_PATTERN,
1065                      ARRAY_SIZE(imx290_test_pattern_menu) - 1,
1066                      0, 0, imx290_test_pattern_menu);
1067 
1068     imx290->sd.ctrl_handler = &imx290->ctrls;
1069 
1070     if (imx290->ctrls.error) {
1071         dev_err(dev, "Control initialization error %d\n",
1072             imx290->ctrls.error);
1073         ret = imx290->ctrls.error;
1074         goto free_ctrl;
1075     }
1076 
1077     v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops);
1078     imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1079     imx290->sd.dev = &client->dev;
1080     imx290->sd.entity.ops = &imx290_subdev_entity_ops;
1081     imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1082 
1083     imx290->pad.flags = MEDIA_PAD_FL_SOURCE;
1084     ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad);
1085     if (ret < 0) {
1086         dev_err(dev, "Could not register media entity\n");
1087         goto free_ctrl;
1088     }
1089 
1090     ret = v4l2_async_register_subdev(&imx290->sd);
1091     if (ret < 0) {
1092         dev_err(dev, "Could not register v4l2 device\n");
1093         goto free_entity;
1094     }
1095 
1096     /* Power on the device to match runtime PM state below */
1097     ret = imx290_power_on(dev);
1098     if (ret < 0) {
1099         dev_err(dev, "Could not power on the device\n");
1100         goto free_entity;
1101     }
1102 
1103     pm_runtime_set_active(dev);
1104     pm_runtime_enable(dev);
1105     pm_runtime_idle(dev);
1106 
1107     v4l2_fwnode_endpoint_free(&ep);
1108 
1109     return 0;
1110 
1111 free_entity:
1112     media_entity_cleanup(&imx290->sd.entity);
1113 free_ctrl:
1114     v4l2_ctrl_handler_free(&imx290->ctrls);
1115     mutex_destroy(&imx290->lock);
1116 free_err:
1117     v4l2_fwnode_endpoint_free(&ep);
1118 
1119     return ret;
1120 }
1121 
1122 static int imx290_remove(struct i2c_client *client)
1123 {
1124     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1125     struct imx290 *imx290 = to_imx290(sd);
1126 
1127     v4l2_async_unregister_subdev(sd);
1128     media_entity_cleanup(&sd->entity);
1129     v4l2_ctrl_handler_free(sd->ctrl_handler);
1130 
1131     mutex_destroy(&imx290->lock);
1132 
1133     pm_runtime_disable(imx290->dev);
1134     if (!pm_runtime_status_suspended(imx290->dev))
1135         imx290_power_off(imx290->dev);
1136     pm_runtime_set_suspended(imx290->dev);
1137 
1138     return 0;
1139 }
1140 
1141 static const struct of_device_id imx290_of_match[] = {
1142     { .compatible = "sony,imx290" },
1143     { /* sentinel */ }
1144 };
1145 MODULE_DEVICE_TABLE(of, imx290_of_match);
1146 
1147 static struct i2c_driver imx290_i2c_driver = {
1148     .probe_new  = imx290_probe,
1149     .remove = imx290_remove,
1150     .driver = {
1151         .name  = "imx290",
1152         .pm = &imx290_pm_ops,
1153         .of_match_table = of_match_ptr(imx290_of_match),
1154     },
1155 };
1156 
1157 module_i2c_driver(imx290_i2c_driver);
1158 
1159 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver");
1160 MODULE_AUTHOR("FRAMOS GmbH");
1161 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
1162 MODULE_LICENSE("GPL v2");
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