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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2018 Intel Corporation
0003 
0004 #include <linux/acpi.h>
0005 #include <linux/clk.h>
0006 #include <linux/delay.h>
0007 #include <linux/i2c.h>
0008 #include <linux/module.h>
0009 #include <linux/pm_runtime.h>
0010 #include <media/v4l2-ctrls.h>
0011 #include <media/v4l2-device.h>
0012 #include <asm/unaligned.h>
0013 
0014 #define IMX258_REG_VALUE_08BIT      1
0015 #define IMX258_REG_VALUE_16BIT      2
0016 
0017 #define IMX258_REG_MODE_SELECT      0x0100
0018 #define IMX258_MODE_STANDBY     0x00
0019 #define IMX258_MODE_STREAMING       0x01
0020 
0021 /* Chip ID */
0022 #define IMX258_REG_CHIP_ID      0x0016
0023 #define IMX258_CHIP_ID          0x0258
0024 
0025 /* V_TIMING internal */
0026 #define IMX258_VTS_30FPS        0x0c50
0027 #define IMX258_VTS_30FPS_2K     0x0638
0028 #define IMX258_VTS_30FPS_VGA        0x034c
0029 #define IMX258_VTS_MAX          0xffff
0030 
0031 /*Frame Length Line*/
0032 #define IMX258_FLL_MIN          0x08a6
0033 #define IMX258_FLL_MAX          0xffff
0034 #define IMX258_FLL_STEP         1
0035 #define IMX258_FLL_DEFAULT      0x0c98
0036 
0037 /* HBLANK control - read only */
0038 #define IMX258_PPL_DEFAULT      5352
0039 
0040 /* Exposure control */
0041 #define IMX258_REG_EXPOSURE     0x0202
0042 #define IMX258_EXPOSURE_MIN     4
0043 #define IMX258_EXPOSURE_STEP        1
0044 #define IMX258_EXPOSURE_DEFAULT     0x640
0045 #define IMX258_EXPOSURE_MAX     65535
0046 
0047 /* Analog gain control */
0048 #define IMX258_REG_ANALOG_GAIN      0x0204
0049 #define IMX258_ANA_GAIN_MIN     0
0050 #define IMX258_ANA_GAIN_MAX     480
0051 #define IMX258_ANA_GAIN_STEP        1
0052 #define IMX258_ANA_GAIN_DEFAULT     0x0
0053 
0054 /* Digital gain control */
0055 #define IMX258_REG_GR_DIGITAL_GAIN  0x020e
0056 #define IMX258_REG_R_DIGITAL_GAIN   0x0210
0057 #define IMX258_REG_B_DIGITAL_GAIN   0x0212
0058 #define IMX258_REG_GB_DIGITAL_GAIN  0x0214
0059 #define IMX258_DGTL_GAIN_MIN        0
0060 #define IMX258_DGTL_GAIN_MAX        4096    /* Max = 0xFFF */
0061 #define IMX258_DGTL_GAIN_DEFAULT    1024
0062 #define IMX258_DGTL_GAIN_STEP       1
0063 
0064 /* HDR control */
0065 #define IMX258_REG_HDR          0x0220
0066 #define IMX258_HDR_ON           BIT(0)
0067 #define IMX258_REG_HDR_RATIO        0x0222
0068 #define IMX258_HDR_RATIO_MIN        0
0069 #define IMX258_HDR_RATIO_MAX        5
0070 #define IMX258_HDR_RATIO_STEP       1
0071 #define IMX258_HDR_RATIO_DEFAULT    0x0
0072 
0073 /* Test Pattern Control */
0074 #define IMX258_REG_TEST_PATTERN     0x0600
0075 
0076 /* Orientation */
0077 #define REG_MIRROR_FLIP_CONTROL     0x0101
0078 #define REG_CONFIG_MIRROR_FLIP      0x03
0079 #define REG_CONFIG_FLIP_TEST_PATTERN    0x02
0080 
0081 /* Input clock frequency in Hz */
0082 #define IMX258_INPUT_CLOCK_FREQ     19200000
0083 
0084 struct imx258_reg {
0085     u16 address;
0086     u8 val;
0087 };
0088 
0089 struct imx258_reg_list {
0090     u32 num_of_regs;
0091     const struct imx258_reg *regs;
0092 };
0093 
0094 /* Link frequency config */
0095 struct imx258_link_freq_config {
0096     u32 pixels_per_line;
0097 
0098     /* PLL registers for this link frequency */
0099     struct imx258_reg_list reg_list;
0100 };
0101 
0102 /* Mode : resolution and related config&values */
0103 struct imx258_mode {
0104     /* Frame width */
0105     u32 width;
0106     /* Frame height */
0107     u32 height;
0108 
0109     /* V-timing */
0110     u32 vts_def;
0111     u32 vts_min;
0112 
0113     /* Index of Link frequency config to be used */
0114     u32 link_freq_index;
0115     /* Default register values */
0116     struct imx258_reg_list reg_list;
0117 };
0118 
0119 /* 4208x3118 needs 1267Mbps/lane, 4 lanes */
0120 static const struct imx258_reg mipi_data_rate_1267mbps[] = {
0121     { 0x0301, 0x05 },
0122     { 0x0303, 0x02 },
0123     { 0x0305, 0x03 },
0124     { 0x0306, 0x00 },
0125     { 0x0307, 0xC6 },
0126     { 0x0309, 0x0A },
0127     { 0x030B, 0x01 },
0128     { 0x030D, 0x02 },
0129     { 0x030E, 0x00 },
0130     { 0x030F, 0xD8 },
0131     { 0x0310, 0x00 },
0132     { 0x0820, 0x13 },
0133     { 0x0821, 0x4C },
0134     { 0x0822, 0xCC },
0135     { 0x0823, 0xCC },
0136 };
0137 
0138 static const struct imx258_reg mipi_data_rate_640mbps[] = {
0139     { 0x0301, 0x05 },
0140     { 0x0303, 0x02 },
0141     { 0x0305, 0x03 },
0142     { 0x0306, 0x00 },
0143     { 0x0307, 0x64 },
0144     { 0x0309, 0x0A },
0145     { 0x030B, 0x01 },
0146     { 0x030D, 0x02 },
0147     { 0x030E, 0x00 },
0148     { 0x030F, 0xD8 },
0149     { 0x0310, 0x00 },
0150     { 0x0820, 0x0A },
0151     { 0x0821, 0x00 },
0152     { 0x0822, 0x00 },
0153     { 0x0823, 0x00 },
0154 };
0155 
0156 static const struct imx258_reg mode_4208x3118_regs[] = {
0157     { 0x0136, 0x13 },
0158     { 0x0137, 0x33 },
0159     { 0x3051, 0x00 },
0160     { 0x3052, 0x00 },
0161     { 0x4E21, 0x14 },
0162     { 0x6B11, 0xCF },
0163     { 0x7FF0, 0x08 },
0164     { 0x7FF1, 0x0F },
0165     { 0x7FF2, 0x08 },
0166     { 0x7FF3, 0x1B },
0167     { 0x7FF4, 0x23 },
0168     { 0x7FF5, 0x60 },
0169     { 0x7FF6, 0x00 },
0170     { 0x7FF7, 0x01 },
0171     { 0x7FF8, 0x00 },
0172     { 0x7FF9, 0x78 },
0173     { 0x7FFA, 0x00 },
0174     { 0x7FFB, 0x00 },
0175     { 0x7FFC, 0x00 },
0176     { 0x7FFD, 0x00 },
0177     { 0x7FFE, 0x00 },
0178     { 0x7FFF, 0x03 },
0179     { 0x7F76, 0x03 },
0180     { 0x7F77, 0xFE },
0181     { 0x7FA8, 0x03 },
0182     { 0x7FA9, 0xFE },
0183     { 0x7B24, 0x81 },
0184     { 0x7B25, 0x00 },
0185     { 0x6564, 0x07 },
0186     { 0x6B0D, 0x41 },
0187     { 0x653D, 0x04 },
0188     { 0x6B05, 0x8C },
0189     { 0x6B06, 0xF9 },
0190     { 0x6B08, 0x65 },
0191     { 0x6B09, 0xFC },
0192     { 0x6B0A, 0xCF },
0193     { 0x6B0B, 0xD2 },
0194     { 0x6700, 0x0E },
0195     { 0x6707, 0x0E },
0196     { 0x9104, 0x00 },
0197     { 0x4648, 0x7F },
0198     { 0x7420, 0x00 },
0199     { 0x7421, 0x1C },
0200     { 0x7422, 0x00 },
0201     { 0x7423, 0xD7 },
0202     { 0x5F04, 0x00 },
0203     { 0x5F05, 0xED },
0204     { 0x0112, 0x0A },
0205     { 0x0113, 0x0A },
0206     { 0x0114, 0x03 },
0207     { 0x0342, 0x14 },
0208     { 0x0343, 0xE8 },
0209     { 0x0340, 0x0C },
0210     { 0x0341, 0x50 },
0211     { 0x0344, 0x00 },
0212     { 0x0345, 0x00 },
0213     { 0x0346, 0x00 },
0214     { 0x0347, 0x00 },
0215     { 0x0348, 0x10 },
0216     { 0x0349, 0x6F },
0217     { 0x034A, 0x0C },
0218     { 0x034B, 0x2E },
0219     { 0x0381, 0x01 },
0220     { 0x0383, 0x01 },
0221     { 0x0385, 0x01 },
0222     { 0x0387, 0x01 },
0223     { 0x0900, 0x00 },
0224     { 0x0901, 0x11 },
0225     { 0x0401, 0x00 },
0226     { 0x0404, 0x00 },
0227     { 0x0405, 0x10 },
0228     { 0x0408, 0x00 },
0229     { 0x0409, 0x00 },
0230     { 0x040A, 0x00 },
0231     { 0x040B, 0x00 },
0232     { 0x040C, 0x10 },
0233     { 0x040D, 0x70 },
0234     { 0x040E, 0x0C },
0235     { 0x040F, 0x30 },
0236     { 0x3038, 0x00 },
0237     { 0x303A, 0x00 },
0238     { 0x303B, 0x10 },
0239     { 0x300D, 0x00 },
0240     { 0x034C, 0x10 },
0241     { 0x034D, 0x70 },
0242     { 0x034E, 0x0C },
0243     { 0x034F, 0x30 },
0244     { 0x0350, 0x01 },
0245     { 0x0202, 0x0C },
0246     { 0x0203, 0x46 },
0247     { 0x0204, 0x00 },
0248     { 0x0205, 0x00 },
0249     { 0x020E, 0x01 },
0250     { 0x020F, 0x00 },
0251     { 0x0210, 0x01 },
0252     { 0x0211, 0x00 },
0253     { 0x0212, 0x01 },
0254     { 0x0213, 0x00 },
0255     { 0x0214, 0x01 },
0256     { 0x0215, 0x00 },
0257     { 0x7BCD, 0x00 },
0258     { 0x94DC, 0x20 },
0259     { 0x94DD, 0x20 },
0260     { 0x94DE, 0x20 },
0261     { 0x95DC, 0x20 },
0262     { 0x95DD, 0x20 },
0263     { 0x95DE, 0x20 },
0264     { 0x7FB0, 0x00 },
0265     { 0x9010, 0x3E },
0266     { 0x9419, 0x50 },
0267     { 0x941B, 0x50 },
0268     { 0x9519, 0x50 },
0269     { 0x951B, 0x50 },
0270     { 0x3030, 0x00 },
0271     { 0x3032, 0x00 },
0272     { 0x0220, 0x00 },
0273 };
0274 
0275 static const struct imx258_reg mode_2104_1560_regs[] = {
0276     { 0x0136, 0x13 },
0277     { 0x0137, 0x33 },
0278     { 0x3051, 0x00 },
0279     { 0x3052, 0x00 },
0280     { 0x4E21, 0x14 },
0281     { 0x6B11, 0xCF },
0282     { 0x7FF0, 0x08 },
0283     { 0x7FF1, 0x0F },
0284     { 0x7FF2, 0x08 },
0285     { 0x7FF3, 0x1B },
0286     { 0x7FF4, 0x23 },
0287     { 0x7FF5, 0x60 },
0288     { 0x7FF6, 0x00 },
0289     { 0x7FF7, 0x01 },
0290     { 0x7FF8, 0x00 },
0291     { 0x7FF9, 0x78 },
0292     { 0x7FFA, 0x00 },
0293     { 0x7FFB, 0x00 },
0294     { 0x7FFC, 0x00 },
0295     { 0x7FFD, 0x00 },
0296     { 0x7FFE, 0x00 },
0297     { 0x7FFF, 0x03 },
0298     { 0x7F76, 0x03 },
0299     { 0x7F77, 0xFE },
0300     { 0x7FA8, 0x03 },
0301     { 0x7FA9, 0xFE },
0302     { 0x7B24, 0x81 },
0303     { 0x7B25, 0x00 },
0304     { 0x6564, 0x07 },
0305     { 0x6B0D, 0x41 },
0306     { 0x653D, 0x04 },
0307     { 0x6B05, 0x8C },
0308     { 0x6B06, 0xF9 },
0309     { 0x6B08, 0x65 },
0310     { 0x6B09, 0xFC },
0311     { 0x6B0A, 0xCF },
0312     { 0x6B0B, 0xD2 },
0313     { 0x6700, 0x0E },
0314     { 0x6707, 0x0E },
0315     { 0x9104, 0x00 },
0316     { 0x4648, 0x7F },
0317     { 0x7420, 0x00 },
0318     { 0x7421, 0x1C },
0319     { 0x7422, 0x00 },
0320     { 0x7423, 0xD7 },
0321     { 0x5F04, 0x00 },
0322     { 0x5F05, 0xED },
0323     { 0x0112, 0x0A },
0324     { 0x0113, 0x0A },
0325     { 0x0114, 0x03 },
0326     { 0x0342, 0x14 },
0327     { 0x0343, 0xE8 },
0328     { 0x0340, 0x06 },
0329     { 0x0341, 0x38 },
0330     { 0x0344, 0x00 },
0331     { 0x0345, 0x00 },
0332     { 0x0346, 0x00 },
0333     { 0x0347, 0x00 },
0334     { 0x0348, 0x10 },
0335     { 0x0349, 0x6F },
0336     { 0x034A, 0x0C },
0337     { 0x034B, 0x2E },
0338     { 0x0381, 0x01 },
0339     { 0x0383, 0x01 },
0340     { 0x0385, 0x01 },
0341     { 0x0387, 0x01 },
0342     { 0x0900, 0x01 },
0343     { 0x0901, 0x12 },
0344     { 0x0401, 0x01 },
0345     { 0x0404, 0x00 },
0346     { 0x0405, 0x20 },
0347     { 0x0408, 0x00 },
0348     { 0x0409, 0x02 },
0349     { 0x040A, 0x00 },
0350     { 0x040B, 0x00 },
0351     { 0x040C, 0x10 },
0352     { 0x040D, 0x6A },
0353     { 0x040E, 0x06 },
0354     { 0x040F, 0x18 },
0355     { 0x3038, 0x00 },
0356     { 0x303A, 0x00 },
0357     { 0x303B, 0x10 },
0358     { 0x300D, 0x00 },
0359     { 0x034C, 0x08 },
0360     { 0x034D, 0x38 },
0361     { 0x034E, 0x06 },
0362     { 0x034F, 0x18 },
0363     { 0x0350, 0x01 },
0364     { 0x0202, 0x06 },
0365     { 0x0203, 0x2E },
0366     { 0x0204, 0x00 },
0367     { 0x0205, 0x00 },
0368     { 0x020E, 0x01 },
0369     { 0x020F, 0x00 },
0370     { 0x0210, 0x01 },
0371     { 0x0211, 0x00 },
0372     { 0x0212, 0x01 },
0373     { 0x0213, 0x00 },
0374     { 0x0214, 0x01 },
0375     { 0x0215, 0x00 },
0376     { 0x7BCD, 0x01 },
0377     { 0x94DC, 0x20 },
0378     { 0x94DD, 0x20 },
0379     { 0x94DE, 0x20 },
0380     { 0x95DC, 0x20 },
0381     { 0x95DD, 0x20 },
0382     { 0x95DE, 0x20 },
0383     { 0x7FB0, 0x00 },
0384     { 0x9010, 0x3E },
0385     { 0x9419, 0x50 },
0386     { 0x941B, 0x50 },
0387     { 0x9519, 0x50 },
0388     { 0x951B, 0x50 },
0389     { 0x3030, 0x00 },
0390     { 0x3032, 0x00 },
0391     { 0x0220, 0x00 },
0392 };
0393 
0394 static const struct imx258_reg mode_1048_780_regs[] = {
0395     { 0x0136, 0x13 },
0396     { 0x0137, 0x33 },
0397     { 0x3051, 0x00 },
0398     { 0x3052, 0x00 },
0399     { 0x4E21, 0x14 },
0400     { 0x6B11, 0xCF },
0401     { 0x7FF0, 0x08 },
0402     { 0x7FF1, 0x0F },
0403     { 0x7FF2, 0x08 },
0404     { 0x7FF3, 0x1B },
0405     { 0x7FF4, 0x23 },
0406     { 0x7FF5, 0x60 },
0407     { 0x7FF6, 0x00 },
0408     { 0x7FF7, 0x01 },
0409     { 0x7FF8, 0x00 },
0410     { 0x7FF9, 0x78 },
0411     { 0x7FFA, 0x00 },
0412     { 0x7FFB, 0x00 },
0413     { 0x7FFC, 0x00 },
0414     { 0x7FFD, 0x00 },
0415     { 0x7FFE, 0x00 },
0416     { 0x7FFF, 0x03 },
0417     { 0x7F76, 0x03 },
0418     { 0x7F77, 0xFE },
0419     { 0x7FA8, 0x03 },
0420     { 0x7FA9, 0xFE },
0421     { 0x7B24, 0x81 },
0422     { 0x7B25, 0x00 },
0423     { 0x6564, 0x07 },
0424     { 0x6B0D, 0x41 },
0425     { 0x653D, 0x04 },
0426     { 0x6B05, 0x8C },
0427     { 0x6B06, 0xF9 },
0428     { 0x6B08, 0x65 },
0429     { 0x6B09, 0xFC },
0430     { 0x6B0A, 0xCF },
0431     { 0x6B0B, 0xD2 },
0432     { 0x6700, 0x0E },
0433     { 0x6707, 0x0E },
0434     { 0x9104, 0x00 },
0435     { 0x4648, 0x7F },
0436     { 0x7420, 0x00 },
0437     { 0x7421, 0x1C },
0438     { 0x7422, 0x00 },
0439     { 0x7423, 0xD7 },
0440     { 0x5F04, 0x00 },
0441     { 0x5F05, 0xED },
0442     { 0x0112, 0x0A },
0443     { 0x0113, 0x0A },
0444     { 0x0114, 0x03 },
0445     { 0x0342, 0x14 },
0446     { 0x0343, 0xE8 },
0447     { 0x0340, 0x03 },
0448     { 0x0341, 0x4C },
0449     { 0x0344, 0x00 },
0450     { 0x0345, 0x00 },
0451     { 0x0346, 0x00 },
0452     { 0x0347, 0x00 },
0453     { 0x0348, 0x10 },
0454     { 0x0349, 0x6F },
0455     { 0x034A, 0x0C },
0456     { 0x034B, 0x2E },
0457     { 0x0381, 0x01 },
0458     { 0x0383, 0x01 },
0459     { 0x0385, 0x01 },
0460     { 0x0387, 0x01 },
0461     { 0x0900, 0x01 },
0462     { 0x0901, 0x14 },
0463     { 0x0401, 0x01 },
0464     { 0x0404, 0x00 },
0465     { 0x0405, 0x40 },
0466     { 0x0408, 0x00 },
0467     { 0x0409, 0x06 },
0468     { 0x040A, 0x00 },
0469     { 0x040B, 0x00 },
0470     { 0x040C, 0x10 },
0471     { 0x040D, 0x64 },
0472     { 0x040E, 0x03 },
0473     { 0x040F, 0x0C },
0474     { 0x3038, 0x00 },
0475     { 0x303A, 0x00 },
0476     { 0x303B, 0x10 },
0477     { 0x300D, 0x00 },
0478     { 0x034C, 0x04 },
0479     { 0x034D, 0x18 },
0480     { 0x034E, 0x03 },
0481     { 0x034F, 0x0C },
0482     { 0x0350, 0x01 },
0483     { 0x0202, 0x03 },
0484     { 0x0203, 0x42 },
0485     { 0x0204, 0x00 },
0486     { 0x0205, 0x00 },
0487     { 0x020E, 0x01 },
0488     { 0x020F, 0x00 },
0489     { 0x0210, 0x01 },
0490     { 0x0211, 0x00 },
0491     { 0x0212, 0x01 },
0492     { 0x0213, 0x00 },
0493     { 0x0214, 0x01 },
0494     { 0x0215, 0x00 },
0495     { 0x7BCD, 0x00 },
0496     { 0x94DC, 0x20 },
0497     { 0x94DD, 0x20 },
0498     { 0x94DE, 0x20 },
0499     { 0x95DC, 0x20 },
0500     { 0x95DD, 0x20 },
0501     { 0x95DE, 0x20 },
0502     { 0x7FB0, 0x00 },
0503     { 0x9010, 0x3E },
0504     { 0x9419, 0x50 },
0505     { 0x941B, 0x50 },
0506     { 0x9519, 0x50 },
0507     { 0x951B, 0x50 },
0508     { 0x3030, 0x00 },
0509     { 0x3032, 0x00 },
0510     { 0x0220, 0x00 },
0511 };
0512 
0513 static const char * const imx258_test_pattern_menu[] = {
0514     "Disabled",
0515     "Solid Colour",
0516     "Eight Vertical Colour Bars",
0517     "Colour Bars With Fade to Grey",
0518     "Pseudorandom Sequence (PN9)",
0519 };
0520 
0521 /* Configurations for supported link frequencies */
0522 #define IMX258_LINK_FREQ_634MHZ 633600000ULL
0523 #define IMX258_LINK_FREQ_320MHZ 320000000ULL
0524 
0525 enum {
0526     IMX258_LINK_FREQ_1267MBPS,
0527     IMX258_LINK_FREQ_640MBPS,
0528 };
0529 
0530 /*
0531  * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
0532  * data rate => double data rate; number of lanes => 4; bits per pixel => 10
0533  */
0534 static u64 link_freq_to_pixel_rate(u64 f)
0535 {
0536     f *= 2 * 4;
0537     do_div(f, 10);
0538 
0539     return f;
0540 }
0541 
0542 /* Menu items for LINK_FREQ V4L2 control */
0543 static const s64 link_freq_menu_items[] = {
0544     IMX258_LINK_FREQ_634MHZ,
0545     IMX258_LINK_FREQ_320MHZ,
0546 };
0547 
0548 /* Link frequency configs */
0549 static const struct imx258_link_freq_config link_freq_configs[] = {
0550     [IMX258_LINK_FREQ_1267MBPS] = {
0551         .pixels_per_line = IMX258_PPL_DEFAULT,
0552         .reg_list = {
0553             .num_of_regs = ARRAY_SIZE(mipi_data_rate_1267mbps),
0554             .regs = mipi_data_rate_1267mbps,
0555         }
0556     },
0557     [IMX258_LINK_FREQ_640MBPS] = {
0558         .pixels_per_line = IMX258_PPL_DEFAULT,
0559         .reg_list = {
0560             .num_of_regs = ARRAY_SIZE(mipi_data_rate_640mbps),
0561             .regs = mipi_data_rate_640mbps,
0562         }
0563     },
0564 };
0565 
0566 /* Mode configs */
0567 static const struct imx258_mode supported_modes[] = {
0568     {
0569         .width = 4208,
0570         .height = 3118,
0571         .vts_def = IMX258_VTS_30FPS,
0572         .vts_min = IMX258_VTS_30FPS,
0573         .reg_list = {
0574             .num_of_regs = ARRAY_SIZE(mode_4208x3118_regs),
0575             .regs = mode_4208x3118_regs,
0576         },
0577         .link_freq_index = IMX258_LINK_FREQ_1267MBPS,
0578     },
0579     {
0580         .width = 2104,
0581         .height = 1560,
0582         .vts_def = IMX258_VTS_30FPS_2K,
0583         .vts_min = IMX258_VTS_30FPS_2K,
0584         .reg_list = {
0585             .num_of_regs = ARRAY_SIZE(mode_2104_1560_regs),
0586             .regs = mode_2104_1560_regs,
0587         },
0588         .link_freq_index = IMX258_LINK_FREQ_640MBPS,
0589     },
0590     {
0591         .width = 1048,
0592         .height = 780,
0593         .vts_def = IMX258_VTS_30FPS_VGA,
0594         .vts_min = IMX258_VTS_30FPS_VGA,
0595         .reg_list = {
0596             .num_of_regs = ARRAY_SIZE(mode_1048_780_regs),
0597             .regs = mode_1048_780_regs,
0598         },
0599         .link_freq_index = IMX258_LINK_FREQ_640MBPS,
0600     },
0601 };
0602 
0603 struct imx258 {
0604     struct v4l2_subdev sd;
0605     struct media_pad pad;
0606 
0607     struct v4l2_ctrl_handler ctrl_handler;
0608     /* V4L2 Controls */
0609     struct v4l2_ctrl *link_freq;
0610     struct v4l2_ctrl *pixel_rate;
0611     struct v4l2_ctrl *vblank;
0612     struct v4l2_ctrl *hblank;
0613     struct v4l2_ctrl *exposure;
0614 
0615     /* Current mode */
0616     const struct imx258_mode *cur_mode;
0617 
0618     /*
0619      * Mutex for serialized access:
0620      * Protect sensor module set pad format and start/stop streaming safely.
0621      */
0622     struct mutex mutex;
0623 
0624     /* Streaming on/off */
0625     bool streaming;
0626 
0627     struct clk *clk;
0628 };
0629 
0630 static inline struct imx258 *to_imx258(struct v4l2_subdev *_sd)
0631 {
0632     return container_of(_sd, struct imx258, sd);
0633 }
0634 
0635 /* Read registers up to 2 at a time */
0636 static int imx258_read_reg(struct imx258 *imx258, u16 reg, u32 len, u32 *val)
0637 {
0638     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
0639     struct i2c_msg msgs[2];
0640     u8 addr_buf[2] = { reg >> 8, reg & 0xff };
0641     u8 data_buf[4] = { 0, };
0642     int ret;
0643 
0644     if (len > 4)
0645         return -EINVAL;
0646 
0647     /* Write register address */
0648     msgs[0].addr = client->addr;
0649     msgs[0].flags = 0;
0650     msgs[0].len = ARRAY_SIZE(addr_buf);
0651     msgs[0].buf = addr_buf;
0652 
0653     /* Read data from register */
0654     msgs[1].addr = client->addr;
0655     msgs[1].flags = I2C_M_RD;
0656     msgs[1].len = len;
0657     msgs[1].buf = &data_buf[4 - len];
0658 
0659     ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
0660     if (ret != ARRAY_SIZE(msgs))
0661         return -EIO;
0662 
0663     *val = get_unaligned_be32(data_buf);
0664 
0665     return 0;
0666 }
0667 
0668 /* Write registers up to 2 at a time */
0669 static int imx258_write_reg(struct imx258 *imx258, u16 reg, u32 len, u32 val)
0670 {
0671     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
0672     u8 buf[6];
0673 
0674     if (len > 4)
0675         return -EINVAL;
0676 
0677     put_unaligned_be16(reg, buf);
0678     put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
0679     if (i2c_master_send(client, buf, len + 2) != len + 2)
0680         return -EIO;
0681 
0682     return 0;
0683 }
0684 
0685 /* Write a list of registers */
0686 static int imx258_write_regs(struct imx258 *imx258,
0687                  const struct imx258_reg *regs, u32 len)
0688 {
0689     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
0690     unsigned int i;
0691     int ret;
0692 
0693     for (i = 0; i < len; i++) {
0694         ret = imx258_write_reg(imx258, regs[i].address, 1,
0695                     regs[i].val);
0696         if (ret) {
0697             dev_err_ratelimited(
0698                 &client->dev,
0699                 "Failed to write reg 0x%4.4x. error = %d\n",
0700                 regs[i].address, ret);
0701 
0702             return ret;
0703         }
0704     }
0705 
0706     return 0;
0707 }
0708 
0709 /* Open sub-device */
0710 static int imx258_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
0711 {
0712     struct v4l2_mbus_framefmt *try_fmt =
0713         v4l2_subdev_get_try_format(sd, fh->state, 0);
0714 
0715     /* Initialize try_fmt */
0716     try_fmt->width = supported_modes[0].width;
0717     try_fmt->height = supported_modes[0].height;
0718     try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
0719     try_fmt->field = V4L2_FIELD_NONE;
0720 
0721     return 0;
0722 }
0723 
0724 static int imx258_update_digital_gain(struct imx258 *imx258, u32 len, u32 val)
0725 {
0726     int ret;
0727 
0728     ret = imx258_write_reg(imx258, IMX258_REG_GR_DIGITAL_GAIN,
0729                 IMX258_REG_VALUE_16BIT,
0730                 val);
0731     if (ret)
0732         return ret;
0733     ret = imx258_write_reg(imx258, IMX258_REG_GB_DIGITAL_GAIN,
0734                 IMX258_REG_VALUE_16BIT,
0735                 val);
0736     if (ret)
0737         return ret;
0738     ret = imx258_write_reg(imx258, IMX258_REG_R_DIGITAL_GAIN,
0739                 IMX258_REG_VALUE_16BIT,
0740                 val);
0741     if (ret)
0742         return ret;
0743     ret = imx258_write_reg(imx258, IMX258_REG_B_DIGITAL_GAIN,
0744                 IMX258_REG_VALUE_16BIT,
0745                 val);
0746     if (ret)
0747         return ret;
0748     return 0;
0749 }
0750 
0751 static int imx258_set_ctrl(struct v4l2_ctrl *ctrl)
0752 {
0753     struct imx258 *imx258 =
0754         container_of(ctrl->handler, struct imx258, ctrl_handler);
0755     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
0756     int ret = 0;
0757 
0758     /*
0759      * Applying V4L2 control value only happens
0760      * when power is up for streaming
0761      */
0762     if (pm_runtime_get_if_in_use(&client->dev) == 0)
0763         return 0;
0764 
0765     switch (ctrl->id) {
0766     case V4L2_CID_ANALOGUE_GAIN:
0767         ret = imx258_write_reg(imx258, IMX258_REG_ANALOG_GAIN,
0768                 IMX258_REG_VALUE_16BIT,
0769                 ctrl->val);
0770         break;
0771     case V4L2_CID_EXPOSURE:
0772         ret = imx258_write_reg(imx258, IMX258_REG_EXPOSURE,
0773                 IMX258_REG_VALUE_16BIT,
0774                 ctrl->val);
0775         break;
0776     case V4L2_CID_DIGITAL_GAIN:
0777         ret = imx258_update_digital_gain(imx258, IMX258_REG_VALUE_16BIT,
0778                 ctrl->val);
0779         break;
0780     case V4L2_CID_TEST_PATTERN:
0781         ret = imx258_write_reg(imx258, IMX258_REG_TEST_PATTERN,
0782                 IMX258_REG_VALUE_16BIT,
0783                 ctrl->val);
0784         ret = imx258_write_reg(imx258, REG_MIRROR_FLIP_CONTROL,
0785                 IMX258_REG_VALUE_08BIT,
0786                 !ctrl->val ? REG_CONFIG_MIRROR_FLIP :
0787                 REG_CONFIG_FLIP_TEST_PATTERN);
0788         break;
0789     case V4L2_CID_WIDE_DYNAMIC_RANGE:
0790         if (!ctrl->val) {
0791             ret = imx258_write_reg(imx258, IMX258_REG_HDR,
0792                            IMX258_REG_VALUE_08BIT,
0793                            IMX258_HDR_RATIO_MIN);
0794         } else {
0795             ret = imx258_write_reg(imx258, IMX258_REG_HDR,
0796                            IMX258_REG_VALUE_08BIT,
0797                            IMX258_HDR_ON);
0798             if (ret)
0799                 break;
0800             ret = imx258_write_reg(imx258, IMX258_REG_HDR_RATIO,
0801                            IMX258_REG_VALUE_08BIT,
0802                            BIT(IMX258_HDR_RATIO_MAX));
0803         }
0804         break;
0805     default:
0806         dev_info(&client->dev,
0807              "ctrl(id:0x%x,val:0x%x) is not handled\n",
0808              ctrl->id, ctrl->val);
0809         ret = -EINVAL;
0810         break;
0811     }
0812 
0813     pm_runtime_put(&client->dev);
0814 
0815     return ret;
0816 }
0817 
0818 static const struct v4l2_ctrl_ops imx258_ctrl_ops = {
0819     .s_ctrl = imx258_set_ctrl,
0820 };
0821 
0822 static int imx258_enum_mbus_code(struct v4l2_subdev *sd,
0823                   struct v4l2_subdev_state *sd_state,
0824                   struct v4l2_subdev_mbus_code_enum *code)
0825 {
0826     /* Only one bayer order(GRBG) is supported */
0827     if (code->index > 0)
0828         return -EINVAL;
0829 
0830     code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
0831 
0832     return 0;
0833 }
0834 
0835 static int imx258_enum_frame_size(struct v4l2_subdev *sd,
0836                   struct v4l2_subdev_state *sd_state,
0837                   struct v4l2_subdev_frame_size_enum *fse)
0838 {
0839     if (fse->index >= ARRAY_SIZE(supported_modes))
0840         return -EINVAL;
0841 
0842     if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
0843         return -EINVAL;
0844 
0845     fse->min_width = supported_modes[fse->index].width;
0846     fse->max_width = fse->min_width;
0847     fse->min_height = supported_modes[fse->index].height;
0848     fse->max_height = fse->min_height;
0849 
0850     return 0;
0851 }
0852 
0853 static void imx258_update_pad_format(const struct imx258_mode *mode,
0854                      struct v4l2_subdev_format *fmt)
0855 {
0856     fmt->format.width = mode->width;
0857     fmt->format.height = mode->height;
0858     fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
0859     fmt->format.field = V4L2_FIELD_NONE;
0860 }
0861 
0862 static int __imx258_get_pad_format(struct imx258 *imx258,
0863                    struct v4l2_subdev_state *sd_state,
0864                    struct v4l2_subdev_format *fmt)
0865 {
0866     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
0867         fmt->format = *v4l2_subdev_get_try_format(&imx258->sd,
0868                               sd_state,
0869                               fmt->pad);
0870     else
0871         imx258_update_pad_format(imx258->cur_mode, fmt);
0872 
0873     return 0;
0874 }
0875 
0876 static int imx258_get_pad_format(struct v4l2_subdev *sd,
0877                  struct v4l2_subdev_state *sd_state,
0878                  struct v4l2_subdev_format *fmt)
0879 {
0880     struct imx258 *imx258 = to_imx258(sd);
0881     int ret;
0882 
0883     mutex_lock(&imx258->mutex);
0884     ret = __imx258_get_pad_format(imx258, sd_state, fmt);
0885     mutex_unlock(&imx258->mutex);
0886 
0887     return ret;
0888 }
0889 
0890 static int imx258_set_pad_format(struct v4l2_subdev *sd,
0891                  struct v4l2_subdev_state *sd_state,
0892                  struct v4l2_subdev_format *fmt)
0893 {
0894     struct imx258 *imx258 = to_imx258(sd);
0895     const struct imx258_mode *mode;
0896     struct v4l2_mbus_framefmt *framefmt;
0897     s32 vblank_def;
0898     s32 vblank_min;
0899     s64 h_blank;
0900     s64 pixel_rate;
0901     s64 link_freq;
0902 
0903     mutex_lock(&imx258->mutex);
0904 
0905     /* Only one raw bayer(GBRG) order is supported */
0906     fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
0907 
0908     mode = v4l2_find_nearest_size(supported_modes,
0909         ARRAY_SIZE(supported_modes), width, height,
0910         fmt->format.width, fmt->format.height);
0911     imx258_update_pad_format(mode, fmt);
0912     if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
0913         framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
0914         *framefmt = fmt->format;
0915     } else {
0916         imx258->cur_mode = mode;
0917         __v4l2_ctrl_s_ctrl(imx258->link_freq, mode->link_freq_index);
0918 
0919         link_freq = link_freq_menu_items[mode->link_freq_index];
0920         pixel_rate = link_freq_to_pixel_rate(link_freq);
0921         __v4l2_ctrl_s_ctrl_int64(imx258->pixel_rate, pixel_rate);
0922         /* Update limits and set FPS to default */
0923         vblank_def = imx258->cur_mode->vts_def -
0924                  imx258->cur_mode->height;
0925         vblank_min = imx258->cur_mode->vts_min -
0926                  imx258->cur_mode->height;
0927         __v4l2_ctrl_modify_range(
0928             imx258->vblank, vblank_min,
0929             IMX258_VTS_MAX - imx258->cur_mode->height, 1,
0930             vblank_def);
0931         __v4l2_ctrl_s_ctrl(imx258->vblank, vblank_def);
0932         h_blank =
0933             link_freq_configs[mode->link_freq_index].pixels_per_line
0934              - imx258->cur_mode->width;
0935         __v4l2_ctrl_modify_range(imx258->hblank, h_blank,
0936                      h_blank, 1, h_blank);
0937     }
0938 
0939     mutex_unlock(&imx258->mutex);
0940 
0941     return 0;
0942 }
0943 
0944 /* Start streaming */
0945 static int imx258_start_streaming(struct imx258 *imx258)
0946 {
0947     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
0948     const struct imx258_reg_list *reg_list;
0949     int ret, link_freq_index;
0950 
0951     /* Setup PLL */
0952     link_freq_index = imx258->cur_mode->link_freq_index;
0953     reg_list = &link_freq_configs[link_freq_index].reg_list;
0954     ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
0955     if (ret) {
0956         dev_err(&client->dev, "%s failed to set plls\n", __func__);
0957         return ret;
0958     }
0959 
0960     /* Apply default values of current mode */
0961     reg_list = &imx258->cur_mode->reg_list;
0962     ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
0963     if (ret) {
0964         dev_err(&client->dev, "%s failed to set mode\n", __func__);
0965         return ret;
0966     }
0967 
0968     /* Set Orientation be 180 degree */
0969     ret = imx258_write_reg(imx258, REG_MIRROR_FLIP_CONTROL,
0970                    IMX258_REG_VALUE_08BIT, REG_CONFIG_MIRROR_FLIP);
0971     if (ret) {
0972         dev_err(&client->dev, "%s failed to set orientation\n",
0973             __func__);
0974         return ret;
0975     }
0976 
0977     /* Apply customized values from user */
0978     ret =  __v4l2_ctrl_handler_setup(imx258->sd.ctrl_handler);
0979     if (ret)
0980         return ret;
0981 
0982     /* set stream on register */
0983     return imx258_write_reg(imx258, IMX258_REG_MODE_SELECT,
0984                 IMX258_REG_VALUE_08BIT,
0985                 IMX258_MODE_STREAMING);
0986 }
0987 
0988 /* Stop streaming */
0989 static int imx258_stop_streaming(struct imx258 *imx258)
0990 {
0991     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
0992     int ret;
0993 
0994     /* set stream off register */
0995     ret = imx258_write_reg(imx258, IMX258_REG_MODE_SELECT,
0996         IMX258_REG_VALUE_08BIT, IMX258_MODE_STANDBY);
0997     if (ret)
0998         dev_err(&client->dev, "%s failed to set stream\n", __func__);
0999 
1000     /*
1001      * Return success even if it was an error, as there is nothing the
1002      * caller can do about it.
1003      */
1004     return 0;
1005 }
1006 
1007 static int imx258_power_on(struct device *dev)
1008 {
1009     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1010     struct imx258 *imx258 = to_imx258(sd);
1011     int ret;
1012 
1013     ret = clk_prepare_enable(imx258->clk);
1014     if (ret)
1015         dev_err(dev, "failed to enable clock\n");
1016 
1017     return ret;
1018 }
1019 
1020 static int imx258_power_off(struct device *dev)
1021 {
1022     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1023     struct imx258 *imx258 = to_imx258(sd);
1024 
1025     clk_disable_unprepare(imx258->clk);
1026 
1027     return 0;
1028 }
1029 
1030 static int imx258_set_stream(struct v4l2_subdev *sd, int enable)
1031 {
1032     struct imx258 *imx258 = to_imx258(sd);
1033     struct i2c_client *client = v4l2_get_subdevdata(sd);
1034     int ret = 0;
1035 
1036     mutex_lock(&imx258->mutex);
1037     if (imx258->streaming == enable) {
1038         mutex_unlock(&imx258->mutex);
1039         return 0;
1040     }
1041 
1042     if (enable) {
1043         ret = pm_runtime_resume_and_get(&client->dev);
1044         if (ret < 0)
1045             goto err_unlock;
1046 
1047         /*
1048          * Apply default & customized values
1049          * and then start streaming.
1050          */
1051         ret = imx258_start_streaming(imx258);
1052         if (ret)
1053             goto err_rpm_put;
1054     } else {
1055         imx258_stop_streaming(imx258);
1056         pm_runtime_put(&client->dev);
1057     }
1058 
1059     imx258->streaming = enable;
1060     mutex_unlock(&imx258->mutex);
1061 
1062     return ret;
1063 
1064 err_rpm_put:
1065     pm_runtime_put(&client->dev);
1066 err_unlock:
1067     mutex_unlock(&imx258->mutex);
1068 
1069     return ret;
1070 }
1071 
1072 static int __maybe_unused imx258_suspend(struct device *dev)
1073 {
1074     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1075     struct imx258 *imx258 = to_imx258(sd);
1076 
1077     if (imx258->streaming)
1078         imx258_stop_streaming(imx258);
1079 
1080     return 0;
1081 }
1082 
1083 static int __maybe_unused imx258_resume(struct device *dev)
1084 {
1085     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1086     struct imx258 *imx258 = to_imx258(sd);
1087     int ret;
1088 
1089     if (imx258->streaming) {
1090         ret = imx258_start_streaming(imx258);
1091         if (ret)
1092             goto error;
1093     }
1094 
1095     return 0;
1096 
1097 error:
1098     imx258_stop_streaming(imx258);
1099     imx258->streaming = 0;
1100     return ret;
1101 }
1102 
1103 /* Verify chip ID */
1104 static int imx258_identify_module(struct imx258 *imx258)
1105 {
1106     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
1107     int ret;
1108     u32 val;
1109 
1110     ret = imx258_read_reg(imx258, IMX258_REG_CHIP_ID,
1111                   IMX258_REG_VALUE_16BIT, &val);
1112     if (ret) {
1113         dev_err(&client->dev, "failed to read chip id %x\n",
1114             IMX258_CHIP_ID);
1115         return ret;
1116     }
1117 
1118     if (val != IMX258_CHIP_ID) {
1119         dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1120             IMX258_CHIP_ID, val);
1121         return -EIO;
1122     }
1123 
1124     return 0;
1125 }
1126 
1127 static const struct v4l2_subdev_video_ops imx258_video_ops = {
1128     .s_stream = imx258_set_stream,
1129 };
1130 
1131 static const struct v4l2_subdev_pad_ops imx258_pad_ops = {
1132     .enum_mbus_code = imx258_enum_mbus_code,
1133     .get_fmt = imx258_get_pad_format,
1134     .set_fmt = imx258_set_pad_format,
1135     .enum_frame_size = imx258_enum_frame_size,
1136 };
1137 
1138 static const struct v4l2_subdev_ops imx258_subdev_ops = {
1139     .video = &imx258_video_ops,
1140     .pad = &imx258_pad_ops,
1141 };
1142 
1143 static const struct v4l2_subdev_internal_ops imx258_internal_ops = {
1144     .open = imx258_open,
1145 };
1146 
1147 /* Initialize control handlers */
1148 static int imx258_init_controls(struct imx258 *imx258)
1149 {
1150     struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
1151     struct v4l2_ctrl_handler *ctrl_hdlr;
1152     s64 vblank_def;
1153     s64 vblank_min;
1154     s64 pixel_rate_min;
1155     s64 pixel_rate_max;
1156     int ret;
1157 
1158     ctrl_hdlr = &imx258->ctrl_handler;
1159     ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
1160     if (ret)
1161         return ret;
1162 
1163     mutex_init(&imx258->mutex);
1164     ctrl_hdlr->lock = &imx258->mutex;
1165     imx258->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1166                 &imx258_ctrl_ops,
1167                 V4L2_CID_LINK_FREQ,
1168                 ARRAY_SIZE(link_freq_menu_items) - 1,
1169                 0,
1170                 link_freq_menu_items);
1171 
1172     if (imx258->link_freq)
1173         imx258->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1174 
1175     pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1176     pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1177     /* By default, PIXEL_RATE is read only */
1178     imx258->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
1179                 V4L2_CID_PIXEL_RATE,
1180                 pixel_rate_min, pixel_rate_max,
1181                 1, pixel_rate_max);
1182 
1183 
1184     vblank_def = imx258->cur_mode->vts_def - imx258->cur_mode->height;
1185     vblank_min = imx258->cur_mode->vts_min - imx258->cur_mode->height;
1186     imx258->vblank = v4l2_ctrl_new_std(
1187                 ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_VBLANK,
1188                 vblank_min,
1189                 IMX258_VTS_MAX - imx258->cur_mode->height, 1,
1190                 vblank_def);
1191 
1192     if (imx258->vblank)
1193         imx258->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1194 
1195     imx258->hblank = v4l2_ctrl_new_std(
1196                 ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_HBLANK,
1197                 IMX258_PPL_DEFAULT - imx258->cur_mode->width,
1198                 IMX258_PPL_DEFAULT - imx258->cur_mode->width,
1199                 1,
1200                 IMX258_PPL_DEFAULT - imx258->cur_mode->width);
1201 
1202     if (imx258->hblank)
1203         imx258->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1204 
1205     imx258->exposure = v4l2_ctrl_new_std(
1206                 ctrl_hdlr, &imx258_ctrl_ops,
1207                 V4L2_CID_EXPOSURE, IMX258_EXPOSURE_MIN,
1208                 IMX258_EXPOSURE_MAX, IMX258_EXPOSURE_STEP,
1209                 IMX258_EXPOSURE_DEFAULT);
1210 
1211     v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1212                 IMX258_ANA_GAIN_MIN, IMX258_ANA_GAIN_MAX,
1213                 IMX258_ANA_GAIN_STEP, IMX258_ANA_GAIN_DEFAULT);
1214 
1215     v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1216                 IMX258_DGTL_GAIN_MIN, IMX258_DGTL_GAIN_MAX,
1217                 IMX258_DGTL_GAIN_STEP,
1218                 IMX258_DGTL_GAIN_DEFAULT);
1219 
1220     v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_WIDE_DYNAMIC_RANGE,
1221                 0, 1, 1, IMX258_HDR_RATIO_DEFAULT);
1222 
1223     v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx258_ctrl_ops,
1224                 V4L2_CID_TEST_PATTERN,
1225                 ARRAY_SIZE(imx258_test_pattern_menu) - 1,
1226                 0, 0, imx258_test_pattern_menu);
1227 
1228     if (ctrl_hdlr->error) {
1229         ret = ctrl_hdlr->error;
1230         dev_err(&client->dev, "%s control init failed (%d)\n",
1231                 __func__, ret);
1232         goto error;
1233     }
1234 
1235     imx258->sd.ctrl_handler = ctrl_hdlr;
1236 
1237     return 0;
1238 
1239 error:
1240     v4l2_ctrl_handler_free(ctrl_hdlr);
1241     mutex_destroy(&imx258->mutex);
1242 
1243     return ret;
1244 }
1245 
1246 static void imx258_free_controls(struct imx258 *imx258)
1247 {
1248     v4l2_ctrl_handler_free(imx258->sd.ctrl_handler);
1249     mutex_destroy(&imx258->mutex);
1250 }
1251 
1252 static int imx258_probe(struct i2c_client *client)
1253 {
1254     struct imx258 *imx258;
1255     int ret;
1256     u32 val = 0;
1257 
1258     imx258 = devm_kzalloc(&client->dev, sizeof(*imx258), GFP_KERNEL);
1259     if (!imx258)
1260         return -ENOMEM;
1261 
1262     imx258->clk = devm_clk_get_optional(&client->dev, NULL);
1263     if (IS_ERR(imx258->clk))
1264         return dev_err_probe(&client->dev, PTR_ERR(imx258->clk),
1265                      "error getting clock\n");
1266     if (!imx258->clk) {
1267         dev_dbg(&client->dev,
1268             "no clock provided, using clock-frequency property\n");
1269 
1270         device_property_read_u32(&client->dev, "clock-frequency", &val);
1271     } else {
1272         val = clk_get_rate(imx258->clk);
1273     }
1274     if (val != IMX258_INPUT_CLOCK_FREQ) {
1275         dev_err(&client->dev, "input clock frequency not supported\n");
1276         return -EINVAL;
1277     }
1278 
1279     /*
1280      * Check that the device is mounted upside down. The driver only
1281      * supports a single pixel order right now.
1282      */
1283     ret = device_property_read_u32(&client->dev, "rotation", &val);
1284     if (ret || val != 180)
1285         return -EINVAL;
1286 
1287     /* Initialize subdev */
1288     v4l2_i2c_subdev_init(&imx258->sd, client, &imx258_subdev_ops);
1289 
1290     /* Will be powered off via pm_runtime_idle */
1291     ret = imx258_power_on(&client->dev);
1292     if (ret)
1293         return ret;
1294 
1295     /* Check module identity */
1296     ret = imx258_identify_module(imx258);
1297     if (ret)
1298         goto error_identify;
1299 
1300     /* Set default mode to max resolution */
1301     imx258->cur_mode = &supported_modes[0];
1302 
1303     ret = imx258_init_controls(imx258);
1304     if (ret)
1305         goto error_identify;
1306 
1307     /* Initialize subdev */
1308     imx258->sd.internal_ops = &imx258_internal_ops;
1309     imx258->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1310     imx258->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1311 
1312     /* Initialize source pad */
1313     imx258->pad.flags = MEDIA_PAD_FL_SOURCE;
1314 
1315     ret = media_entity_pads_init(&imx258->sd.entity, 1, &imx258->pad);
1316     if (ret)
1317         goto error_handler_free;
1318 
1319     ret = v4l2_async_register_subdev_sensor(&imx258->sd);
1320     if (ret < 0)
1321         goto error_media_entity;
1322 
1323     pm_runtime_set_active(&client->dev);
1324     pm_runtime_enable(&client->dev);
1325     pm_runtime_idle(&client->dev);
1326 
1327     return 0;
1328 
1329 error_media_entity:
1330     media_entity_cleanup(&imx258->sd.entity);
1331 
1332 error_handler_free:
1333     imx258_free_controls(imx258);
1334 
1335 error_identify:
1336     imx258_power_off(&client->dev);
1337 
1338     return ret;
1339 }
1340 
1341 static int imx258_remove(struct i2c_client *client)
1342 {
1343     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1344     struct imx258 *imx258 = to_imx258(sd);
1345 
1346     v4l2_async_unregister_subdev(sd);
1347     media_entity_cleanup(&sd->entity);
1348     imx258_free_controls(imx258);
1349 
1350     pm_runtime_disable(&client->dev);
1351     if (!pm_runtime_status_suspended(&client->dev))
1352         imx258_power_off(&client->dev);
1353     pm_runtime_set_suspended(&client->dev);
1354 
1355     return 0;
1356 }
1357 
1358 static const struct dev_pm_ops imx258_pm_ops = {
1359     SET_SYSTEM_SLEEP_PM_OPS(imx258_suspend, imx258_resume)
1360     SET_RUNTIME_PM_OPS(imx258_power_off, imx258_power_on, NULL)
1361 };
1362 
1363 #ifdef CONFIG_ACPI
1364 static const struct acpi_device_id imx258_acpi_ids[] = {
1365     { "SONY258A" },
1366     { /* sentinel */ }
1367 };
1368 
1369 MODULE_DEVICE_TABLE(acpi, imx258_acpi_ids);
1370 #endif
1371 
1372 static const struct of_device_id imx258_dt_ids[] = {
1373     { .compatible = "sony,imx258" },
1374     { /* sentinel */ }
1375 };
1376 MODULE_DEVICE_TABLE(of, imx258_dt_ids);
1377 
1378 static struct i2c_driver imx258_i2c_driver = {
1379     .driver = {
1380         .name = "imx258",
1381         .pm = &imx258_pm_ops,
1382         .acpi_match_table = ACPI_PTR(imx258_acpi_ids),
1383         .of_match_table = imx258_dt_ids,
1384     },
1385     .probe_new = imx258_probe,
1386     .remove = imx258_remove,
1387 };
1388 
1389 module_i2c_driver(imx258_i2c_driver);
1390 
1391 MODULE_AUTHOR("Yeh, Andy <andy.yeh@intel.com>");
1392 MODULE_AUTHOR("Chiang, Alan");
1393 MODULE_AUTHOR("Chen, Jason");
1394 MODULE_DESCRIPTION("Sony IMX258 sensor driver");
1395 MODULE_LICENSE("GPL v2");
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