media/i2c/dw9768.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2020 MediaTek Inc.
0003
0004 #include <linux/delay.h>
0005 #include <linux/i2c.h>
0006 #include <linux/module.h>
0007 #include <linux/pm_runtime.h>
0008 #include <linux/regulator/consumer.h>
0009 #include <media/v4l2-async.h>
0010 #include <media/v4l2-ctrls.h>
0011 #include <media/v4l2-device.h>
0012 #include <media/v4l2-fwnode.h>
0013 #include <media/v4l2-subdev.h>
0014
0015 #define DW9768_NAME             "dw9768"
0016 #define DW9768_MAX_FOCUS_POS            (1024 - 1)
0017 /*
0018  * This sets the minimum granularity for the focus positions.
0019  * A value of 1 gives maximum accuracy for a desired focus position
0020  */
0021 #define DW9768_FOCUS_STEPS          1
0022
0023 /*
0024  * Ring control and Power control register
0025  * Bit[1] RING_EN
0026  * 0: Direct mode
0027  * 1: AAC mode (ringing control mode)
0028  * Bit[0] PD
0029  * 0: Normal operation mode
0030  * 1: Power down mode
0031  * DW9768 requires waiting time of Topr after PD reset takes place.
0032  */
0033 #define DW9768_RING_PD_CONTROL_REG      0x02
0034 #define DW9768_PD_MODE_OFF          0x00
0035 #define DW9768_PD_MODE_EN           BIT(0)
0036 #define DW9768_AAC_MODE_EN          BIT(1)
0037
0038 /*
0039  * DW9768 separates two registers to control the VCM position.
0040  * One for MSB value, another is LSB value.
0041  * DAC_MSB: D[9:8] (ADD: 0x03)
0042  * DAC_LSB: D[7:0] (ADD: 0x04)
0043  * D[9:0] DAC data input: positive output current = D[9:0] / 1023 * 100[mA]
0044  */
0045 #define DW9768_MSB_ADDR             0x03
0046 #define DW9768_LSB_ADDR             0x04
0047 #define DW9768_STATUS_ADDR          0x05
0048
0049 /*
0050  * AAC mode control & prescale register
0051  * Bit[7:5] Namely AC[2:0], decide the VCM mode and operation time.
0052  * 001 AAC2 0.48 x Tvib
0053  * 010 AAC3 0.70 x Tvib
0054  * 011 AAC4 0.75 x Tvib
0055  * 101 AAC8 1.13 x Tvib
0056  * Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow.
0057  * 000 2
0058  * 001 1
0059  * 010 1/2
0060  * 011 1/4
0061  * 100 8
0062  * 101 4
0063  */
0064 #define DW9768_AAC_PRESC_REG            0x06
0065 #define DW9768_AAC_MODE_SEL_MASK        GENMASK(7, 5)
0066 #define DW9768_CLOCK_PRE_SCALE_SEL_MASK     GENMASK(2, 0)
0067
0068 /*
0069  * VCM period of vibration register
0070  * Bit[5:0] Defined as VCM rising periodic time (Tvib) together with PRESC[2:0]
0071  * Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate
0072  * Dividing Rate is the internal clock dividing rate that is defined at
0073  * PRESCALE register (ADD: 0x06)
0074  */
0075 #define DW9768_AAC_TIME_REG         0x07
0076
0077 /*
0078  * DW9768 requires waiting time (delay time) of t_OPR after power-up,
0079  * or in the case of PD reset taking place.
0080  */
0081 #define DW9768_T_OPR_US             1000
0082 #define DW9768_TVIB_MS_BASE10           (64 - 1)
0083 #define DW9768_AAC_MODE_DEFAULT         2
0084 #define DW9768_AAC_TIME_DEFAULT         0x20
0085 #define DW9768_CLOCK_PRE_SCALE_DEFAULT      1
0086
0087 /*
0088  * This acts as the minimum granularity of lens movement.
0089  * Keep this value power of 2, so the control steps can be
0090  * uniformly adjusted for gradual lens movement, with desired
0091  * number of control steps.
0092  */
0093 #define DW9768_MOVE_STEPS           16
0094
0095 static const char * const dw9768_supply_names[] = {
0096     "vin",  /* Digital I/O power */
0097     "vdd",  /* Digital core power */
0098 };
0099
0100 /* dw9768 device structure */
0101 struct dw9768 {
0102     struct regulator_bulk_data supplies[ARRAY_SIZE(dw9768_supply_names)];
0103     struct v4l2_ctrl_handler ctrls;
0104     struct v4l2_ctrl *focus;
0105     struct v4l2_subdev sd;
0106
0107     u32 aac_mode;
0108     u32 aac_timing;
0109     u32 clock_presc;
0110     u32 move_delay_us;
0111 };
0112
0113 static inline struct dw9768 *sd_to_dw9768(struct v4l2_subdev *subdev)
0114 {
0115     return container_of(subdev, struct dw9768, sd);
0116 }
0117
0118 struct regval_list {
0119     u8 reg_num;
0120     u8 value;
0121 };
0122
0123 struct dw9768_aac_mode_ot_multi {
0124     u32 aac_mode_enum;
0125     u32 ot_multi_base100;
0126 };
0127
0128 struct dw9768_clk_presc_dividing_rate {
0129     u32 clk_presc_enum;
0130     u32 dividing_rate_base100;
0131 };
0132
0133 static const struct dw9768_aac_mode_ot_multi aac_mode_ot_multi[] = {
0134     {1,  48},
0135     {2,  70},
0136     {3,  75},
0137     {5, 113},
0138 };
0139
0140 static const struct dw9768_clk_presc_dividing_rate presc_dividing_rate[] = {
0141     {0, 200},
0142     {1, 100},
0143     {2,  50},
0144     {3,  25},
0145     {4, 800},
0146     {5, 400},
0147 };
0148
0149 static u32 dw9768_find_ot_multi(u32 aac_mode_param)
0150 {
0151     u32 cur_ot_multi_base100 = 70;
0152     unsigned int i;
0153
0154     for (i = 0; i < ARRAY_SIZE(aac_mode_ot_multi); i++) {
0155         if (aac_mode_ot_multi[i].aac_mode_enum == aac_mode_param) {
0156             cur_ot_multi_base100 =
0157                 aac_mode_ot_multi[i].ot_multi_base100;
0158         }
0159     }
0160
0161     return cur_ot_multi_base100;
0162 }
0163
0164 static u32 dw9768_find_dividing_rate(u32 presc_param)
0165 {
0166     u32 cur_clk_dividing_rate_base100 = 100;
0167     unsigned int i;
0168
0169     for (i = 0; i < ARRAY_SIZE(presc_dividing_rate); i++) {
0170         if (presc_dividing_rate[i].clk_presc_enum == presc_param) {
0171             cur_clk_dividing_rate_base100 =
0172                 presc_dividing_rate[i].dividing_rate_base100;
0173         }
0174     }
0175
0176     return cur_clk_dividing_rate_base100;
0177 }
0178
0179 /*
0180  * DW9768_AAC_PRESC_REG & DW9768_AAC_TIME_REG determine VCM operation time.
0181  * For current VCM mode: AAC3, Operation Time would be 0.70 x Tvib.
0182  * Tvib = (6.3ms + AACT[5:0] * 0.1MS) * Dividing Rate.
0183  * Below is calculation of the operation delay for each step.
0184  */
0185 static inline u32 dw9768_cal_move_delay(u32 aac_mode_param, u32 presc_param,
0186                     u32 aac_timing_param)
0187 {
0188     u32 Tvib_us;
0189     u32 ot_multi_base100;
0190     u32 clk_dividing_rate_base100;
0191
0192     ot_multi_base100 = dw9768_find_ot_multi(aac_mode_param);
0193
0194     clk_dividing_rate_base100 = dw9768_find_dividing_rate(presc_param);
0195
0196     Tvib_us = (DW9768_TVIB_MS_BASE10 + aac_timing_param) *
0197           clk_dividing_rate_base100;
0198
0199     return Tvib_us * ot_multi_base100 / 100;
0200 }
0201
0202 static int dw9768_mod_reg(struct dw9768 *dw9768, u8 reg, u8 mask, u8 val)
0203 {
0204     struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
0205     int ret;
0206
0207     ret = i2c_smbus_read_byte_data(client, reg);
0208     if (ret < 0)
0209         return ret;
0210
0211     val = ((unsigned char)ret & ~mask) | (val & mask);
0212
0213     return i2c_smbus_write_byte_data(client, reg, val);
0214 }
0215
0216 static int dw9768_set_dac(struct dw9768 *dw9768, u16 val)
0217 {
0218     struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
0219
0220     /* Write VCM position to registers */
0221     return i2c_smbus_write_word_swapped(client, DW9768_MSB_ADDR, val);
0222 }
0223
0224 static int dw9768_init(struct dw9768 *dw9768)
0225 {
0226     struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
0227     int ret, val;
0228
0229     /* Reset DW9768_RING_PD_CONTROL_REG to default status 0x00 */
0230     ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
0231                     DW9768_PD_MODE_OFF);
0232     if (ret < 0)
0233         return ret;
0234
0235     /*
0236      * DW9769 requires waiting delay time of t_OPR
0237      * after PD reset takes place.
0238      */
0239     usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
0240
0241     /* Set DW9768_RING_PD_CONTROL_REG to DW9768_AAC_MODE_EN(0x01) */
0242     ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
0243                     DW9768_AAC_MODE_EN);
0244     if (ret < 0)
0245         return ret;
0246
0247     /* Set AAC mode */
0248     ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
0249                  DW9768_AAC_MODE_SEL_MASK,
0250                  dw9768->aac_mode << 5);
0251     if (ret < 0)
0252         return ret;
0253
0254     /* Set clock presc */
0255     if (dw9768->clock_presc != DW9768_CLOCK_PRE_SCALE_DEFAULT) {
0256         ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
0257                      DW9768_CLOCK_PRE_SCALE_SEL_MASK,
0258                      dw9768->clock_presc);
0259         if (ret < 0)
0260             return ret;
0261     }
0262
0263     /* Set AAC Timing */
0264     if (dw9768->aac_timing != DW9768_AAC_TIME_DEFAULT) {
0265         ret = i2c_smbus_write_byte_data(client, DW9768_AAC_TIME_REG,
0266                         dw9768->aac_timing);
0267         if (ret < 0)
0268             return ret;
0269     }
0270
0271     for (val = dw9768->focus->val % DW9768_MOVE_STEPS;
0272          val <= dw9768->focus->val;
0273          val += DW9768_MOVE_STEPS) {
0274         ret = dw9768_set_dac(dw9768, val);
0275         if (ret) {
0276             dev_err(&client->dev, "I2C failure: %d", ret);
0277             return ret;
0278         }
0279         usleep_range(dw9768->move_delay_us,
0280                  dw9768->move_delay_us + 1000);
0281     }
0282
0283     return 0;
0284 }
0285
0286 static int dw9768_release(struct dw9768 *dw9768)
0287 {
0288     struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
0289     int ret, val;
0290
0291     val = round_down(dw9768->focus->val, DW9768_MOVE_STEPS);
0292     for ( ; val >= 0; val -= DW9768_MOVE_STEPS) {
0293         ret = dw9768_set_dac(dw9768, val);
0294         if (ret) {
0295             dev_err(&client->dev, "I2C write fail: %d", ret);
0296             return ret;
0297         }
0298         usleep_range(dw9768->move_delay_us,
0299                  dw9768->move_delay_us + 1000);
0300     }
0301
0302     ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
0303                     DW9768_PD_MODE_EN);
0304     if (ret < 0)
0305         return ret;
0306
0307     /*
0308      * DW9769 requires waiting delay time of t_OPR
0309      * after PD reset takes place.
0310      */
0311     usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
0312
0313     return 0;
0314 }
0315
0316 static int dw9768_runtime_suspend(struct device *dev)
0317 {
0318     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0319     struct dw9768 *dw9768 = sd_to_dw9768(sd);
0320
0321     dw9768_release(dw9768);
0322     regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
0323                    dw9768->supplies);
0324
0325     return 0;
0326 }
0327
0328 static int dw9768_runtime_resume(struct device *dev)
0329 {
0330     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0331     struct dw9768 *dw9768 = sd_to_dw9768(sd);
0332     int ret;
0333
0334     ret = regulator_bulk_enable(ARRAY_SIZE(dw9768_supply_names),
0335                     dw9768->supplies);
0336     if (ret < 0) {
0337         dev_err(dev, "failed to enable regulators\n");
0338         return ret;
0339     }
0340
0341     /*
0342      * The datasheet refers to t_OPR that needs to be waited before sending
0343      * I2C commands after power-up.
0344      */
0345     usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
0346
0347     ret = dw9768_init(dw9768);
0348     if (ret < 0)
0349         goto disable_regulator;
0350
0351     return 0;
0352
0353 disable_regulator:
0354     regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
0355                    dw9768->supplies);
0356
0357     return ret;
0358 }
0359
0360 static int dw9768_set_ctrl(struct v4l2_ctrl *ctrl)
0361 {
0362     struct dw9768 *dw9768 = container_of(ctrl->handler,
0363                          struct dw9768, ctrls);
0364
0365     if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE)
0366         return dw9768_set_dac(dw9768, ctrl->val);
0367
0368     return 0;
0369 }
0370
0371 static const struct v4l2_ctrl_ops dw9768_ctrl_ops = {
0372     .s_ctrl = dw9768_set_ctrl,
0373 };
0374
0375 static int dw9768_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
0376 {
0377     return pm_runtime_resume_and_get(sd->dev);
0378 }
0379
0380 static int dw9768_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
0381 {
0382     pm_runtime_put(sd->dev);
0383
0384     return 0;
0385 }
0386
0387 static const struct v4l2_subdev_internal_ops dw9768_int_ops = {
0388     .open = dw9768_open,
0389     .close = dw9768_close,
0390 };
0391
0392 static const struct v4l2_subdev_ops dw9768_ops = { };
0393
0394 static int dw9768_init_controls(struct dw9768 *dw9768)
0395 {
0396     struct v4l2_ctrl_handler *hdl = &dw9768->ctrls;
0397     const struct v4l2_ctrl_ops *ops = &dw9768_ctrl_ops;
0398
0399     v4l2_ctrl_handler_init(hdl, 1);
0400
0401     dw9768->focus = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE, 0,
0402                       DW9768_MAX_FOCUS_POS,
0403                       DW9768_FOCUS_STEPS, 0);
0404
0405     if (hdl->error)
0406         return hdl->error;
0407
0408     dw9768->sd.ctrl_handler = hdl;
0409
0410     return 0;
0411 }
0412
0413 static int dw9768_probe(struct i2c_client *client)
0414 {
0415     struct device *dev = &client->dev;
0416     struct dw9768 *dw9768;
0417     unsigned int i;
0418     int ret;
0419
0420     dw9768 = devm_kzalloc(dev, sizeof(*dw9768), GFP_KERNEL);
0421     if (!dw9768)
0422         return -ENOMEM;
0423
0424     /* Initialize subdev */
0425     v4l2_i2c_subdev_init(&dw9768->sd, client, &dw9768_ops);
0426
0427     dw9768->aac_mode = DW9768_AAC_MODE_DEFAULT;
0428     dw9768->aac_timing = DW9768_AAC_TIME_DEFAULT;
0429     dw9768->clock_presc = DW9768_CLOCK_PRE_SCALE_DEFAULT;
0430
0431     /* Optional indication of AAC mode select */
0432     fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-mode",
0433                  &dw9768->aac_mode);
0434
0435     /* Optional indication of clock pre-scale select */
0436     fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,clock-presc",
0437                  &dw9768->clock_presc);
0438
0439     /* Optional indication of AAC Timing */
0440     fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-timing",
0441                  &dw9768->aac_timing);
0442
0443     dw9768->move_delay_us = dw9768_cal_move_delay(dw9768->aac_mode,
0444                               dw9768->clock_presc,
0445                               dw9768->aac_timing);
0446
0447     for (i = 0; i < ARRAY_SIZE(dw9768_supply_names); i++)
0448         dw9768->supplies[i].supply = dw9768_supply_names[i];
0449
0450     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dw9768_supply_names),
0451                       dw9768->supplies);
0452     if (ret) {
0453         dev_err(dev, "failed to get regulators\n");
0454         return ret;
0455     }
0456
0457     /* Initialize controls */
0458     ret = dw9768_init_controls(dw9768);
0459     if (ret)
0460         goto err_free_handler;
0461
0462     /* Initialize subdev */
0463     dw9768->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
0464     dw9768->sd.internal_ops = &dw9768_int_ops;
0465
0466     ret = media_entity_pads_init(&dw9768->sd.entity, 0, NULL);
0467     if (ret < 0)
0468         goto err_free_handler;
0469
0470     dw9768->sd.entity.function = MEDIA_ENT_F_LENS;
0471
0472     pm_runtime_enable(dev);
0473     if (!pm_runtime_enabled(dev)) {
0474         ret = dw9768_runtime_resume(dev);
0475         if (ret < 0) {
0476             dev_err(dev, "failed to power on: %d\n", ret);
0477             goto err_clean_entity;
0478         }
0479     }
0480
0481     ret = v4l2_async_register_subdev(&dw9768->sd);
0482     if (ret < 0) {
0483         dev_err(dev, "failed to register V4L2 subdev: %d", ret);
0484         goto err_power_off;
0485     }
0486
0487     return 0;
0488
0489 err_power_off:
0490     if (pm_runtime_enabled(dev))
0491         pm_runtime_disable(dev);
0492     else
0493         dw9768_runtime_suspend(dev);
0494 err_clean_entity:
0495     media_entity_cleanup(&dw9768->sd.entity);
0496 err_free_handler:
0497     v4l2_ctrl_handler_free(&dw9768->ctrls);
0498
0499     return ret;
0500 }
0501
0502 static int dw9768_remove(struct i2c_client *client)
0503 {
0504     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0505     struct dw9768 *dw9768 = sd_to_dw9768(sd);
0506
0507     v4l2_async_unregister_subdev(&dw9768->sd);
0508     v4l2_ctrl_handler_free(&dw9768->ctrls);
0509     media_entity_cleanup(&dw9768->sd.entity);
0510     pm_runtime_disable(&client->dev);
0511     if (!pm_runtime_status_suspended(&client->dev))
0512         dw9768_runtime_suspend(&client->dev);
0513     pm_runtime_set_suspended(&client->dev);
0514
0515     return 0;
0516 }
0517
0518 static const struct of_device_id dw9768_of_table[] = {
0519     { .compatible = "dongwoon,dw9768" },
0520     { .compatible = "giantec,gt9769" },
0521     {}
0522 };
0523 MODULE_DEVICE_TABLE(of, dw9768_of_table);
0524
0525 static const struct dev_pm_ops dw9768_pm_ops = {
0526     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0527                 pm_runtime_force_resume)
0528     SET_RUNTIME_PM_OPS(dw9768_runtime_suspend, dw9768_runtime_resume, NULL)
0529 };
0530
0531 static struct i2c_driver dw9768_i2c_driver = {
0532     .driver = {
0533         .name = DW9768_NAME,
0534         .pm = &dw9768_pm_ops,
0535         .of_match_table = dw9768_of_table,
0536     },
0537     .probe_new  = dw9768_probe,
0538     .remove = dw9768_remove,
0539 };
0540 module_i2c_driver(dw9768_i2c_driver);
0541
0542 MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
0543 MODULE_DESCRIPTION("DW9768 VCM driver");
0544 MODULE_LICENSE("GPL v2");