i2c/ccs/ccs-limits.c

0001 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
0002 /* Copyright (C) 2019--2020 Intel Corporation */
0003 /*
0004  * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
0005  * do not modify.
0006  */
0007
0008 #include "ccs-limits.h"
0009 #include "ccs-regs.h"
0010
0011 const struct ccs_limit ccs_limits[] = {
0012     { CCS_R_FRAME_FORMAT_MODEL_TYPE, 1, 0, "frame_format_model_type" },
0013     { CCS_R_FRAME_FORMAT_MODEL_SUBTYPE, 1, 0, "frame_format_model_subtype" },
0014     { CCS_R_FRAME_FORMAT_DESCRIPTOR(0), 30, 0, "frame_format_descriptor" },
0015     { CCS_R_FRAME_FORMAT_DESCRIPTOR_4(0), 32, 0, "frame_format_descriptor_4" },
0016     { CCS_R_ANALOG_GAIN_CAPABILITY, 2, 0, "analog_gain_capability" },
0017     { CCS_R_ANALOG_GAIN_CODE_MIN, 2, 0, "analog_gain_code_min" },
0018     { CCS_R_ANALOG_GAIN_CODE_MAX, 2, 0, "analog_gain_code_max" },
0019     { CCS_R_ANALOG_GAIN_CODE_STEP, 2, 0, "analog_gain_code_step" },
0020     { CCS_R_ANALOG_GAIN_TYPE, 2, 0, "analog_gain_type" },
0021     { CCS_R_ANALOG_GAIN_M0, 2, 0, "analog_gain_m0" },
0022     { CCS_R_ANALOG_GAIN_C0, 2, 0, "analog_gain_c0" },
0023     { CCS_R_ANALOG_GAIN_M1, 2, 0, "analog_gain_m1" },
0024     { CCS_R_ANALOG_GAIN_C1, 2, 0, "analog_gain_c1" },
0025     { CCS_R_ANALOG_LINEAR_GAIN_MIN, 2, 0, "analog_linear_gain_min" },
0026     { CCS_R_ANALOG_LINEAR_GAIN_MAX, 2, 0, "analog_linear_gain_max" },
0027     { CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE, 2, 0, "analog_linear_gain_step_size" },
0028     { CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN, 2, 0, "analog_exponential_gain_min" },
0029     { CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX, 2, 0, "analog_exponential_gain_max" },
0030     { CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE, 2, 0, "analog_exponential_gain_step_size" },
0031     { CCS_R_DATA_FORMAT_MODEL_TYPE, 1, 0, "data_format_model_type" },
0032     { CCS_R_DATA_FORMAT_MODEL_SUBTYPE, 1, 0, "data_format_model_subtype" },
0033     { CCS_R_DATA_FORMAT_DESCRIPTOR(0), 32, 0, "data_format_descriptor" },
0034     { CCS_R_INTEGRATION_TIME_CAPABILITY, 2, 0, "integration_time_capability" },
0035     { CCS_R_COARSE_INTEGRATION_TIME_MIN, 2, 0, "coarse_integration_time_min" },
0036     { CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "coarse_integration_time_max_margin" },
0037     { CCS_R_FINE_INTEGRATION_TIME_MIN, 2, 0, "fine_integration_time_min" },
0038     { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "fine_integration_time_max_margin" },
0039     { CCS_R_DIGITAL_GAIN_CAPABILITY, 1, 0, "digital_gain_capability" },
0040     { CCS_R_DIGITAL_GAIN_MIN, 2, 0, "digital_gain_min" },
0041     { CCS_R_DIGITAL_GAIN_MAX, 2, 0, "digital_gain_max" },
0042     { CCS_R_DIGITAL_GAIN_STEP_SIZE, 2, 0, "digital_gain_step_size" },
0043     { CCS_R_PEDESTAL_CAPABILITY, 1, 0, "Pedestal_capability" },
0044     { CCS_R_ADC_CAPABILITY, 1, 0, "ADC_capability" },
0045     { CCS_R_ADC_BIT_DEPTH_CAPABILITY, 4, 0, "ADC_bit_depth_capability" },
0046     { CCS_R_MIN_EXT_CLK_FREQ_MHZ, 4, 0, "min_ext_clk_freq_mhz" },
0047     { CCS_R_MAX_EXT_CLK_FREQ_MHZ, 4, 0, "max_ext_clk_freq_mhz" },
0048     { CCS_R_MIN_PRE_PLL_CLK_DIV, 2, 0, "min_pre_pll_clk_div" },
0049     { CCS_R_MAX_PRE_PLL_CLK_DIV, 2, 0, "max_pre_pll_clk_div" },
0050     { CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_pll_ip_clk_freq_mhz" },
0051     { CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_pll_ip_clk_freq_mhz" },
0052     { CCS_R_MIN_PLL_MULTIPLIER, 2, 0, "min_pll_multiplier" },
0053     { CCS_R_MAX_PLL_MULTIPLIER, 2, 0, "max_pll_multiplier" },
0054     { CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_pll_op_clk_freq_mhz" },
0055     { CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_pll_op_clk_freq_mhz" },
0056     { CCS_R_MIN_VT_SYS_CLK_DIV, 2, 0, "min_vt_sys_clk_div" },
0057     { CCS_R_MAX_VT_SYS_CLK_DIV, 2, 0, "max_vt_sys_clk_div" },
0058     { CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ, 4, 0, "min_vt_sys_clk_freq_mhz" },
0059     { CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ, 4, 0, "max_vt_sys_clk_freq_mhz" },
0060     { CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ, 4, 0, "min_vt_pix_clk_freq_mhz" },
0061     { CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ, 4, 0, "max_vt_pix_clk_freq_mhz" },
0062     { CCS_R_MIN_VT_PIX_CLK_DIV, 2, 0, "min_vt_pix_clk_div" },
0063     { CCS_R_MAX_VT_PIX_CLK_DIV, 2, 0, "max_vt_pix_clk_div" },
0064     { CCS_R_CLOCK_CALCULATION, 1, 0, "clock_calculation" },
0065     { CCS_R_NUM_OF_VT_LANES, 1, 0, "num_of_vt_lanes" },
0066     { CCS_R_NUM_OF_OP_LANES, 1, 0, "num_of_op_lanes" },
0067     { CCS_R_OP_BITS_PER_LANE, 1, 0, "op_bits_per_lane" },
0068     { CCS_R_MIN_FRAME_LENGTH_LINES, 2, 0, "min_frame_length_lines" },
0069     { CCS_R_MAX_FRAME_LENGTH_LINES, 2, 0, "max_frame_length_lines" },
0070     { CCS_R_MIN_LINE_LENGTH_PCK, 2, 0, "min_line_length_pck" },
0071     { CCS_R_MAX_LINE_LENGTH_PCK, 2, 0, "max_line_length_pck" },
0072     { CCS_R_MIN_LINE_BLANKING_PCK, 2, 0, "min_line_blanking_pck" },
0073     { CCS_R_MIN_FRAME_BLANKING_LINES, 2, 0, "min_frame_blanking_lines" },
0074     { CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE, 1, 0, "min_line_length_pck_step_size" },
0075     { CCS_R_TIMING_MODE_CAPABILITY, 1, 0, "timing_mode_capability" },
0076     { CCS_R_FRAME_MARGIN_MAX_VALUE, 2, 0, "frame_margin_max_value" },
0077     { CCS_R_FRAME_MARGIN_MIN_VALUE, 1, 0, "frame_margin_min_value" },
0078     { CCS_R_GAIN_DELAY_TYPE, 1, 0, "gain_delay_type" },
0079     { CCS_R_MIN_OP_SYS_CLK_DIV, 2, 0, "min_op_sys_clk_div" },
0080     { CCS_R_MAX_OP_SYS_CLK_DIV, 2, 0, "max_op_sys_clk_div" },
0081     { CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ, 4, 0, "min_op_sys_clk_freq_mhz" },
0082     { CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ, 4, 0, "max_op_sys_clk_freq_mhz" },
0083     { CCS_R_MIN_OP_PIX_CLK_DIV, 2, 0, "min_op_pix_clk_div" },
0084     { CCS_R_MAX_OP_PIX_CLK_DIV, 2, 0, "max_op_pix_clk_div" },
0085     { CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ, 4, 0, "min_op_pix_clk_freq_mhz" },
0086     { CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ, 4, 0, "max_op_pix_clk_freq_mhz" },
0087     { CCS_R_X_ADDR_MIN, 2, 0, "x_addr_min" },
0088     { CCS_R_Y_ADDR_MIN, 2, 0, "y_addr_min" },
0089     { CCS_R_X_ADDR_MAX, 2, 0, "x_addr_max" },
0090     { CCS_R_Y_ADDR_MAX, 2, 0, "y_addr_max" },
0091     { CCS_R_MIN_X_OUTPUT_SIZE, 2, 0, "min_x_output_size" },
0092     { CCS_R_MIN_Y_OUTPUT_SIZE, 2, 0, "min_y_output_size" },
0093     { CCS_R_MAX_X_OUTPUT_SIZE, 2, 0, "max_x_output_size" },
0094     { CCS_R_MAX_Y_OUTPUT_SIZE, 2, 0, "max_y_output_size" },
0095     { CCS_R_X_ADDR_START_DIV_CONSTANT, 1, 0, "x_addr_start_div_constant" },
0096     { CCS_R_Y_ADDR_START_DIV_CONSTANT, 1, 0, "y_addr_start_div_constant" },
0097     { CCS_R_X_ADDR_END_DIV_CONSTANT, 1, 0, "x_addr_end_div_constant" },
0098     { CCS_R_Y_ADDR_END_DIV_CONSTANT, 1, 0, "y_addr_end_div_constant" },
0099     { CCS_R_X_SIZE_DIV, 1, 0, "x_size_div" },
0100     { CCS_R_Y_SIZE_DIV, 1, 0, "y_size_div" },
0101     { CCS_R_X_OUTPUT_DIV, 1, 0, "x_output_div" },
0102     { CCS_R_Y_OUTPUT_DIV, 1, 0, "y_output_div" },
0103     { CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT, 1, 0, "non_flexible_resolution_support" },
0104     { CCS_R_MIN_OP_PRE_PLL_CLK_DIV, 2, 0, "min_op_pre_pll_clk_div" },
0105     { CCS_R_MAX_OP_PRE_PLL_CLK_DIV, 2, 0, "max_op_pre_pll_clk_div" },
0106     { CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_ip_clk_freq_mhz" },
0107     { CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_ip_clk_freq_mhz" },
0108     { CCS_R_MIN_OP_PLL_MULTIPLIER, 2, 0, "min_op_pll_multiplier" },
0109     { CCS_R_MAX_OP_PLL_MULTIPLIER, 2, 0, "max_op_pll_multiplier" },
0110     { CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_op_clk_freq_mhz" },
0111     { CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_op_clk_freq_mhz" },
0112     { CCS_R_CLOCK_TREE_PLL_CAPABILITY, 1, 0, "clock_tree_pll_capability" },
0113     { CCS_R_CLOCK_CAPA_TYPE_CAPABILITY, 1, 0, "clock_capa_type_capability" },
0114     { CCS_R_MIN_EVEN_INC, 2, 0, "min_even_inc" },
0115     { CCS_R_MIN_ODD_INC, 2, 0, "min_odd_inc" },
0116     { CCS_R_MAX_EVEN_INC, 2, 0, "max_even_inc" },
0117     { CCS_R_MAX_ODD_INC, 2, 0, "max_odd_inc" },
0118     { CCS_R_AUX_SUBSAMP_CAPABILITY, 1, 0, "aux_subsamp_capability" },
0119     { CCS_R_AUX_SUBSAMP_MONO_CAPABILITY, 1, 0, "aux_subsamp_mono_capability" },
0120     { CCS_R_MONOCHROME_CAPABILITY, 1, 0, "monochrome_capability" },
0121     { CCS_R_PIXEL_READOUT_CAPABILITY, 1, 0, "pixel_readout_capability" },
0122     { CCS_R_MIN_EVEN_INC_MONO, 2, 0, "min_even_inc_mono" },
0123     { CCS_R_MAX_EVEN_INC_MONO, 2, 0, "max_even_inc_mono" },
0124     { CCS_R_MIN_ODD_INC_MONO, 2, 0, "min_odd_inc_mono" },
0125     { CCS_R_MAX_ODD_INC_MONO, 2, 0, "max_odd_inc_mono" },
0126     { CCS_R_MIN_EVEN_INC_BC2, 2, 0, "min_even_inc_bc2" },
0127     { CCS_R_MAX_EVEN_INC_BC2, 2, 0, "max_even_inc_bc2" },
0128     { CCS_R_MIN_ODD_INC_BC2, 2, 0, "min_odd_inc_bc2" },
0129     { CCS_R_MAX_ODD_INC_BC2, 2, 0, "max_odd_inc_bc2" },
0130     { CCS_R_MIN_EVEN_INC_MONO_BC2, 2, 0, "min_even_inc_mono_bc2" },
0131     { CCS_R_MAX_EVEN_INC_MONO_BC2, 2, 0, "max_even_inc_mono_bc2" },
0132     { CCS_R_MIN_ODD_INC_MONO_BC2, 2, 0, "min_odd_inc_mono_bc2" },
0133     { CCS_R_MAX_ODD_INC_MONO_BC2, 2, 0, "max_odd_inc_mono_bc2" },
0134     { CCS_R_SCALING_CAPABILITY, 2, 0, "scaling_capability" },
0135     { CCS_R_SCALER_M_MIN, 2, 0, "scaler_m_min" },
0136     { CCS_R_SCALER_M_MAX, 2, 0, "scaler_m_max" },
0137     { CCS_R_SCALER_N_MIN, 2, 0, "scaler_n_min" },
0138     { CCS_R_SCALER_N_MAX, 2, 0, "scaler_n_max" },
0139     { CCS_R_DIGITAL_CROP_CAPABILITY, 1, 0, "digital_crop_capability" },
0140     { CCS_R_HDR_CAPABILITY_1, 1, 0, "hdr_capability_1" },
0141     { CCS_R_MIN_HDR_BIT_DEPTH, 1, 0, "min_hdr_bit_depth" },
0142     { CCS_R_HDR_RESOLUTION_SUB_TYPES, 1, 0, "hdr_resolution_sub_types" },
0143     { CCS_R_HDR_RESOLUTION_SUB_TYPE(0), 2, 0, "hdr_resolution_sub_type" },
0144     { CCS_R_HDR_CAPABILITY_2, 1, 0, "hdr_capability_2" },
0145     { CCS_R_MAX_HDR_BIT_DEPTH, 1, 0, "max_hdr_bit_depth" },
0146     { CCS_R_USL_SUPPORT_CAPABILITY, 1, 0, "usl_support_capability" },
0147     { CCS_R_USL_CLOCK_MODE_D_CAPABILITY, 1, 0, "usl_clock_mode_d_capability" },
0148     { CCS_R_MIN_OP_SYS_CLK_DIV_REV, 1, 0, "min_op_sys_clk_div_rev" },
0149     { CCS_R_MAX_OP_SYS_CLK_DIV_REV, 1, 0, "max_op_sys_clk_div_rev" },
0150     { CCS_R_MIN_OP_PIX_CLK_DIV_REV, 1, 0, "min_op_pix_clk_div_rev" },
0151     { CCS_R_MAX_OP_PIX_CLK_DIV_REV, 1, 0, "max_op_pix_clk_div_rev" },
0152     { CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "min_op_sys_clk_freq_rev_mhz" },
0153     { CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "max_op_sys_clk_freq_rev_mhz" },
0154     { CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "min_op_pix_clk_freq_rev_mhz" },
0155     { CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "max_op_pix_clk_freq_rev_mhz" },
0156     { CCS_R_MAX_BITRATE_REV_D_MODE_MBPS, 4, 0, "max_bitrate_rev_d_mode_mbps" },
0157     { CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS, 4, 0, "max_symrate_rev_c_mode_msps" },
0158     { CCS_R_COMPRESSION_CAPABILITY, 1, 0, "compression_capability" },
0159     { CCS_R_TEST_MODE_CAPABILITY, 2, 0, "test_mode_capability" },
0160     { CCS_R_PN9_DATA_FORMAT1, 1, 0, "pn9_data_format1" },
0161     { CCS_R_PN9_DATA_FORMAT2, 1, 0, "pn9_data_format2" },
0162     { CCS_R_PN9_DATA_FORMAT3, 1, 0, "pn9_data_format3" },
0163     { CCS_R_PN9_DATA_FORMAT4, 1, 0, "pn9_data_format4" },
0164     { CCS_R_PN9_MISC_CAPABILITY, 1, 0, "pn9_misc_capability" },
0165     { CCS_R_TEST_PATTERN_CAPABILITY, 1, 0, "test_pattern_capability" },
0166     { CCS_R_PATTERN_SIZE_DIV_M1, 1, 0, "pattern_size_div_m1" },
0167     { CCS_R_FIFO_SUPPORT_CAPABILITY, 1, 0, "fifo_support_capability" },
0168     { CCS_R_PHY_CTRL_CAPABILITY, 1, 0, "phy_ctrl_capability" },
0169     { CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_dphy_lane_mode_capability" },
0170     { CCS_R_CSI_SIGNALING_MODE_CAPABILITY, 1, 0, "csi_signaling_mode_capability" },
0171     { CCS_R_FAST_STANDBY_CAPABILITY, 1, 0, "fast_standby_capability" },
0172     { CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY, 1, 0, "csi_address_control_capability" },
0173     { CCS_R_DATA_TYPE_CAPABILITY, 1, 0, "data_type_capability" },
0174     { CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_cphy_lane_mode_capability" },
0175     { CCS_R_EMB_DATA_CAPABILITY, 1, 0, "emb_data_capability" },
0176     { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_d_mode_mbps 0" },
0177     { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_d_mode_mbps 4" },
0178     { CCS_R_TEMP_SENSOR_CAPABILITY, 1, 0, "temp_sensor_capability" },
0179     { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_c_mode_mbps 0" },
0180     { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_c_mode_mbps 4" },
0181     { CCS_R_DPHY_EQUALIZATION_CAPABILITY, 1, 0, "dphy_equalization_capability" },
0182     { CCS_R_CPHY_EQUALIZATION_CAPABILITY, 1, 0, "cphy_equalization_capability" },
0183     { CCS_R_DPHY_PREAMBLE_CAPABILITY, 1, 0, "dphy_preamble_capability" },
0184     { CCS_R_DPHY_SSC_CAPABILITY, 1, 0, "dphy_ssc_capability" },
0185     { CCS_R_CPHY_CALIBRATION_CAPABILITY, 1, 0, "cphy_calibration_capability" },
0186     { CCS_R_DPHY_CALIBRATION_CAPABILITY, 1, 0, "dphy_calibration_capability" },
0187     { CCS_R_PHY_CTRL_CAPABILITY_2, 1, 0, "phy_ctrl_capability_2" },
0188     { CCS_R_LRTE_CPHY_CAPABILITY, 1, 0, "lrte_cphy_capability" },
0189     { CCS_R_LRTE_DPHY_CAPABILITY, 1, 0, "lrte_dphy_capability" },
0190     { CCS_R_ALPS_CAPABILITY_DPHY, 1, 0, "alps_capability_dphy" },
0191     { CCS_R_ALPS_CAPABILITY_CPHY, 1, 0, "alps_capability_cphy" },
0192     { CCS_R_SCRAMBLING_CAPABILITY, 1, 0, "scrambling_capability" },
0193     { CCS_R_DPHY_MANUAL_CONSTANT, 1, 0, "dphy_manual_constant" },
0194     { CCS_R_CPHY_MANUAL_CONSTANT, 1, 0, "cphy_manual_constant" },
0195     { CCS_R_CSI2_INTERFACE_CAPABILITY_MISC, 1, 0, "CSI2_interface_capability_misc" },
0196     { CCS_R_PHY_CTRL_CAPABILITY_3, 1, 0, "PHY_ctrl_capability_3" },
0197     { CCS_R_DPHY_SF, 1, 0, "dphy_sf" },
0198     { CCS_R_CPHY_SF, 1, 0, "cphy_sf" },
0199     { CCS_R_DPHY_LIMITS_1, 1, 0, "dphy_limits_1" },
0200     { CCS_R_DPHY_LIMITS_2, 1, 0, "dphy_limits_2" },
0201     { CCS_R_DPHY_LIMITS_3, 1, 0, "dphy_limits_3" },
0202     { CCS_R_DPHY_LIMITS_4, 1, 0, "dphy_limits_4" },
0203     { CCS_R_DPHY_LIMITS_5, 1, 0, "dphy_limits_5" },
0204     { CCS_R_DPHY_LIMITS_6, 1, 0, "dphy_limits_6" },
0205     { CCS_R_CPHY_LIMITS_1, 1, 0, "cphy_limits_1" },
0206     { CCS_R_CPHY_LIMITS_2, 1, 0, "cphy_limits_2" },
0207     { CCS_R_CPHY_LIMITS_3, 1, 0, "cphy_limits_3" },
0208     { CCS_R_MIN_FRAME_LENGTH_LINES_BIN, 2, 0, "min_frame_length_lines_bin" },
0209     { CCS_R_MAX_FRAME_LENGTH_LINES_BIN, 2, 0, "max_frame_length_lines_bin" },
0210     { CCS_R_MIN_LINE_LENGTH_PCK_BIN, 2, 0, "min_line_length_pck_bin" },
0211     { CCS_R_MAX_LINE_LENGTH_PCK_BIN, 2, 0, "max_line_length_pck_bin" },
0212     { CCS_R_MIN_LINE_BLANKING_PCK_BIN, 2, 0, "min_line_blanking_pck_bin" },
0213     { CCS_R_FINE_INTEGRATION_TIME_MIN_BIN, 2, 0, "fine_integration_time_min_bin" },
0214     { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, 2, 0, "fine_integration_time_max_margin_bin" },
0215     { CCS_R_BINNING_CAPABILITY, 1, 0, "binning_capability" },
0216     { CCS_R_BINNING_WEIGHTING_CAPABILITY, 1, 0, "binning_weighting_capability" },
0217     { CCS_R_BINNING_SUB_TYPES, 1, 0, "binning_sub_types" },
0218     { CCS_R_BINNING_SUB_TYPE(0), 64, 0, "binning_sub_type" },
0219     { CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY, 1, 0, "binning_weighting_mono_capability" },
0220     { CCS_R_BINNING_SUB_TYPES_MONO, 1, 0, "binning_sub_types_mono" },
0221     { CCS_R_BINNING_SUB_TYPE_MONO(0), 64, 0, "binning_sub_type_mono" },
0222     { CCS_R_DATA_TRANSFER_IF_CAPABILITY, 1, 0, "data_transfer_if_capability" },
0223     { CCS_R_SHADING_CORRECTION_CAPABILITY, 1, 0, "shading_correction_capability" },
0224     { CCS_R_GREEN_IMBALANCE_CAPABILITY, 1, 0, "green_imbalance_capability" },
0225     { CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY, 1, 0, "module_specific_correction_capability" },
0226     { CCS_R_DEFECT_CORRECTION_CAPABILITY, 2, 0, "defect_correction_capability" },
0227     { CCS_R_DEFECT_CORRECTION_CAPABILITY_2, 2, 0, "defect_correction_capability_2" },
0228     { CCS_R_NF_CAPABILITY, 1, 0, "nf_capability" },
0229     { CCS_R_OB_READOUT_CAPABILITY, 1, 0, "ob_readout_capability" },
0230     { CCS_R_COLOR_FEEDBACK_CAPABILITY, 1, 0, "color_feedback_capability" },
0231     { CCS_R_CFA_PATTERN_CAPABILITY, 1, 0, "CFA_pattern_capability" },
0232     { CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY, 1, 0, "CFA_pattern_conversion_capability" },
0233     { CCS_R_FLASH_MODE_CAPABILITY, 1, 0, "flash_mode_capability" },
0234     { CCS_R_SA_STROBE_MODE_CAPABILITY, 1, 0, "sa_strobe_mode_capability" },
0235     { CCS_R_RESET_MAX_DELAY, 1, 0, "reset_max_delay" },
0236     { CCS_R_RESET_MIN_TIME, 1, 0, "reset_min_time" },
0237     { CCS_R_PDAF_CAPABILITY_1, 1, 0, "pdaf_capability_1" },
0238     { CCS_R_PDAF_CAPABILITY_2, 1, 0, "pdaf_capability_2" },
0239     { CCS_R_BRACKETING_LUT_CAPABILITY_1, 1, 0, "bracketing_lut_capability_1" },
0240     { CCS_R_BRACKETING_LUT_CAPABILITY_2, 1, 0, "bracketing_lut_capability_2" },
0241     { CCS_R_BRACKETING_LUT_SIZE, 1, 0, "bracketing_lut_size" },
0242     { 0 } /* Guardian */
0243 };