media/i2c/ccs-pll.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * drivers/media/i2c/ccs-pll.h
0004  *
0005  * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
0006  *
0007  * Copyright (C) 2020 Intel Corporation
0008  * Copyright (C) 2012 Nokia Corporation
0009  * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
0010  */
0011
0012 #ifndef CCS_PLL_H
0013 #define CCS_PLL_H
0014
0015 #include <linux/bits.h>
0016
0017 /* CSI-2 or CCP-2 */
0018 #define CCS_PLL_BUS_TYPE_CSI2_DPHY              0x00
0019 #define CCS_PLL_BUS_TYPE_CSI2_CPHY              0x01
0020
0021 /* Old SMIA and implementation specific flags */
0022 /* op pix clock is for all lanes in total normally */
0023 #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE          BIT(0)
0024 #define CCS_PLL_FLAG_NO_OP_CLOCKS               BIT(1)
0025 /* CCS PLL flags */
0026 #define CCS_PLL_FLAG_LANE_SPEED_MODEL               BIT(2)
0027 #define CCS_PLL_FLAG_LINK_DECOUPLED             BIT(3)
0028 #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER             BIT(4)
0029 #define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV            BIT(5)
0030 #define CCS_PLL_FLAG_FIFO_DERATING              BIT(6)
0031 #define CCS_PLL_FLAG_FIFO_OVERRATING                BIT(7)
0032 #define CCS_PLL_FLAG_DUAL_PLL                   BIT(8)
0033 #define CCS_PLL_FLAG_OP_SYS_DDR                 BIT(9)
0034 #define CCS_PLL_FLAG_OP_PIX_DDR                 BIT(10)
0035
0036 /**
0037  * struct ccs_pll_branch_fr - CCS PLL configuration (front)
0038  *
0039  * A single branch front-end of the CCS PLL tree.
0040  *
0041  * @pre_pll_clk_div: Pre-PLL clock divisor
0042  * @pll_multiplier: PLL multiplier
0043  * @pll_ip_clk_freq_hz: PLL input clock frequency
0044  * @pll_op_clk_freq_hz: PLL output clock frequency
0045  */
0046 struct ccs_pll_branch_fr {
0047     u16 pre_pll_clk_div;
0048     u16 pll_multiplier;
0049     u32 pll_ip_clk_freq_hz;
0050     u32 pll_op_clk_freq_hz;
0051 };
0052
0053 /**
0054  * struct ccs_pll_branch_bk - CCS PLL configuration (back)
0055  *
0056  * A single branch back-end of the CCS PLL tree.
0057  *
0058  * @sys_clk_div: System clock divider
0059  * @pix_clk_div: Pixel clock divider
0060  * @sys_clk_freq_hz: System clock frequency
0061  * @pix_clk_freq_hz: Pixel clock frequency
0062  */
0063 struct ccs_pll_branch_bk {
0064     u16 sys_clk_div;
0065     u16 pix_clk_div;
0066     u32 sys_clk_freq_hz;
0067     u32 pix_clk_freq_hz;
0068 };
0069
0070 /**
0071  * struct ccs_pll - Full CCS PLL configuration
0072  *
0073  * All information required to calculate CCS PLL configuration.
0074  *
0075  * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
0076  * @op_lanes: Number of operational lanes (input)
0077  * @vt_lanes: Number of video timing lanes (input)
0078  * @csi2: CSI-2 related parameters
0079  * @csi2.lanes: The number of the CSI-2 data lanes (input)
0080  * @binning_vertical: Vertical binning factor (input)
0081  * @binning_horizontal: Horizontal binning factor (input)
0082  * @scale_m: Downscaling factor, M component, [16, max] (input)
0083  * @scale_n: Downscaling factor, N component, typically 16 (input)
0084  * @bits_per_pixel: Bits per pixel on the output data bus (input)
0085  * @op_bits_per_lane: Number of bits per OP lane (input)
0086  * @flags: CCS_PLL_FLAG_* (input)
0087  * @link_freq: Chosen link frequency (input)
0088  * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
0089  *           (input)
0090  * @vt_fr: Video timing front-end configuration (output)
0091  * @vt_bk: Video timing back-end configuration (output)
0092  * @op_fr: Operational timing front-end configuration (output)
0093  * @op_bk: Operational timing back-end configuration (output)
0094  * @pixel_rate_csi: Pixel rate on the output data bus (output)
0095  * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
0096  *              (output)
0097  */
0098 struct ccs_pll {
0099     /* input values */
0100     u8 bus_type;
0101     u8 op_lanes;
0102     u8 vt_lanes;
0103     struct {
0104         u8 lanes;
0105     } csi2;
0106     u8 binning_horizontal;
0107     u8 binning_vertical;
0108     u8 scale_m;
0109     u8 scale_n;
0110     u8 bits_per_pixel;
0111     u8 op_bits_per_lane;
0112     u16 flags;
0113     u32 link_freq;
0114     u32 ext_clk_freq_hz;
0115
0116     /* output values */
0117     struct ccs_pll_branch_fr vt_fr;
0118     struct ccs_pll_branch_bk vt_bk;
0119     struct ccs_pll_branch_fr op_fr;
0120     struct ccs_pll_branch_bk op_bk;
0121
0122     u32 pixel_rate_csi;
0123     u32 pixel_rate_pixel_array;
0124 };
0125
0126 /**
0127  * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
0128  *
0129  * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
0130  * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
0131  * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency
0132  * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency
0133  * @min_pll_multiplier: Minimum PLL multiplier
0134  * @max_pll_multiplier: Maximum PLL multiplier
0135  * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency
0136  * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency
0137  */
0138 struct ccs_pll_branch_limits_fr {
0139     u16 min_pre_pll_clk_div;
0140     u16 max_pre_pll_clk_div;
0141     u32 min_pll_ip_clk_freq_hz;
0142     u32 max_pll_ip_clk_freq_hz;
0143     u16 min_pll_multiplier;
0144     u16 max_pll_multiplier;
0145     u32 min_pll_op_clk_freq_hz;
0146     u32 max_pll_op_clk_freq_hz;
0147 };
0148
0149 /**
0150  * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
0151  *
0152  * @min_sys_clk_div: Minimum system clock divider
0153  * @max_sys_clk_div: Maximum system clock divider
0154  * @min_sys_clk_freq_hz: Minimum system clock frequency
0155  * @max_sys_clk_freq_hz: Maximum system clock frequency
0156  * @min_pix_clk_div: Minimum pixel clock divider
0157  * @max_pix_clk_div: Maximum pixel clock divider
0158  * @min_pix_clk_freq_hz: Minimum pixel clock frequency
0159  * @max_pix_clk_freq_hz: Maximum pixel clock frequency
0160  */
0161 struct ccs_pll_branch_limits_bk {
0162     u16 min_sys_clk_div;
0163     u16 max_sys_clk_div;
0164     u32 min_sys_clk_freq_hz;
0165     u32 max_sys_clk_freq_hz;
0166     u16 min_pix_clk_div;
0167     u16 max_pix_clk_div;
0168     u32 min_pix_clk_freq_hz;
0169     u32 max_pix_clk_freq_hz;
0170 };
0171
0172 /**
0173  * struct ccs_pll_limits - CCS PLL limits
0174  *
0175  * @min_ext_clk_freq_hz: Minimum external clock frequency
0176  * @max_ext_clk_freq_hz: Maximum external clock frequency
0177  * @vt_fr: Video timing front-end limits
0178  * @vt_bk: Video timing back-end limits
0179  * @op_fr: Operational timing front-end limits
0180  * @op_bk: Operational timing back-end limits
0181  * @min_line_length_pck_bin: Minimum line length in pixels, with binning
0182  * @min_line_length_pck: Minimum line length in pixels without binning
0183  */
0184 struct ccs_pll_limits {
0185     /* Strict PLL limits */
0186     u32 min_ext_clk_freq_hz;
0187     u32 max_ext_clk_freq_hz;
0188
0189     struct ccs_pll_branch_limits_fr vt_fr;
0190     struct ccs_pll_branch_limits_bk vt_bk;
0191     struct ccs_pll_branch_limits_fr op_fr;
0192     struct ccs_pll_branch_limits_bk op_bk;
0193
0194     /* Other relevant limits */
0195     u32 min_line_length_pck_bin;
0196     u32 min_line_length_pck;
0197 };
0198
0199 struct device;
0200
0201 /**
0202  * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters
0203  *
0204  * @dev: Device pointer, used for printing messages
0205  * @limits: Limits specific to the sensor
0206  * @pll: Given PLL configuration
0207  *
0208  * Calculate the CCS PLL configuration based on the limits as well as given
0209  * device specific, system specific or user configured input data.
0210  */
0211 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
0212               struct ccs_pll *pll);
0213
0214 #endif /* CCS_PLL_H */