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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2021 Sieć Badawcza Łukasiewicz
0004  * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
0005  * Written by Krzysztof Hałasa
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/pm_runtime.h>
0011 
0012 #include <media/v4l2-ctrls.h>
0013 #include <media/v4l2-fwnode.h>
0014 #include <media/v4l2-subdev.h>
0015 
0016 /* External clock (extclk) frequencies */
0017 #define AR0521_EXTCLK_MIN     (10 * 1000 * 1000)
0018 #define AR0521_EXTCLK_MAX     (48 * 1000 * 1000)
0019 
0020 /* PLL and PLL2 */
0021 #define AR0521_PLL_MIN       (320 * 1000 * 1000)
0022 #define AR0521_PLL_MAX      (1280 * 1000 * 1000)
0023 
0024 /* Effective pixel clocks, the registers may be DDR */
0025 #define AR0521_PIXEL_CLOCK_RATE  (184 * 1000 * 1000)
0026 #define AR0521_PIXEL_CLOCK_MIN   (168 * 1000 * 1000)
0027 #define AR0521_PIXEL_CLOCK_MAX   (414 * 1000 * 1000)
0028 
0029 #define AR0521_WIDTH_MIN           8u
0030 #define AR0521_WIDTH_MAX        2608u
0031 #define AR0521_HEIGHT_MIN          8u
0032 #define AR0521_HEIGHT_MAX       1958u
0033 
0034 #define AR0521_WIDTH_BLANKING_MIN     572u
0035 #define AR0521_HEIGHT_BLANKING_MIN     38u /* must be even */
0036 #define AR0521_TOTAL_WIDTH_MIN       2968u
0037 
0038 /* AR0521 registers */
0039 #define AR0521_REG_VT_PIX_CLK_DIV       0x0300
0040 #define AR0521_REG_FRAME_LENGTH_LINES       0x0340
0041 
0042 #define AR0521_REG_CHIP_ID          0x3000
0043 #define AR0521_REG_COARSE_INTEGRATION_TIME  0x3012
0044 #define AR0521_REG_ROW_SPEED            0x3016
0045 #define AR0521_REG_EXTRA_DELAY          0x3018
0046 #define AR0521_REG_RESET            0x301A
0047 #define   AR0521_REG_RESET_DEFAULTS       0x0238
0048 #define   AR0521_REG_RESET_GROUP_PARAM_HOLD   0x8000
0049 #define   AR0521_REG_RESET_STREAM         BIT(2)
0050 #define   AR0521_REG_RESET_RESTART        BIT(1)
0051 #define   AR0521_REG_RESET_INIT           BIT(0)
0052 
0053 #define AR0521_REG_GREEN1_GAIN          0x3056
0054 #define AR0521_REG_BLUE_GAIN            0x3058
0055 #define AR0521_REG_RED_GAIN         0x305A
0056 #define AR0521_REG_GREEN2_GAIN          0x305C
0057 #define AR0521_REG_GLOBAL_GAIN          0x305E
0058 
0059 #define AR0521_REG_HISPI_TEST_MODE      0x3066
0060 #define AR0521_REG_HISPI_TEST_MODE_LP11       0x0004
0061 
0062 #define AR0521_REG_TEST_PATTERN_MODE        0x3070
0063 
0064 #define AR0521_REG_SERIAL_FORMAT        0x31AE
0065 #define AR0521_REG_SERIAL_FORMAT_MIPI         0x0200
0066 
0067 #define AR0521_REG_HISPI_CONTROL_STATUS     0x31C6
0068 #define AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE 0x80
0069 
0070 #define be      cpu_to_be16
0071 
0072 static const char * const ar0521_supply_names[] = {
0073     "vdd_io",   /* I/O (1.8V) supply */
0074     "vdd",      /* Core, PLL and MIPI (1.2V) supply */
0075     "vaa",      /* Analog (2.7V) supply */
0076 };
0077 
0078 struct ar0521_ctrls {
0079     struct v4l2_ctrl_handler handler;
0080     struct {
0081         struct v4l2_ctrl *gain;
0082         struct v4l2_ctrl *red_balance;
0083         struct v4l2_ctrl *blue_balance;
0084     };
0085     struct {
0086         struct v4l2_ctrl *hblank;
0087         struct v4l2_ctrl *vblank;
0088     };
0089     struct v4l2_ctrl *pixrate;
0090     struct v4l2_ctrl *exposure;
0091     struct v4l2_ctrl *test_pattern;
0092 };
0093 
0094 struct ar0521_dev {
0095     struct i2c_client *i2c_client;
0096     struct v4l2_subdev sd;
0097     struct media_pad pad;
0098     struct clk *extclk;
0099     u32 extclk_freq;
0100 
0101     struct regulator *supplies[ARRAY_SIZE(ar0521_supply_names)];
0102     struct gpio_desc *reset_gpio;
0103 
0104     /* lock to protect all members below */
0105     struct mutex lock;
0106 
0107     struct v4l2_mbus_framefmt fmt;
0108     struct ar0521_ctrls ctrls;
0109     unsigned int lane_count;
0110     u16 total_width;
0111     u16 total_height;
0112     u16 pll_pre;
0113     u16 pll_mult;
0114     u16 pll_pre2;
0115     u16 pll_mult2;
0116     bool streaming;
0117 };
0118 
0119 static inline struct ar0521_dev *to_ar0521_dev(struct v4l2_subdev *sd)
0120 {
0121     return container_of(sd, struct ar0521_dev, sd);
0122 }
0123 
0124 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
0125 {
0126     return &container_of(ctrl->handler, struct ar0521_dev,
0127                  ctrls.handler)->sd;
0128 }
0129 
0130 static u32 div64_round(u64 v, u32 d)
0131 {
0132     return div_u64(v + (d >> 1), d);
0133 }
0134 
0135 static u32 div64_round_up(u64 v, u32 d)
0136 {
0137     return div_u64(v + d - 1, d);
0138 }
0139 
0140 /* Data must be BE16, the first value is the register address */
0141 static int ar0521_write_regs(struct ar0521_dev *sensor, const __be16 *data,
0142                  unsigned int count)
0143 {
0144     struct i2c_client *client = sensor->i2c_client;
0145     struct i2c_msg msg;
0146     int ret;
0147 
0148     msg.addr = client->addr;
0149     msg.flags = client->flags;
0150     msg.buf = (u8 *)data;
0151     msg.len = count * sizeof(*data);
0152 
0153     ret = i2c_transfer(client->adapter, &msg, 1);
0154 
0155     if (ret < 0) {
0156         v4l2_err(&sensor->sd, "%s: I2C write error\n", __func__);
0157         return ret;
0158     }
0159 
0160     return 0;
0161 }
0162 
0163 static int ar0521_write_reg(struct ar0521_dev *sensor, u16 reg, u16 val)
0164 {
0165     __be16 buf[2] = {be(reg), be(val)};
0166 
0167     return ar0521_write_regs(sensor, buf, 2);
0168 }
0169 
0170 static int ar0521_set_geometry(struct ar0521_dev *sensor)
0171 {
0172     /* All dimensions are unsigned 12-bit integers */
0173     u16 x = (AR0521_WIDTH_MAX - sensor->fmt.width) / 2;
0174     u16 y = ((AR0521_HEIGHT_MAX - sensor->fmt.height) / 2) & ~1;
0175     __be16 regs[] = {
0176         be(AR0521_REG_FRAME_LENGTH_LINES),
0177         be(sensor->total_height),
0178         be(sensor->total_width),
0179         be(x),
0180         be(y),
0181         be(x + sensor->fmt.width - 1),
0182         be(y + sensor->fmt.height - 1),
0183         be(sensor->fmt.width),
0184         be(sensor->fmt.height)
0185     };
0186 
0187     return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
0188 }
0189 
0190 static int ar0521_set_gains(struct ar0521_dev *sensor)
0191 {
0192     int green = sensor->ctrls.gain->val;
0193     int red = max(green + sensor->ctrls.red_balance->val, 0);
0194     int blue = max(green + sensor->ctrls.blue_balance->val, 0);
0195     unsigned int gain = min(red, min(green, blue));
0196     unsigned int analog = min(gain, 64u); /* range is 0 - 127 */
0197     __be16 regs[5];
0198 
0199     red   = min(red   - analog + 64, 511u);
0200     green = min(green - analog + 64, 511u);
0201     blue  = min(blue  - analog + 64, 511u);
0202     regs[0] = be(AR0521_REG_GREEN1_GAIN);
0203     regs[1] = be(green << 7 | analog);
0204     regs[2] = be(blue  << 7 | analog);
0205     regs[3] = be(red   << 7 | analog);
0206     regs[4] = be(green << 7 | analog);
0207 
0208     return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
0209 }
0210 
0211 static u32 calc_pll(struct ar0521_dev *sensor, int num, u32 freq, u16 *pre_ptr,
0212             u16 *mult_ptr)
0213 {
0214     u16 pre = 1, mult = 1, new_pre;
0215     u32 pll = AR0521_PLL_MAX + 1;
0216 
0217     for (new_pre = 1; new_pre < 64; new_pre++) {
0218         u32 new_pll;
0219         u32 new_mult = div64_round_up((u64)freq * new_pre,
0220                           sensor->extclk_freq);
0221 
0222         if (new_mult < 32)
0223             continue; /* Minimum value */
0224         if (new_mult > 254)
0225             break; /* Maximum, larger pre won't work either */
0226         if (sensor->extclk_freq * (u64)new_mult < AR0521_PLL_MIN *
0227             new_pre)
0228             continue;
0229         if (sensor->extclk_freq * (u64)new_mult > AR0521_PLL_MAX *
0230             new_pre)
0231             break; /* Larger pre won't work either */
0232         new_pll = div64_round_up(sensor->extclk_freq * (u64)new_mult,
0233                      new_pre);
0234         if (new_pll < pll) {
0235             pll = new_pll;
0236             pre = new_pre;
0237             mult = new_mult;
0238         }
0239     }
0240 
0241     pll = div64_round(sensor->extclk_freq * (u64)mult, pre);
0242     *pre_ptr = pre;
0243     *mult_ptr = mult;
0244     return pll;
0245 }
0246 
0247 #define DIV 4
0248 static void ar0521_calc_mode(struct ar0521_dev *sensor)
0249 {
0250     unsigned int speed_mod = 4 / sensor->lane_count; /* 1 with 4 DDR lanes */
0251     u16 total_width = max(sensor->fmt.width + AR0521_WIDTH_BLANKING_MIN,
0252                   AR0521_TOTAL_WIDTH_MIN);
0253     u16 total_height = sensor->fmt.height + AR0521_HEIGHT_BLANKING_MIN;
0254 
0255     /* Calculate approximate pixel clock first */
0256     u64 pix_clk = AR0521_PIXEL_CLOCK_RATE;
0257 
0258     /* PLL1 drives pixel clock - dual rate */
0259     pix_clk = calc_pll(sensor, 1, pix_clk * (DIV / 2), &sensor->pll_pre,
0260                &sensor->pll_mult);
0261     pix_clk = div64_round(pix_clk, (DIV / 2));
0262     calc_pll(sensor, 2, pix_clk * (DIV / 2) * speed_mod, &sensor->pll_pre2,
0263          &sensor->pll_mult2);
0264 
0265     sensor->total_width = total_width;
0266     sensor->total_height = total_height;
0267 }
0268 
0269 static int ar0521_write_mode(struct ar0521_dev *sensor)
0270 {
0271     __be16 pll_regs[] = {
0272         be(AR0521_REG_VT_PIX_CLK_DIV),
0273         /* 0x300 */ be(4), /* vt_pix_clk_div = number of bits / 2 */
0274         /* 0x302 */ be(1), /* vt_sys_clk_div */
0275         /* 0x304 */ be((sensor->pll_pre2 << 8) | sensor->pll_pre),
0276         /* 0x306 */ be((sensor->pll_mult2 << 8) | sensor->pll_mult),
0277         /* 0x308 */ be(8), /* op_pix_clk_div = 2 * vt_pix_clk_div */
0278         /* 0x30A */ be(1)  /* op_sys_clk_div */
0279     };
0280     int ret;
0281 
0282     /* Stop streaming for just a moment */
0283     ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
0284                    AR0521_REG_RESET_DEFAULTS);
0285     if (ret)
0286         return ret;
0287 
0288     ret = ar0521_set_geometry(sensor);
0289     if (ret)
0290         return ret;
0291 
0292     ret = ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs));
0293     if (ret)
0294         return ret;
0295 
0296     ret = ar0521_write_reg(sensor, AR0521_REG_COARSE_INTEGRATION_TIME,
0297                    sensor->ctrls.exposure->val);
0298     if (ret)
0299         return ret;
0300 
0301     ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
0302                    AR0521_REG_RESET_DEFAULTS |
0303                    AR0521_REG_RESET_STREAM);
0304     if (ret)
0305         return ret;
0306 
0307     ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
0308                    sensor->ctrls.test_pattern->val);
0309     return ret;
0310 }
0311 
0312 static int ar0521_set_stream(struct ar0521_dev *sensor, bool on)
0313 {
0314     int ret;
0315 
0316     if (on) {
0317         ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
0318         if (ret < 0)
0319             return ret;
0320 
0321         ar0521_calc_mode(sensor);
0322         ret = ar0521_write_mode(sensor);
0323         if (ret)
0324             goto err;
0325 
0326         ret = ar0521_set_gains(sensor);
0327         if (ret)
0328             goto err;
0329 
0330         /* Exit LP-11 mode on clock and data lanes */
0331         ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
0332                        0);
0333         if (ret)
0334             goto err;
0335 
0336         /* Start streaming */
0337         ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
0338                        AR0521_REG_RESET_DEFAULTS |
0339                        AR0521_REG_RESET_STREAM);
0340         if (ret)
0341             goto err;
0342 
0343         return 0;
0344 
0345 err:
0346         pm_runtime_put(&sensor->i2c_client->dev);
0347         return ret;
0348 
0349     } else {
0350         /*
0351          * Reset gain, the sensor may produce all white pixels without
0352          * this
0353          */
0354         ret = ar0521_write_reg(sensor, AR0521_REG_GLOBAL_GAIN, 0x2000);
0355         if (ret)
0356             return ret;
0357 
0358         /* Stop streaming */
0359         ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
0360                        AR0521_REG_RESET_DEFAULTS);
0361         if (ret)
0362             return ret;
0363 
0364         pm_runtime_put(&sensor->i2c_client->dev);
0365         return 0;
0366     }
0367 }
0368 
0369 static void ar0521_adj_fmt(struct v4l2_mbus_framefmt *fmt)
0370 {
0371     fmt->width = clamp(ALIGN(fmt->width, 4), AR0521_WIDTH_MIN,
0372                AR0521_WIDTH_MAX);
0373     fmt->height = clamp(ALIGN(fmt->height, 4), AR0521_HEIGHT_MIN,
0374                 AR0521_HEIGHT_MAX);
0375     fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
0376     fmt->field = V4L2_FIELD_NONE;
0377     fmt->colorspace = V4L2_COLORSPACE_SRGB;
0378     fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
0379     fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
0380     fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
0381 }
0382 
0383 static int ar0521_get_fmt(struct v4l2_subdev *sd,
0384               struct v4l2_subdev_state *sd_state,
0385               struct v4l2_subdev_format *format)
0386 {
0387     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0388     struct v4l2_mbus_framefmt *fmt;
0389 
0390     mutex_lock(&sensor->lock);
0391 
0392     if (format->which == V4L2_SUBDEV_FORMAT_TRY)
0393         fmt = v4l2_subdev_get_try_format(&sensor->sd, sd_state, 0
0394                          /* pad */);
0395     else
0396         fmt = &sensor->fmt;
0397 
0398     format->format = *fmt;
0399 
0400     mutex_unlock(&sensor->lock);
0401     return 0;
0402 }
0403 
0404 static int ar0521_set_fmt(struct v4l2_subdev *sd,
0405               struct v4l2_subdev_state *sd_state,
0406               struct v4l2_subdev_format *format)
0407 {
0408     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0409     int ret = 0;
0410 
0411     ar0521_adj_fmt(&format->format);
0412 
0413     mutex_lock(&sensor->lock);
0414 
0415     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
0416         struct v4l2_mbus_framefmt *fmt;
0417 
0418         fmt = v4l2_subdev_get_try_format(sd, sd_state, 0 /* pad */);
0419         *fmt = format->format;
0420     } else {
0421         sensor->fmt = format->format;
0422         ar0521_calc_mode(sensor);
0423     }
0424 
0425     mutex_unlock(&sensor->lock);
0426     return ret;
0427 }
0428 
0429 static int ar0521_s_ctrl(struct v4l2_ctrl *ctrl)
0430 {
0431     struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
0432     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0433     int ret;
0434 
0435     /* v4l2_ctrl_lock() locks our own mutex */
0436 
0437     switch (ctrl->id) {
0438     case V4L2_CID_HBLANK:
0439     case V4L2_CID_VBLANK:
0440         sensor->total_width = sensor->fmt.width +
0441             sensor->ctrls.hblank->val;
0442         sensor->total_height = sensor->fmt.width +
0443             sensor->ctrls.vblank->val;
0444         break;
0445     default:
0446         ret = -EINVAL;
0447         break;
0448     }
0449 
0450     /* access the sensor only if it's powered up */
0451     if (!pm_runtime_get_if_in_use(&sensor->i2c_client->dev))
0452         return 0;
0453 
0454     switch (ctrl->id) {
0455     case V4L2_CID_HBLANK:
0456     case V4L2_CID_VBLANK:
0457         ret = ar0521_set_geometry(sensor);
0458         break;
0459     case V4L2_CID_GAIN:
0460     case V4L2_CID_RED_BALANCE:
0461     case V4L2_CID_BLUE_BALANCE:
0462         ret = ar0521_set_gains(sensor);
0463         break;
0464     case V4L2_CID_EXPOSURE:
0465         ret = ar0521_write_reg(sensor,
0466                        AR0521_REG_COARSE_INTEGRATION_TIME,
0467                        ctrl->val);
0468         break;
0469     case V4L2_CID_TEST_PATTERN:
0470         ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
0471                        ctrl->val);
0472         break;
0473     }
0474 
0475     pm_runtime_put(&sensor->i2c_client->dev);
0476     return ret;
0477 }
0478 
0479 static const struct v4l2_ctrl_ops ar0521_ctrl_ops = {
0480     .s_ctrl = ar0521_s_ctrl,
0481 };
0482 
0483 static const char * const test_pattern_menu[] = {
0484     "Disabled",
0485     "Solid color",
0486     "Color bars",
0487     "Faded color bars"
0488 };
0489 
0490 static int ar0521_init_controls(struct ar0521_dev *sensor)
0491 {
0492     const struct v4l2_ctrl_ops *ops = &ar0521_ctrl_ops;
0493     struct ar0521_ctrls *ctrls = &sensor->ctrls;
0494     struct v4l2_ctrl_handler *hdl = &ctrls->handler;
0495     int ret;
0496 
0497     v4l2_ctrl_handler_init(hdl, 32);
0498 
0499     /* We can use our own mutex for the ctrl lock */
0500     hdl->lock = &sensor->lock;
0501 
0502     /* Manual gain */
0503     ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 511, 1, 0);
0504     ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
0505                            -512, 511, 1, 0);
0506     ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
0507                         -512, 511, 1, 0);
0508     v4l2_ctrl_cluster(3, &ctrls->gain);
0509 
0510     ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
0511                       AR0521_WIDTH_BLANKING_MIN, 4094, 1,
0512                       AR0521_WIDTH_BLANKING_MIN);
0513     ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
0514                       AR0521_HEIGHT_BLANKING_MIN, 4094, 2,
0515                       AR0521_HEIGHT_BLANKING_MIN);
0516     v4l2_ctrl_cluster(2, &ctrls->hblank);
0517 
0518     /* Read-only */
0519     ctrls->pixrate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
0520                        AR0521_PIXEL_CLOCK_MIN,
0521                        AR0521_PIXEL_CLOCK_MAX, 1,
0522                        AR0521_PIXEL_CLOCK_RATE);
0523 
0524     /* Manual exposure time */
0525     ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0,
0526                         65535, 1, 360);
0527 
0528     ctrls->test_pattern = v4l2_ctrl_new_std_menu_items(hdl, ops,
0529                     V4L2_CID_TEST_PATTERN,
0530                     ARRAY_SIZE(test_pattern_menu) - 1,
0531                     0, 0, test_pattern_menu);
0532 
0533     if (hdl->error) {
0534         ret = hdl->error;
0535         goto free_ctrls;
0536     }
0537 
0538     sensor->sd.ctrl_handler = hdl;
0539     return 0;
0540 
0541 free_ctrls:
0542     v4l2_ctrl_handler_free(hdl);
0543     return ret;
0544 }
0545 
0546 #define REGS_ENTRY(a)   {(a), ARRAY_SIZE(a)}
0547 #define REGS(...)   REGS_ENTRY(((const __be16[]){__VA_ARGS__}))
0548 
0549 static const struct initial_reg {
0550     const __be16 *data; /* data[0] is register address */
0551     unsigned int count;
0552 } initial_regs[] = {
0553     REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
0554 
0555     /* PEDESTAL+2 :+2 is a workaround for 10bit mode +0.5 rounding */
0556     REGS(be(0x301E), be(0x00AA)),
0557 
0558     /* corrections_recommended_bayer */
0559     REGS(be(0x3042),
0560          be(0x0004),  /* 3042: RNC: enable b/w rnc mode */
0561          be(0x4580)), /* 3044: RNC: enable row noise correction */
0562 
0563     REGS(be(0x30D2),
0564          be(0x0000),  /* 30D2: CRM/CC: enable crm on Visible and CC rows */
0565          be(0x0000),  /* 30D4: CC: CC enabled with 16 samples per column */
0566          /* 30D6: CC: bw mode enabled/12 bit data resolution/bw mode */
0567          be(0x2FFF)),
0568 
0569     REGS(be(0x30DA),
0570          be(0x0FFF),  /* 30DA: CC: column correction clip level 2 is 0 */
0571          be(0x0FFF),  /* 30DC: CC: column correction clip level 3 is 0 */
0572          be(0x0000)), /* 30DE: CC: Group FPN correction */
0573 
0574     /* RNC: rnc scaling factor = * 54 / 64 (32 / 38 * 64 = 53.9) */
0575     REGS(be(0x30EE), be(0x1136)),
0576     REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
0577     REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
0578     REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
0579     /* FDOC:fdoc settings with fdoc every frame turned of */
0580     REGS(be(0x3180), be(0x9434)),
0581 
0582     REGS(be(0x31B0),
0583          be(0x008B),  /* 31B0: frame_preamble - FIXME check WRT lanes# */
0584          be(0x0050)), /* 31B2: line_preamble - FIXME check WRT lanes# */
0585 
0586     /* don't use continuous clock mode while shut down */
0587     REGS(be(0x31BC), be(0x068C)),
0588     REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
0589 
0590     /* analog_setup_recommended_10bit */
0591     REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
0592     REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
0593     REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
0594     REGS(be(0x342A), be(0x0018)), /* pulse_config */
0595 
0596     /* pixel_timing_recommended */
0597     REGS(be(0x3D00),
0598          /* 3D00 */ be(0x043E), be(0x4760), be(0xFFFF), be(0xFFFF),
0599          /* 3D08 */ be(0x8000), be(0x0510), be(0xAF08), be(0x0252),
0600          /* 3D10 */ be(0x486F), be(0x5D5D), be(0x8056), be(0x8313),
0601          /* 3D18 */ be(0x0087), be(0x6A48), be(0x6982), be(0x0280),
0602          /* 3D20 */ be(0x8359), be(0x8D02), be(0x8020), be(0x4882),
0603          /* 3D28 */ be(0x4269), be(0x6A95), be(0x5988), be(0x5A83),
0604          /* 3D30 */ be(0x5885), be(0x6280), be(0x6289), be(0x6097),
0605          /* 3D38 */ be(0x5782), be(0x605C), be(0xBF18), be(0x0961),
0606          /* 3D40 */ be(0x5080), be(0x2090), be(0x4390), be(0x4382),
0607          /* 3D48 */ be(0x5F8A), be(0x5D5D), be(0x9C63), be(0x8063),
0608          /* 3D50 */ be(0xA960), be(0x9757), be(0x8260), be(0x5CFF),
0609          /* 3D58 */ be(0xBF10), be(0x1681), be(0x0802), be(0x8000),
0610          /* 3D60 */ be(0x141C), be(0x6000), be(0x6022), be(0x4D80),
0611          /* 3D68 */ be(0x5C97), be(0x6A69), be(0xAC6F), be(0x4645),
0612          /* 3D70 */ be(0x4400), be(0x0513), be(0x8069), be(0x6AC6),
0613          /* 3D78 */ be(0x5F95), be(0x5F70), be(0x8040), be(0x4A81),
0614          /* 3D80 */ be(0x0300), be(0xE703), be(0x0088), be(0x4A83),
0615          /* 3D88 */ be(0x40FF), be(0xFFFF), be(0xFD70), be(0x8040),
0616          /* 3D90 */ be(0x4A85), be(0x4FA8), be(0x4F8C), be(0x0070),
0617          /* 3D98 */ be(0xBE47), be(0x8847), be(0xBC78), be(0x6B89),
0618          /* 3DA0 */ be(0x6A80), be(0x6986), be(0x6B8E), be(0x6B80),
0619          /* 3DA8 */ be(0x6980), be(0x6A88), be(0x7C9F), be(0x866B),
0620          /* 3DB0 */ be(0x8765), be(0x46FF), be(0xE365), be(0xA679),
0621          /* 3DB8 */ be(0x4A40), be(0x4580), be(0x44BC), be(0x7000),
0622          /* 3DC0 */ be(0x8040), be(0x0802), be(0x10EF), be(0x0104),
0623          /* 3DC8 */ be(0x3860), be(0x5D5D), be(0x5682), be(0x1300),
0624          /* 3DD0 */ be(0x8648), be(0x8202), be(0x8082), be(0x598A),
0625          /* 3DD8 */ be(0x0280), be(0x2048), be(0x3060), be(0x8042),
0626          /* 3DE0 */ be(0x9259), be(0x865A), be(0x8258), be(0x8562),
0627          /* 3DE8 */ be(0x8062), be(0x8560), be(0x9257), be(0x8221),
0628          /* 3DF0 */ be(0x10FF), be(0xB757), be(0x9361), be(0x1019),
0629          /* 3DF8 */ be(0x8020), be(0x9043), be(0x8E43), be(0x845F),
0630          /* 3E00 */ be(0x835D), be(0x805D), be(0x8163), be(0x8063),
0631          /* 3E08 */ be(0xA060), be(0x9157), be(0x8260), be(0x5CFF),
0632          /* 3E10 */ be(0xFFFF), be(0xFFE5), be(0x1016), be(0x2048),
0633          /* 3E18 */ be(0x0802), be(0x1C60), be(0x0014), be(0x0060),
0634          /* 3E20 */ be(0x2205), be(0x8120), be(0x908F), be(0x6A80),
0635          /* 3E28 */ be(0x6982), be(0x5F9F), be(0x6F46), be(0x4544),
0636          /* 3E30 */ be(0x0005), be(0x8013), be(0x8069), be(0x6A80),
0637          /* 3E38 */ be(0x7000), be(0x0000), be(0x0000), be(0x0000),
0638          /* 3E40 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0639          /* 3E48 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0640          /* 3E50 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0641          /* 3E58 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0642          /* 3E60 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0643          /* 3E68 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0644          /* 3E70 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0645          /* 3E78 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0646          /* 3E80 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0647          /* 3E88 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0648          /* 3E90 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0649          /* 3E98 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0650          /* 3EA0 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0651          /* 3EA8 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
0652          /* 3EB0 */ be(0x0000), be(0x0000), be(0x0000)),
0653 
0654     REGS(be(0x3EB6), be(0x004C)), /* ECL */
0655 
0656     REGS(be(0x3EBA),
0657          be(0xAAAD),  /* 3EBA */
0658          be(0x0086)), /* 3EBC: Bias currents for FSC/ECL */
0659 
0660     REGS(be(0x3EC0),
0661          be(0x1E00),  /* 3EC0: SFbin/SH mode settings */
0662          be(0x100A),  /* 3EC2: CLK divider for ramp for 10 bit 400MH */
0663          /* 3EC4: FSC clamps for HDR mode and adc comp power down co */
0664          be(0x3300),
0665          be(0xEA44),  /* 3EC6: VLN and clk gating controls */
0666          be(0x6F6F),  /* 3EC8: Txl0 and Txlo1 settings for normal mode */
0667          be(0x2F4A),  /* 3ECA: CDAC/Txlo2/RSTGHI/RSTGLO settings */
0668          be(0x0506),  /* 3ECC: RSTDHI/RSTDLO/CDAC/TXHI settings */
0669          /* 3ECE: Ramp buffer settings and Booster enable (bits 0-5) */
0670          be(0x203B),
0671          be(0x13F0),  /* 3ED0: TXLO from atest/sf bin settings */
0672          be(0xA53D),  /* 3ED2: Ramp offset */
0673          be(0x862F),  /* 3ED4: TXLO open loop/row driver settings */
0674          be(0x4081),  /* 3ED6: Txlatch fr cfpn rows/vln bias */
0675          be(0x8003),  /* 3ED8: Ramp step setting for 10 bit 400 Mhz */
0676          be(0xA580),  /* 3EDA: Ramp Offset */
0677          be(0xC000),  /* 3EDC: over range for rst and under range for sig */
0678          be(0xC103)), /* 3EDE: over range for sig and col dec clk settings */
0679 
0680     /* corrections_recommended_bayer */
0681     REGS(be(0x3F00),
0682          be(0x0017),  /* 3F00: BM_T0 */
0683          be(0x02DD),  /* 3F02: BM_T1 */
0684          /* 3F04: if Ana_gain less than 2, use noise_floor0, multipl */
0685          be(0x0020),
0686          /* 3F06: if Ana_gain between 4 and 7, use noise_floor2 and */
0687          be(0x0040),
0688          /* 3F08: if Ana_gain between 4 and 7, use noise_floor2 and */
0689          be(0x0070),
0690          /* 3F0A: Define noise_floor0(low address) and noise_floor1 */
0691          be(0x0101),
0692          be(0x0302)), /* 3F0C: Define noise_floor2 and noise_floor3 */
0693 
0694     REGS(be(0x3F10),
0695          be(0x0505),  /* 3F10: single k factor 0 */
0696          be(0x0505),  /* 3F12: single k factor 1 */
0697          be(0x0505),  /* 3F14: single k factor 2 */
0698          be(0x01FF),  /* 3F16: cross factor 0 */
0699          be(0x01FF),  /* 3F18: cross factor 1 */
0700          be(0x01FF),  /* 3F1A: cross factor 2 */
0701          be(0x0022)), /* 3F1E */
0702 
0703     /* GTH_THRES_RTN: 4max,4min filtered out of every 46 samples and */
0704     REGS(be(0x3F2C), be(0x442E)),
0705 
0706     REGS(be(0x3F3E),
0707          be(0x0000),  /* 3F3E: Switch ADC from 12 bit to 10 bit mode */
0708          be(0x1511),  /* 3F40: couple k factor 0 */
0709          be(0x1511),  /* 3F42: couple k factor 1 */
0710          be(0x0707)), /* 3F44: couple k factor 2 */
0711 };
0712 
0713 static int ar0521_power_off(struct device *dev)
0714 {
0715     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0716     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0717     int i;
0718 
0719     clk_disable_unprepare(sensor->extclk);
0720 
0721     if (sensor->reset_gpio)
0722         gpiod_set_value(sensor->reset_gpio, 1); /* assert RESET signal */
0723 
0724     for (i = ARRAY_SIZE(ar0521_supply_names) - 1; i >= 0; i--) {
0725         if (sensor->supplies[i])
0726             regulator_disable(sensor->supplies[i]);
0727     }
0728     return 0;
0729 }
0730 
0731 static int ar0521_power_on(struct device *dev)
0732 {
0733     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0734     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0735     unsigned int cnt;
0736     int ret;
0737 
0738     for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++)
0739         if (sensor->supplies[cnt]) {
0740             ret = regulator_enable(sensor->supplies[cnt]);
0741             if (ret < 0)
0742                 goto off;
0743 
0744             usleep_range(1000, 1500); /* min 1 ms */
0745         }
0746 
0747     ret = clk_prepare_enable(sensor->extclk);
0748     if (ret < 0) {
0749         v4l2_err(&sensor->sd, "error enabling sensor clock\n");
0750         goto off;
0751     }
0752     usleep_range(1000, 1500); /* min 1 ms */
0753 
0754     if (sensor->reset_gpio)
0755         /* deassert RESET signal */
0756         gpiod_set_value(sensor->reset_gpio, 0);
0757     usleep_range(4500, 5000); /* min 45000 clocks */
0758 
0759     for (cnt = 0; cnt < ARRAY_SIZE(initial_regs); cnt++)
0760         if (ar0521_write_regs(sensor, initial_regs[cnt].data,
0761                       initial_regs[cnt].count))
0762             goto off;
0763 
0764     ret = ar0521_write_reg(sensor, AR0521_REG_SERIAL_FORMAT,
0765                    AR0521_REG_SERIAL_FORMAT_MIPI |
0766                    sensor->lane_count);
0767     if (ret)
0768         goto off;
0769 
0770     /* set MIPI test mode - disabled for now */
0771     ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_TEST_MODE,
0772                    ((0x40 << sensor->lane_count) - 0x40) |
0773                    AR0521_REG_HISPI_TEST_MODE_LP11);
0774     if (ret)
0775         goto off;
0776 
0777     ret = ar0521_write_reg(sensor, AR0521_REG_ROW_SPEED, 0x110 |
0778                    4 / sensor->lane_count);
0779     if (ret)
0780         goto off;
0781 
0782     return 0;
0783 off:
0784     ar0521_power_off(dev);
0785     return ret;
0786 }
0787 
0788 static int ar0521_enum_mbus_code(struct v4l2_subdev *sd,
0789                  struct v4l2_subdev_state *sd_state,
0790                  struct v4l2_subdev_mbus_code_enum *code)
0791 {
0792     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0793 
0794     if (code->index)
0795         return -EINVAL;
0796 
0797     code->code = sensor->fmt.code;
0798     return 0;
0799 }
0800 
0801 static int ar0521_pre_streamon(struct v4l2_subdev *sd, u32 flags)
0802 {
0803     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0804     int ret;
0805 
0806     if (!(flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP))
0807         return -EACCES;
0808 
0809     ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
0810     if (ret < 0)
0811         return ret;
0812 
0813     /* Set LP-11 on clock and data lanes */
0814     ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
0815             AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE);
0816     if (ret)
0817         goto err;
0818 
0819     /* Start streaming LP-11 */
0820     ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
0821                    AR0521_REG_RESET_DEFAULTS |
0822                    AR0521_REG_RESET_STREAM);
0823     if (ret)
0824         goto err;
0825     return 0;
0826 
0827 err:
0828     pm_runtime_put(&sensor->i2c_client->dev);
0829     return ret;
0830 }
0831 
0832 static int ar0521_post_streamoff(struct v4l2_subdev *sd)
0833 {
0834     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0835 
0836     pm_runtime_put(&sensor->i2c_client->dev);
0837     return 0;
0838 }
0839 
0840 static int ar0521_s_stream(struct v4l2_subdev *sd, int enable)
0841 {
0842     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0843     int ret;
0844 
0845     mutex_lock(&sensor->lock);
0846 
0847     ret = ar0521_set_stream(sensor, enable);
0848     if (!ret)
0849         sensor->streaming = enable;
0850 
0851     mutex_unlock(&sensor->lock);
0852     return ret;
0853 }
0854 
0855 static const struct v4l2_subdev_core_ops ar0521_core_ops = {
0856     .log_status = v4l2_ctrl_subdev_log_status,
0857 };
0858 
0859 static const struct v4l2_subdev_video_ops ar0521_video_ops = {
0860     .s_stream = ar0521_s_stream,
0861     .pre_streamon = ar0521_pre_streamon,
0862     .post_streamoff = ar0521_post_streamoff,
0863 };
0864 
0865 static const struct v4l2_subdev_pad_ops ar0521_pad_ops = {
0866     .enum_mbus_code = ar0521_enum_mbus_code,
0867     .get_fmt = ar0521_get_fmt,
0868     .set_fmt = ar0521_set_fmt,
0869 };
0870 
0871 static const struct v4l2_subdev_ops ar0521_subdev_ops = {
0872     .core = &ar0521_core_ops,
0873     .video = &ar0521_video_ops,
0874     .pad = &ar0521_pad_ops,
0875 };
0876 
0877 static int __maybe_unused ar0521_suspend(struct device *dev)
0878 {
0879     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0880     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0881 
0882     if (sensor->streaming)
0883         ar0521_set_stream(sensor, 0);
0884 
0885     return 0;
0886 }
0887 
0888 static int __maybe_unused ar0521_resume(struct device *dev)
0889 {
0890     struct v4l2_subdev *sd = dev_get_drvdata(dev);
0891     struct ar0521_dev *sensor = to_ar0521_dev(sd);
0892 
0893     if (sensor->streaming)
0894         return ar0521_set_stream(sensor, 1);
0895 
0896     return 0;
0897 }
0898 
0899 static int ar0521_probe(struct i2c_client *client)
0900 {
0901     struct v4l2_fwnode_endpoint ep = {
0902         .bus_type = V4L2_MBUS_CSI2_DPHY
0903     };
0904     struct device *dev = &client->dev;
0905     struct fwnode_handle *endpoint;
0906     struct ar0521_dev *sensor;
0907     unsigned int cnt;
0908     int ret;
0909 
0910     sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
0911     if (!sensor)
0912         return -ENOMEM;
0913 
0914     sensor->i2c_client = client;
0915     sensor->fmt.width = AR0521_WIDTH_MAX;
0916     sensor->fmt.height = AR0521_HEIGHT_MAX;
0917 
0918     endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
0919                            FWNODE_GRAPH_ENDPOINT_NEXT);
0920     if (!endpoint) {
0921         dev_err(dev, "endpoint node not found\n");
0922         return -EINVAL;
0923     }
0924 
0925     ret = v4l2_fwnode_endpoint_parse(endpoint, &ep);
0926     fwnode_handle_put(endpoint);
0927     if (ret) {
0928         dev_err(dev, "could not parse endpoint\n");
0929         return ret;
0930     }
0931 
0932     if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
0933         dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
0934         return -EINVAL;
0935     }
0936 
0937     sensor->lane_count = ep.bus.mipi_csi2.num_data_lanes;
0938     switch (sensor->lane_count) {
0939     case 1:
0940     case 2:
0941     case 4:
0942         break;
0943     default:
0944         dev_err(dev, "invalid number of MIPI data lanes\n");
0945         return -EINVAL;
0946     }
0947 
0948     /* Get master clock (extclk) */
0949     sensor->extclk = devm_clk_get(dev, "extclk");
0950     if (IS_ERR(sensor->extclk)) {
0951         dev_err(dev, "failed to get extclk\n");
0952         return PTR_ERR(sensor->extclk);
0953     }
0954 
0955     sensor->extclk_freq = clk_get_rate(sensor->extclk);
0956 
0957     if (sensor->extclk_freq < AR0521_EXTCLK_MIN ||
0958         sensor->extclk_freq > AR0521_EXTCLK_MAX) {
0959         dev_err(dev, "extclk frequency out of range: %u Hz\n",
0960             sensor->extclk_freq);
0961         return -EINVAL;
0962     }
0963 
0964     /* Request optional reset pin (usually active low) and assert it */
0965     sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
0966                              GPIOD_OUT_HIGH);
0967 
0968     v4l2_i2c_subdev_init(&sensor->sd, client, &ar0521_subdev_ops);
0969 
0970     sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
0971     sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
0972     sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
0973     ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
0974     if (ret)
0975         return ret;
0976 
0977     for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) {
0978         struct regulator *supply = devm_regulator_get(dev,
0979                         ar0521_supply_names[cnt]);
0980 
0981         if (IS_ERR(supply)) {
0982             dev_info(dev, "no %s regulator found: %li\n",
0983                  ar0521_supply_names[cnt], PTR_ERR(supply));
0984             return PTR_ERR(supply);
0985         }
0986         sensor->supplies[cnt] = supply;
0987     }
0988 
0989     mutex_init(&sensor->lock);
0990 
0991     ret = ar0521_init_controls(sensor);
0992     if (ret)
0993         goto entity_cleanup;
0994 
0995     ar0521_adj_fmt(&sensor->fmt);
0996 
0997     ret = v4l2_async_register_subdev(&sensor->sd);
0998     if (ret)
0999         goto free_ctrls;
1000 
1001     /* Turn on the device and enable runtime PM */
1002     ret = ar0521_power_on(&client->dev);
1003     if (ret)
1004         goto disable;
1005     pm_runtime_set_active(&client->dev);
1006     pm_runtime_enable(&client->dev);
1007     pm_runtime_idle(&client->dev);
1008     return 0;
1009 
1010 disable:
1011     v4l2_async_unregister_subdev(&sensor->sd);
1012     media_entity_cleanup(&sensor->sd.entity);
1013 free_ctrls:
1014     v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1015 entity_cleanup:
1016     media_entity_cleanup(&sensor->sd.entity);
1017     mutex_destroy(&sensor->lock);
1018     return ret;
1019 }
1020 
1021 static int ar0521_remove(struct i2c_client *client)
1022 {
1023     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1024     struct ar0521_dev *sensor = to_ar0521_dev(sd);
1025 
1026     v4l2_async_unregister_subdev(&sensor->sd);
1027     media_entity_cleanup(&sensor->sd.entity);
1028     v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1029     pm_runtime_disable(&client->dev);
1030     if (!pm_runtime_status_suspended(&client->dev))
1031         ar0521_power_off(&client->dev);
1032     pm_runtime_set_suspended(&client->dev);
1033     mutex_destroy(&sensor->lock);
1034     return 0;
1035 }
1036 
1037 static const struct dev_pm_ops ar0521_pm_ops = {
1038     SET_SYSTEM_SLEEP_PM_OPS(ar0521_suspend, ar0521_resume)
1039     SET_RUNTIME_PM_OPS(ar0521_power_off, ar0521_power_on, NULL)
1040 };
1041 static const struct of_device_id ar0521_dt_ids[] = {
1042     {.compatible = "onnn,ar0521"},
1043     {}
1044 };
1045 MODULE_DEVICE_TABLE(of, ar0521_dt_ids);
1046 
1047 static struct i2c_driver ar0521_i2c_driver = {
1048     .driver = {
1049         .name  = "ar0521",
1050         .pm = &ar0521_pm_ops,
1051         .of_match_table = ar0521_dt_ids,
1052     },
1053     .probe_new = ar0521_probe,
1054     .remove = ar0521_remove,
1055 };
1056 
1057 module_i2c_driver(ar0521_i2c_driver);
1058 
1059 MODULE_DESCRIPTION("AR0521 MIPI Camera subdev driver");
1060 MODULE_AUTHOR("Krzysztof Hałasa <khalasa@piap.pl>");
1061 MODULE_LICENSE("GPL");
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