media/i2c/aptina-pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Aptina Sensor PLL Configuration
0004  *
0005  * Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0006  */
0007
0008 #include <linux/device.h>
0009 #include <linux/gcd.h>
0010 #include <linux/kernel.h>
0011 #include <linux/lcm.h>
0012 #include <linux/module.h>
0013
0014 #include "aptina-pll.h"
0015
0016 int aptina_pll_calculate(struct device *dev,
0017              const struct aptina_pll_limits *limits,
0018              struct aptina_pll *pll)
0019 {
0020     unsigned int mf_min;
0021     unsigned int mf_max;
0022     unsigned int p1_min;
0023     unsigned int p1_max;
0024     unsigned int p1;
0025     unsigned int div;
0026
0027     dev_dbg(dev, "PLL: ext clock %u pix clock %u\n",
0028         pll->ext_clock, pll->pix_clock);
0029
0030     if (pll->ext_clock < limits->ext_clock_min ||
0031         pll->ext_clock > limits->ext_clock_max) {
0032         dev_err(dev, "pll: invalid external clock frequency.\n");
0033         return -EINVAL;
0034     }
0035
0036     if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) {
0037         dev_err(dev, "pll: invalid pixel clock frequency.\n");
0038         return -EINVAL;
0039     }
0040
0041     /* Compute the multiplier M and combined N*P1 divisor. */
0042     div = gcd(pll->pix_clock, pll->ext_clock);
0043     pll->m = pll->pix_clock / div;
0044     div = pll->ext_clock / div;
0045
0046     /* We now have the smallest M and N*P1 values that will result in the
0047      * desired pixel clock frequency, but they might be out of the valid
0048      * range. Compute the factor by which we should multiply them given the
0049      * following constraints:
0050      *
0051      * - minimum/maximum multiplier
0052      * - minimum/maximum multiplier output clock frequency assuming the
0053      *   minimum/maximum N value
0054      * - minimum/maximum combined N*P1 divisor
0055      */
0056     mf_min = DIV_ROUND_UP(limits->m_min, pll->m);
0057     mf_min = max(mf_min, limits->out_clock_min /
0058              (pll->ext_clock / limits->n_min * pll->m));
0059     mf_min = max(mf_min, limits->n_min * limits->p1_min / div);
0060     mf_max = limits->m_max / pll->m;
0061     mf_max = min(mf_max, limits->out_clock_max /
0062             (pll->ext_clock / limits->n_max * pll->m));
0063     mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div));
0064
0065     dev_dbg(dev, "pll: mf min %u max %u\n", mf_min, mf_max);
0066     if (mf_min > mf_max) {
0067         dev_err(dev, "pll: no valid combined N*P1 divisor.\n");
0068         return -EINVAL;
0069     }
0070
0071     /*
0072      * We're looking for the highest acceptable P1 value for which a
0073      * multiplier factor MF exists that fulfills the following conditions:
0074      *
0075      * 1. p1 is in the [p1_min, p1_max] range given by the limits and is
0076      *    even
0077      * 2. mf is in the [mf_min, mf_max] range computed above
0078      * 3. div * mf is a multiple of p1, in order to compute
0079      *  n = div * mf / p1
0080      *  m = pll->m * mf
0081      * 4. the internal clock frequency, given by ext_clock / n, is in the
0082      *    [int_clock_min, int_clock_max] range given by the limits
0083      * 5. the output clock frequency, given by ext_clock / n * m, is in the
0084      *    [out_clock_min, out_clock_max] range given by the limits
0085      *
0086      * The first naive approach is to iterate over all p1 values acceptable
0087      * according to (1) and all mf values acceptable according to (2), and
0088      * stop at the first combination that fulfills (3), (4) and (5). This
0089      * has a O(n^2) complexity.
0090      *
0091      * Instead of iterating over all mf values in the [mf_min, mf_max] range
0092      * we can compute the mf increment between two acceptable values
0093      * according to (3) with
0094      *
0095      *  mf_inc = p1 / gcd(div, p1)          (6)
0096      *
0097      * and round the minimum up to the nearest multiple of mf_inc. This will
0098      * restrict the number of mf values to be checked.
0099      *
0100      * Furthermore, conditions (4) and (5) only restrict the range of
0101      * acceptable p1 and mf values by modifying the minimum and maximum
0102      * limits. (5) can be expressed as
0103      *
0104      *  ext_clock / (div * mf / p1) * m * mf >= out_clock_min
0105      *  ext_clock / (div * mf / p1) * m * mf <= out_clock_max
0106      *
0107      * or
0108      *
0109      *  p1 >= out_clock_min * div / (ext_clock * m) (7)
0110      *  p1 <= out_clock_max * div / (ext_clock * m)
0111      *
0112      * Similarly, (4) can be expressed as
0113      *
0114      *  mf >= ext_clock * p1 / (int_clock_max * div)    (8)
0115      *  mf <= ext_clock * p1 / (int_clock_min * div)
0116      *
0117      * We can thus iterate over the restricted p1 range defined by the
0118      * combination of (1) and (7), and then compute the restricted mf range
0119      * defined by the combination of (2), (6) and (8). If the resulting mf
0120      * range is not empty, any value in the mf range is acceptable. We thus
0121      * select the mf lwoer bound and the corresponding p1 value.
0122      */
0123     if (limits->p1_min == 0) {
0124         dev_err(dev, "pll: P1 minimum value must be >0.\n");
0125         return -EINVAL;
0126     }
0127
0128     p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div,
0129              pll->ext_clock * pll->m));
0130     p1_max = min(limits->p1_max, limits->out_clock_max * div /
0131              (pll->ext_clock * pll->m));
0132
0133     for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) {
0134         unsigned int mf_inc = p1 / gcd(div, p1);
0135         unsigned int mf_high;
0136         unsigned int mf_low;
0137
0138         mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1,
0139                     limits->int_clock_max * div)), mf_inc);
0140         mf_high = min(mf_max, pll->ext_clock * p1 /
0141                   (limits->int_clock_min * div));
0142
0143         if (mf_low > mf_high)
0144             continue;
0145
0146         pll->n = div * mf_low / p1;
0147         pll->m *= mf_low;
0148         pll->p1 = p1;
0149         dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1);
0150         return 0;
0151     }
0152
0153     dev_err(dev, "pll: no valid N and P1 divisors found.\n");
0154     return -EINVAL;
0155 }
0156 EXPORT_SYMBOL_GPL(aptina_pll_calculate);
0157
0158 MODULE_DESCRIPTION("Aptina PLL Helpers");
0159 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
0160 MODULE_LICENSE("GPL v2");