media/i2c/adv7604.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * adv7604 - Analog Devices ADV7604 video decoder driver
0004  *
0005  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
0006  *
0007  */
0008
0009 /*
0010  * References (c = chapter, p = page):
0011  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
0012  *      Revision 2.5, June 2010
0013  * REF_02 - Analog devices, Register map documentation, Documentation of
0014  *      the register maps, Software manual, Rev. F, June 2010
0015  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
0016  */
0017
0018 #include <linux/delay.h>
0019 #include <linux/gpio/consumer.h>
0020 #include <linux/hdmi.h>
0021 #include <linux/i2c.h>
0022 #include <linux/kernel.h>
0023 #include <linux/module.h>
0024 #include <linux/of_graph.h>
0025 #include <linux/slab.h>
0026 #include <linux/v4l2-dv-timings.h>
0027 #include <linux/videodev2.h>
0028 #include <linux/workqueue.h>
0029 #include <linux/regmap.h>
0030 #include <linux/interrupt.h>
0031
0032 #include <media/i2c/adv7604.h>
0033 #include <media/cec.h>
0034 #include <media/v4l2-ctrls.h>
0035 #include <media/v4l2-device.h>
0036 #include <media/v4l2-event.h>
0037 #include <media/v4l2-dv-timings.h>
0038 #include <media/v4l2-fwnode.h>
0039
0040 static int debug;
0041 module_param(debug, int, 0644);
0042 MODULE_PARM_DESC(debug, "debug level (0-2)");
0043
0044 MODULE_DESCRIPTION("Analog Devices ADV7604/10/11/12 video decoder driver");
0045 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
0046 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
0047 MODULE_LICENSE("GPL");
0048
0049 /* ADV7604 system clock frequency */
0050 #define ADV76XX_FSC (28636360)
0051
0052 #define ADV76XX_RGB_OUT                 (1 << 1)
0053
0054 #define ADV76XX_OP_FORMAT_SEL_8BIT          (0 << 0)
0055 #define ADV7604_OP_FORMAT_SEL_10BIT         (1 << 0)
0056 #define ADV76XX_OP_FORMAT_SEL_12BIT         (2 << 0)
0057
0058 #define ADV76XX_OP_MODE_SEL_SDR_422         (0 << 5)
0059 #define ADV7604_OP_MODE_SEL_DDR_422         (1 << 5)
0060 #define ADV76XX_OP_MODE_SEL_SDR_444         (2 << 5)
0061 #define ADV7604_OP_MODE_SEL_DDR_444         (3 << 5)
0062 #define ADV76XX_OP_MODE_SEL_SDR_422_2X          (4 << 5)
0063 #define ADV7604_OP_MODE_SEL_ADI_CM          (5 << 5)
0064
0065 #define ADV76XX_OP_CH_SEL_GBR               (0 << 5)
0066 #define ADV76XX_OP_CH_SEL_GRB               (1 << 5)
0067 #define ADV76XX_OP_CH_SEL_BGR               (2 << 5)
0068 #define ADV76XX_OP_CH_SEL_RGB               (3 << 5)
0069 #define ADV76XX_OP_CH_SEL_BRG               (4 << 5)
0070 #define ADV76XX_OP_CH_SEL_RBG               (5 << 5)
0071
0072 #define ADV76XX_OP_SWAP_CB_CR               (1 << 0)
0073
0074 #define ADV76XX_MAX_ADDRS (3)
0075
0076 #define ADV76XX_MAX_EDID_BLOCKS 4
0077
0078 enum adv76xx_type {
0079     ADV7604,
0080     ADV7611, // including ADV7610
0081     ADV7612,
0082 };
0083
0084 struct adv76xx_reg_seq {
0085     unsigned int reg;
0086     u8 val;
0087 };
0088
0089 struct adv76xx_format_info {
0090     u32 code;
0091     u8 op_ch_sel;
0092     bool rgb_out;
0093     bool swap_cb_cr;
0094     u8 op_format_sel;
0095 };
0096
0097 struct adv76xx_cfg_read_infoframe {
0098     const char *desc;
0099     u8 present_mask;
0100     u8 head_addr;
0101     u8 payload_addr;
0102 };
0103
0104 struct adv76xx_chip_info {
0105     enum adv76xx_type type;
0106
0107     bool has_afe;
0108     unsigned int max_port;
0109     unsigned int num_dv_ports;
0110
0111     unsigned int edid_enable_reg;
0112     unsigned int edid_status_reg;
0113     unsigned int edid_segment_reg;
0114     unsigned int edid_segment_mask;
0115     unsigned int edid_spa_loc_reg;
0116     unsigned int edid_spa_loc_msb_mask;
0117     unsigned int edid_spa_port_b_reg;
0118     unsigned int lcf_reg;
0119
0120     unsigned int cable_det_mask;
0121     unsigned int tdms_lock_mask;
0122     unsigned int fmt_change_digital_mask;
0123     unsigned int cp_csc;
0124
0125     unsigned int cec_irq_status;
0126     unsigned int cec_rx_enable;
0127     unsigned int cec_rx_enable_mask;
0128     bool cec_irq_swap;
0129
0130     const struct adv76xx_format_info *formats;
0131     unsigned int nformats;
0132
0133     void (*set_termination)(struct v4l2_subdev *sd, bool enable);
0134     void (*setup_irqs)(struct v4l2_subdev *sd);
0135     unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
0136     unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
0137
0138     /* 0 = AFE, 1 = HDMI */
0139     const struct adv76xx_reg_seq *recommended_settings[2];
0140     unsigned int num_recommended_settings[2];
0141
0142     unsigned long page_mask;
0143
0144     /* Masks for timings */
0145     unsigned int linewidth_mask;
0146     unsigned int field0_height_mask;
0147     unsigned int field1_height_mask;
0148     unsigned int hfrontporch_mask;
0149     unsigned int hsync_mask;
0150     unsigned int hbackporch_mask;
0151     unsigned int field0_vfrontporch_mask;
0152     unsigned int field1_vfrontporch_mask;
0153     unsigned int field0_vsync_mask;
0154     unsigned int field1_vsync_mask;
0155     unsigned int field0_vbackporch_mask;
0156     unsigned int field1_vbackporch_mask;
0157 };
0158
0159 /*
0160  **********************************************************************
0161  *
0162  *  Arrays with configuration parameters for the ADV7604
0163  *
0164  **********************************************************************
0165  */
0166
0167 struct adv76xx_state {
0168     const struct adv76xx_chip_info *info;
0169     struct adv76xx_platform_data pdata;
0170
0171     struct gpio_desc *hpd_gpio[4];
0172     struct gpio_desc *reset_gpio;
0173
0174     struct v4l2_subdev sd;
0175     struct media_pad pads[ADV76XX_PAD_MAX];
0176     unsigned int source_pad;
0177
0178     struct v4l2_ctrl_handler hdl;
0179
0180     enum adv76xx_pad selected_input;
0181
0182     struct v4l2_dv_timings timings;
0183     const struct adv76xx_format_info *format;
0184
0185     struct {
0186         u8 edid[ADV76XX_MAX_EDID_BLOCKS * 128];
0187         u32 present;
0188         unsigned blocks;
0189     } edid;
0190     u16 spa_port_a[2];
0191     struct v4l2_fract aspect_ratio;
0192     u32 rgb_quantization_range;
0193     struct delayed_work delayed_work_enable_hotplug;
0194     bool restart_stdi_once;
0195
0196     /* CEC */
0197     struct cec_adapter *cec_adap;
0198     u8   cec_addr[ADV76XX_MAX_ADDRS];
0199     u8   cec_valid_addrs;
0200     bool cec_enabled_adap;
0201
0202     /* i2c clients */
0203     struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
0204
0205     /* Regmaps */
0206     struct regmap *regmap[ADV76XX_PAGE_MAX];
0207
0208     /* controls */
0209     struct v4l2_ctrl *detect_tx_5v_ctrl;
0210     struct v4l2_ctrl *analog_sampling_phase_ctrl;
0211     struct v4l2_ctrl *free_run_color_manual_ctrl;
0212     struct v4l2_ctrl *free_run_color_ctrl;
0213     struct v4l2_ctrl *rgb_quantization_range_ctrl;
0214 };
0215
0216 static bool adv76xx_has_afe(struct adv76xx_state *state)
0217 {
0218     return state->info->has_afe;
0219 }
0220
0221 /* Unsupported timings. This device cannot support 720p30. */
0222 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
0223     V4L2_DV_BT_CEA_1280X720P30,
0224     { }
0225 };
0226
0227 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
0228 {
0229     int i;
0230
0231     for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
0232         if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
0233             return false;
0234     return true;
0235 }
0236
0237 struct adv76xx_video_standards {
0238     struct v4l2_dv_timings timings;
0239     u8 vid_std;
0240     u8 v_freq;
0241 };
0242
0243 /* sorted by number of lines */
0244 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
0245     /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
0246     { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
0247     { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
0248     { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
0249     { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
0250     { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
0251     { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
0252     { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
0253     { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
0254     /* TODO add 1920x1080P60_RB (CVT timing) */
0255     { },
0256 };
0257
0258 /* sorted by number of lines */
0259 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
0260     { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
0261     { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
0262     { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
0263     { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
0264     { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
0265     { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
0266     { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
0267     { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
0268     { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
0269     { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
0270     { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
0271     { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
0272     { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
0273     { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
0274     { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
0275     { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
0276     { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
0277     { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
0278     { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
0279     { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
0280     /* TODO add 1600X1200P60_RB (not a DMT timing) */
0281     { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
0282     { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
0283     { },
0284 };
0285
0286 /* sorted by number of lines */
0287 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
0288     { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
0289     { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
0290     { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
0291     { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
0292     { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
0293     { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
0294     { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
0295     { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
0296     { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
0297     { },
0298 };
0299
0300 /* sorted by number of lines */
0301 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
0302     { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
0303     { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
0304     { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
0305     { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
0306     { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
0307     { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
0308     { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
0309     { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
0310     { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
0311     { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
0312     { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
0313     { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
0314     { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
0315     { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
0316     { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
0317     { },
0318 };
0319
0320 static const struct v4l2_event adv76xx_ev_fmt = {
0321     .type = V4L2_EVENT_SOURCE_CHANGE,
0322     .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
0323 };
0324
0325 /* ----------------------------------------------------------------------- */
0326
0327 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
0328 {
0329     return container_of(sd, struct adv76xx_state, sd);
0330 }
0331
0332 static inline unsigned htotal(const struct v4l2_bt_timings *t)
0333 {
0334     return V4L2_DV_BT_FRAME_WIDTH(t);
0335 }
0336
0337 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
0338 {
0339     return V4L2_DV_BT_FRAME_HEIGHT(t);
0340 }
0341
0342 /* ----------------------------------------------------------------------- */
0343
0344 static int adv76xx_read_check(struct adv76xx_state *state,
0345                  int client_page, u8 reg)
0346 {
0347     struct i2c_client *client = state->i2c_clients[client_page];
0348     int err;
0349     unsigned int val;
0350
0351     err = regmap_read(state->regmap[client_page], reg, &val);
0352
0353     if (err) {
0354         v4l_err(client, "error reading %02x, %02x\n",
0355                 client->addr, reg);
0356         return err;
0357     }
0358     return val;
0359 }
0360
0361 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
0362  * size to one or more registers.
0363  *
0364  * A value of zero will be returned on success, a negative errno will
0365  * be returned in error cases.
0366  */
0367 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
0368                   unsigned int init_reg, const void *val,
0369                   size_t val_len)
0370 {
0371     struct regmap *regmap = state->regmap[client_page];
0372
0373     if (val_len > I2C_SMBUS_BLOCK_MAX)
0374         val_len = I2C_SMBUS_BLOCK_MAX;
0375
0376     return regmap_raw_write(regmap, init_reg, val, val_len);
0377 }
0378
0379 /* ----------------------------------------------------------------------- */
0380
0381 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
0382 {
0383     struct adv76xx_state *state = to_state(sd);
0384
0385     return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
0386 }
0387
0388 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0389 {
0390     struct adv76xx_state *state = to_state(sd);
0391
0392     return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
0393 }
0394
0395 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
0396                    u8 val)
0397 {
0398     return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
0399 }
0400
0401 static inline int __always_unused avlink_read(struct v4l2_subdev *sd, u8 reg)
0402 {
0403     struct adv76xx_state *state = to_state(sd);
0404
0405     return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
0406 }
0407
0408 static inline int __always_unused avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0409 {
0410     struct adv76xx_state *state = to_state(sd);
0411
0412     return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
0413 }
0414
0415 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
0416 {
0417     struct adv76xx_state *state = to_state(sd);
0418
0419     return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
0420 }
0421
0422 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0423 {
0424     struct adv76xx_state *state = to_state(sd);
0425
0426     return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
0427 }
0428
0429 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
0430                    u8 val)
0431 {
0432     return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
0433 }
0434
0435 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
0436 {
0437     struct adv76xx_state *state = to_state(sd);
0438
0439     return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
0440 }
0441
0442 static inline int __always_unused infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0443 {
0444     struct adv76xx_state *state = to_state(sd);
0445
0446     return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
0447 }
0448
0449 static inline int __always_unused afe_read(struct v4l2_subdev *sd, u8 reg)
0450 {
0451     struct adv76xx_state *state = to_state(sd);
0452
0453     return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
0454 }
0455
0456 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0457 {
0458     struct adv76xx_state *state = to_state(sd);
0459
0460     return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
0461 }
0462
0463 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
0464 {
0465     struct adv76xx_state *state = to_state(sd);
0466
0467     return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
0468 }
0469
0470 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0471 {
0472     struct adv76xx_state *state = to_state(sd);
0473
0474     return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
0475 }
0476
0477 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
0478 {
0479     return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
0480 }
0481
0482 static inline int __always_unused edid_read(struct v4l2_subdev *sd, u8 reg)
0483 {
0484     struct adv76xx_state *state = to_state(sd);
0485
0486     return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
0487 }
0488
0489 static inline int __always_unused edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0490 {
0491     struct adv76xx_state *state = to_state(sd);
0492
0493     return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
0494 }
0495
0496 static inline int edid_write_block(struct v4l2_subdev *sd,
0497                     unsigned int total_len, const u8 *val)
0498 {
0499     struct adv76xx_state *state = to_state(sd);
0500     int err = 0;
0501     int i = 0;
0502     int len = 0;
0503
0504     v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
0505                 __func__, total_len);
0506
0507     while (!err && i < total_len) {
0508         len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
0509                 I2C_SMBUS_BLOCK_MAX :
0510                 (total_len - i);
0511
0512         err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
0513                 i, val + i, len);
0514         i += len;
0515     }
0516
0517     return err;
0518 }
0519
0520 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
0521 {
0522     const struct adv76xx_chip_info *info = state->info;
0523     unsigned int i;
0524
0525     if (info->type == ADV7604) {
0526         for (i = 0; i < state->info->num_dv_ports; ++i)
0527             gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
0528     } else {
0529         for (i = 0; i < state->info->num_dv_ports; ++i)
0530             io_write_clr_set(&state->sd, 0x20, 0x80 >> i,
0531                      (!!(hpd & BIT(i))) << (7 - i));
0532     }
0533
0534     v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
0535 }
0536
0537 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
0538 {
0539     struct delayed_work *dwork = to_delayed_work(work);
0540     struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
0541                         delayed_work_enable_hotplug);
0542     struct v4l2_subdev *sd = &state->sd;
0543
0544     v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
0545
0546     adv76xx_set_hpd(state, state->edid.present);
0547 }
0548
0549 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
0550 {
0551     struct adv76xx_state *state = to_state(sd);
0552
0553     return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
0554 }
0555
0556 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
0557 {
0558     return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
0559 }
0560
0561 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0562 {
0563     struct adv76xx_state *state = to_state(sd);
0564
0565     return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
0566 }
0567
0568 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
0569 {
0570     return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
0571 }
0572
0573 static inline int __always_unused test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0574 {
0575     struct adv76xx_state *state = to_state(sd);
0576
0577     return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
0578 }
0579
0580 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
0581 {
0582     struct adv76xx_state *state = to_state(sd);
0583
0584     return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
0585 }
0586
0587 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
0588 {
0589     return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
0590 }
0591
0592 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0593 {
0594     struct adv76xx_state *state = to_state(sd);
0595
0596     return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
0597 }
0598
0599 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
0600 {
0601     return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
0602 }
0603
0604 static inline int __always_unused vdp_read(struct v4l2_subdev *sd, u8 reg)
0605 {
0606     struct adv76xx_state *state = to_state(sd);
0607
0608     return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
0609 }
0610
0611 static inline int __always_unused vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
0612 {
0613     struct adv76xx_state *state = to_state(sd);
0614
0615     return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
0616 }
0617
0618 #define ADV76XX_REG(page, offset)   (((page) << 8) | (offset))
0619 #define ADV76XX_REG_SEQ_TERM        0xffff
0620
0621 #ifdef CONFIG_VIDEO_ADV_DEBUG
0622 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
0623 {
0624     struct adv76xx_state *state = to_state(sd);
0625     unsigned int page = reg >> 8;
0626     unsigned int val;
0627     int err;
0628
0629     if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
0630         return -EINVAL;
0631
0632     reg &= 0xff;
0633     err = regmap_read(state->regmap[page], reg, &val);
0634
0635     return err ? err : val;
0636 }
0637 #endif
0638
0639 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
0640 {
0641     struct adv76xx_state *state = to_state(sd);
0642     unsigned int page = reg >> 8;
0643
0644     if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
0645         return -EINVAL;
0646
0647     reg &= 0xff;
0648
0649     return regmap_write(state->regmap[page], reg, val);
0650 }
0651
0652 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
0653                   const struct adv76xx_reg_seq *reg_seq)
0654 {
0655     unsigned int i;
0656
0657     for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
0658         adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
0659 }
0660
0661 /* -----------------------------------------------------------------------------
0662  * Format helpers
0663  */
0664
0665 static const struct adv76xx_format_info adv7604_formats[] = {
0666     { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
0667       ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
0668     { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
0669       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
0670     { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
0671       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
0672     { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
0673       ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
0674     { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
0675       ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
0676     { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
0677       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
0678     { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
0679       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
0680     { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
0681       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0682     { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
0683       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0684     { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
0685       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0686     { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
0687       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0688     { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
0689       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
0690     { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
0691       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
0692     { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
0693       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
0694     { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
0695       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
0696     { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
0697       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0698     { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
0699       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0700     { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
0701       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0702     { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
0703       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0704 };
0705
0706 static const struct adv76xx_format_info adv7611_formats[] = {
0707     { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
0708       ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
0709     { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
0710       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
0711     { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
0712       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
0713     { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
0714       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
0715     { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
0716       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
0717     { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
0718       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0719     { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
0720       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0721     { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
0722       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0723     { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
0724       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0725     { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
0726       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0727     { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
0728       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0729     { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
0730       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0731     { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
0732       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
0733 };
0734
0735 static const struct adv76xx_format_info adv7612_formats[] = {
0736     { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
0737       ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
0738     { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
0739       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
0740     { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
0741       ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
0742     { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
0743       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0744     { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
0745       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0746     { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
0747       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0748     { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
0749       ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
0750 };
0751
0752 static const struct adv76xx_format_info *
0753 adv76xx_format_info(struct adv76xx_state *state, u32 code)
0754 {
0755     unsigned int i;
0756
0757     for (i = 0; i < state->info->nformats; ++i) {
0758         if (state->info->formats[i].code == code)
0759             return &state->info->formats[i];
0760     }
0761
0762     return NULL;
0763 }
0764
0765 /* ----------------------------------------------------------------------- */
0766
0767 static inline bool is_analog_input(struct v4l2_subdev *sd)
0768 {
0769     struct adv76xx_state *state = to_state(sd);
0770
0771     return state->selected_input == ADV7604_PAD_VGA_RGB ||
0772            state->selected_input == ADV7604_PAD_VGA_COMP;
0773 }
0774
0775 static inline bool is_digital_input(struct v4l2_subdev *sd)
0776 {
0777     struct adv76xx_state *state = to_state(sd);
0778
0779     return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
0780            state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
0781            state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
0782            state->selected_input == ADV7604_PAD_HDMI_PORT_D;
0783 }
0784
0785 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
0786     .type = V4L2_DV_BT_656_1120,
0787     /* keep this initialization for compatibility with GCC < 4.4.6 */
0788     .reserved = { 0 },
0789     V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
0790         V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
0791             V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
0792         V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
0793             V4L2_DV_BT_CAP_CUSTOM)
0794 };
0795
0796 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
0797     .type = V4L2_DV_BT_656_1120,
0798     /* keep this initialization for compatibility with GCC < 4.4.6 */
0799     .reserved = { 0 },
0800     V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
0801         V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
0802             V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
0803         V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
0804             V4L2_DV_BT_CAP_CUSTOM)
0805 };
0806
0807 /*
0808  * Return the DV timings capabilities for the requested sink pad. As a special
0809  * case, pad value -1 returns the capabilities for the currently selected input.
0810  */
0811 static const struct v4l2_dv_timings_cap *
0812 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
0813 {
0814     if (pad == -1) {
0815         struct adv76xx_state *state = to_state(sd);
0816
0817         pad = state->selected_input;
0818     }
0819
0820     switch (pad) {
0821     case ADV76XX_PAD_HDMI_PORT_A:
0822     case ADV7604_PAD_HDMI_PORT_B:
0823     case ADV7604_PAD_HDMI_PORT_C:
0824     case ADV7604_PAD_HDMI_PORT_D:
0825         return &adv76xx_timings_cap_digital;
0826
0827     case ADV7604_PAD_VGA_RGB:
0828     case ADV7604_PAD_VGA_COMP:
0829     default:
0830         return &adv7604_timings_cap_analog;
0831     }
0832 }
0833
0834
0835 /* ----------------------------------------------------------------------- */
0836
0837 #ifdef CONFIG_VIDEO_ADV_DEBUG
0838 static void adv76xx_inv_register(struct v4l2_subdev *sd)
0839 {
0840     v4l2_info(sd, "0x000-0x0ff: IO Map\n");
0841     v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
0842     v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
0843     v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
0844     v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
0845     v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
0846     v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
0847     v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
0848     v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
0849     v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
0850     v4l2_info(sd, "0xa00-0xaff: Test Map\n");
0851     v4l2_info(sd, "0xb00-0xbff: CP Map\n");
0852     v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
0853 }
0854
0855 static int adv76xx_g_register(struct v4l2_subdev *sd,
0856                     struct v4l2_dbg_register *reg)
0857 {
0858     int ret;
0859
0860     ret = adv76xx_read_reg(sd, reg->reg);
0861     if (ret < 0) {
0862         v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
0863         adv76xx_inv_register(sd);
0864         return ret;
0865     }
0866
0867     reg->size = 1;
0868     reg->val = ret;
0869
0870     return 0;
0871 }
0872
0873 static int adv76xx_s_register(struct v4l2_subdev *sd,
0874                     const struct v4l2_dbg_register *reg)
0875 {
0876     int ret;
0877
0878     ret = adv76xx_write_reg(sd, reg->reg, reg->val);
0879     if (ret < 0) {
0880         v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
0881         adv76xx_inv_register(sd);
0882         return ret;
0883     }
0884
0885     return 0;
0886 }
0887 #endif
0888
0889 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
0890 {
0891     u8 value = io_read(sd, 0x6f);
0892
0893     return ((value & 0x10) >> 4)
0894          | ((value & 0x08) >> 2)
0895          | ((value & 0x04) << 0)
0896          | ((value & 0x02) << 2);
0897 }
0898
0899 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
0900 {
0901     u8 value = io_read(sd, 0x6f);
0902
0903     return value & 1;
0904 }
0905
0906 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
0907 {
0908     /*  Reads CABLE_DET_A_RAW. For input B support, need to
0909      *  account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
0910      */
0911     u8 value = io_read(sd, 0x6f);
0912
0913     return value & 1;
0914 }
0915
0916 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
0917 {
0918     struct adv76xx_state *state = to_state(sd);
0919     const struct adv76xx_chip_info *info = state->info;
0920     u16 cable_det = info->read_cable_det(sd);
0921
0922     return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
0923 }
0924
0925 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
0926         u8 prim_mode,
0927         const struct adv76xx_video_standards *predef_vid_timings,
0928         const struct v4l2_dv_timings *timings)
0929 {
0930     int i;
0931
0932     for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
0933         if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
0934                 is_digital_input(sd) ? 250000 : 1000000, false))
0935             continue;
0936         io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
0937         io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
0938                 prim_mode); /* v_freq and prim mode */
0939         return 0;
0940     }
0941
0942     return -1;
0943 }
0944
0945 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
0946         struct v4l2_dv_timings *timings)
0947 {
0948     struct adv76xx_state *state = to_state(sd);
0949     int err;
0950
0951     v4l2_dbg(1, debug, sd, "%s", __func__);
0952
0953     if (adv76xx_has_afe(state)) {
0954         /* reset to default values */
0955         io_write(sd, 0x16, 0x43);
0956         io_write(sd, 0x17, 0x5a);
0957     }
0958     /* disable embedded syncs for auto graphics mode */
0959     cp_write_clr_set(sd, 0x81, 0x10, 0x00);
0960     cp_write(sd, 0x8f, 0x00);
0961     cp_write(sd, 0x90, 0x00);
0962     cp_write(sd, 0xa2, 0x00);
0963     cp_write(sd, 0xa3, 0x00);
0964     cp_write(sd, 0xa4, 0x00);
0965     cp_write(sd, 0xa5, 0x00);
0966     cp_write(sd, 0xa6, 0x00);
0967     cp_write(sd, 0xa7, 0x00);
0968     cp_write(sd, 0xab, 0x00);
0969     cp_write(sd, 0xac, 0x00);
0970
0971     if (is_analog_input(sd)) {
0972         err = find_and_set_predefined_video_timings(sd,
0973                 0x01, adv7604_prim_mode_comp, timings);
0974         if (err)
0975             err = find_and_set_predefined_video_timings(sd,
0976                     0x02, adv7604_prim_mode_gr, timings);
0977     } else if (is_digital_input(sd)) {
0978         err = find_and_set_predefined_video_timings(sd,
0979                 0x05, adv76xx_prim_mode_hdmi_comp, timings);
0980         if (err)
0981             err = find_and_set_predefined_video_timings(sd,
0982                     0x06, adv76xx_prim_mode_hdmi_gr, timings);
0983     } else {
0984         v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
0985                 __func__, state->selected_input);
0986         err = -1;
0987     }
0988
0989
0990     return err;
0991 }
0992
0993 static void configure_custom_video_timings(struct v4l2_subdev *sd,
0994         const struct v4l2_bt_timings *bt)
0995 {
0996     struct adv76xx_state *state = to_state(sd);
0997     u32 width = htotal(bt);
0998     u32 height = vtotal(bt);
0999     u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1000     u16 cp_start_eav = width - bt->hfrontporch;
1001     u16 cp_start_vbi = height - bt->vfrontporch;
1002     u16 cp_end_vbi = bt->vsync + bt->vbackporch;
1003     u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1004         ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1005     const u8 pll[2] = {
1006         0xc0 | ((width >> 8) & 0x1f),
1007         width & 0xff
1008     };
1009
1010     v4l2_dbg(2, debug, sd, "%s\n", __func__);
1011
1012     if (is_analog_input(sd)) {
1013         /* auto graphics */
1014         io_write(sd, 0x00, 0x07); /* video std */
1015         io_write(sd, 0x01, 0x02); /* prim mode */
1016         /* enable embedded syncs for auto graphics mode */
1017         cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1018
1019         /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1020         /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1021         /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1022         if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1023                     0x16, pll, 2))
1024             v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1025
1026         /* active video - horizontal timing */
1027         cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1028         cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1029                    ((cp_start_eav >> 8) & 0x0f));
1030         cp_write(sd, 0xa4, cp_start_eav & 0xff);
1031
1032         /* active video - vertical timing */
1033         cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1034         cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1035                    ((cp_end_vbi >> 8) & 0xf));
1036         cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1037     } else if (is_digital_input(sd)) {
1038         /* set default prim_mode/vid_std for HDMI
1039            according to [REF_03, c. 4.2] */
1040         io_write(sd, 0x00, 0x02); /* video std */
1041         io_write(sd, 0x01, 0x06); /* prim mode */
1042     } else {
1043         v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1044                 __func__, state->selected_input);
1045     }
1046
1047     cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1048     cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1049     cp_write(sd, 0xab, (height >> 4) & 0xff);
1050     cp_write(sd, 0xac, (height & 0x0f) << 4);
1051 }
1052
1053 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1054 {
1055     struct adv76xx_state *state = to_state(sd);
1056     u8 offset_buf[4];
1057
1058     if (auto_offset) {
1059         offset_a = 0x3ff;
1060         offset_b = 0x3ff;
1061         offset_c = 0x3ff;
1062     }
1063
1064     v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1065             __func__, auto_offset ? "Auto" : "Manual",
1066             offset_a, offset_b, offset_c);
1067
1068     offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1069     offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1070     offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1071     offset_buf[3] = offset_c & 0x0ff;
1072
1073     /* Registers must be written in this order with no i2c access in between */
1074     if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1075             0x77, offset_buf, 4))
1076         v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1077 }
1078
1079 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1080 {
1081     struct adv76xx_state *state = to_state(sd);
1082     u8 gain_buf[4];
1083     u8 gain_man = 1;
1084     u8 agc_mode_man = 1;
1085
1086     if (auto_gain) {
1087         gain_man = 0;
1088         agc_mode_man = 0;
1089         gain_a = 0x100;
1090         gain_b = 0x100;
1091         gain_c = 0x100;
1092     }
1093
1094     v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1095             __func__, auto_gain ? "Auto" : "Manual",
1096             gain_a, gain_b, gain_c);
1097
1098     gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1099     gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1100     gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1101     gain_buf[3] = ((gain_c & 0x0ff));
1102
1103     /* Registers must be written in this order with no i2c access in between */
1104     if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1105                  0x73, gain_buf, 4))
1106         v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1107 }
1108
1109 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1110 {
1111     struct adv76xx_state *state = to_state(sd);
1112     bool rgb_output = io_read(sd, 0x02) & 0x02;
1113     bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1114     u8 y = HDMI_COLORSPACE_RGB;
1115
1116     if (hdmi_signal && (io_read(sd, 0x60) & 1))
1117         y = infoframe_read(sd, 0x01) >> 5;
1118
1119     v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1120             __func__, state->rgb_quantization_range,
1121             rgb_output, hdmi_signal);
1122
1123     adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1124     adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1125     io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1126
1127     switch (state->rgb_quantization_range) {
1128     case V4L2_DV_RGB_RANGE_AUTO:
1129         if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1130             /* Receiving analog RGB signal
1131              * Set RGB full range (0-255) */
1132             io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1133             break;
1134         }
1135
1136         if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1137             /* Receiving analog YPbPr signal
1138              * Set automode */
1139             io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1140             break;
1141         }
1142
1143         if (hdmi_signal) {
1144             /* Receiving HDMI signal
1145              * Set automode */
1146             io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1147             break;
1148         }
1149
1150         /* Receiving DVI-D signal
1151          * ADV7604 selects RGB limited range regardless of
1152          * input format (CE/IT) in automatic mode */
1153         if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1154             /* RGB limited range (16-235) */
1155             io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1156         } else {
1157             /* RGB full range (0-255) */
1158             io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1159
1160             if (is_digital_input(sd) && rgb_output) {
1161                 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1162             } else {
1163                 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1164                 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1165             }
1166         }
1167         break;
1168     case V4L2_DV_RGB_RANGE_LIMITED:
1169         if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1170             /* YCrCb limited range (16-235) */
1171             io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1172             break;
1173         }
1174
1175         if (y != HDMI_COLORSPACE_RGB)
1176             break;
1177
1178         /* RGB limited range (16-235) */
1179         io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1180
1181         break;
1182     case V4L2_DV_RGB_RANGE_FULL:
1183         if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1184             /* YCrCb full range (0-255) */
1185             io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1186             break;
1187         }
1188
1189         if (y != HDMI_COLORSPACE_RGB)
1190             break;
1191
1192         /* RGB full range (0-255) */
1193         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1194
1195         if (is_analog_input(sd) || hdmi_signal)
1196             break;
1197
1198         /* Adjust gain/offset for DVI-D signals only */
1199         if (rgb_output) {
1200             adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1201         } else {
1202             adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1203             adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1204         }
1205         break;
1206     }
1207 }
1208
1209 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1210 {
1211     struct v4l2_subdev *sd =
1212         &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1213
1214     struct adv76xx_state *state = to_state(sd);
1215
1216     switch (ctrl->id) {
1217     case V4L2_CID_BRIGHTNESS:
1218         cp_write(sd, 0x3c, ctrl->val);
1219         return 0;
1220     case V4L2_CID_CONTRAST:
1221         cp_write(sd, 0x3a, ctrl->val);
1222         return 0;
1223     case V4L2_CID_SATURATION:
1224         cp_write(sd, 0x3b, ctrl->val);
1225         return 0;
1226     case V4L2_CID_HUE:
1227         cp_write(sd, 0x3d, ctrl->val);
1228         return 0;
1229     case  V4L2_CID_DV_RX_RGB_RANGE:
1230         state->rgb_quantization_range = ctrl->val;
1231         set_rgb_quantization_range(sd);
1232         return 0;
1233     case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1234         if (!adv76xx_has_afe(state))
1235             return -EINVAL;
1236         /* Set the analog sampling phase. This is needed to find the
1237            best sampling phase for analog video: an application or
1238            driver has to try a number of phases and analyze the picture
1239            quality before settling on the best performing phase. */
1240         afe_write(sd, 0xc8, ctrl->val);
1241         return 0;
1242     case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1243         /* Use the default blue color for free running mode,
1244            or supply your own. */
1245         cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1246         return 0;
1247     case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1248         cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1249         cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1250         cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1251         return 0;
1252     }
1253     return -EINVAL;
1254 }
1255
1256 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1257 {
1258     struct v4l2_subdev *sd =
1259         &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1260
1261     if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1262         ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1263         if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1264             ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1265         return 0;
1266     }
1267     return -EINVAL;
1268 }
1269
1270 /* ----------------------------------------------------------------------- */
1271
1272 static inline bool no_power(struct v4l2_subdev *sd)
1273 {
1274     /* Entire chip or CP powered off */
1275     return io_read(sd, 0x0c) & 0x24;
1276 }
1277
1278 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1279 {
1280     struct adv76xx_state *state = to_state(sd);
1281
1282     return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1283 }
1284
1285 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1286 {
1287     struct adv76xx_state *state = to_state(sd);
1288     const struct adv76xx_chip_info *info = state->info;
1289
1290     return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1291 }
1292
1293 static inline bool is_hdmi(struct v4l2_subdev *sd)
1294 {
1295     return hdmi_read(sd, 0x05) & 0x80;
1296 }
1297
1298 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1299 {
1300     struct adv76xx_state *state = to_state(sd);
1301
1302     /*
1303      * Chips without a AFE don't expose registers for the SSPD, so just assume
1304      * that we have a lock.
1305      */
1306     if (adv76xx_has_afe(state))
1307         return false;
1308
1309     /* TODO channel 2 */
1310     return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1311 }
1312
1313 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1314 {
1315     /* TODO channel 2 */
1316     return !(cp_read(sd, 0xb1) & 0x80);
1317 }
1318
1319 static inline bool no_signal(struct v4l2_subdev *sd)
1320 {
1321     bool ret;
1322
1323     ret = no_power(sd);
1324
1325     ret |= no_lock_stdi(sd);
1326     ret |= no_lock_sspd(sd);
1327
1328     if (is_digital_input(sd)) {
1329         ret |= no_lock_tmds(sd);
1330         ret |= no_signal_tmds(sd);
1331     }
1332
1333     return ret;
1334 }
1335
1336 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1337 {
1338     struct adv76xx_state *state = to_state(sd);
1339
1340     if (!adv76xx_has_afe(state))
1341         return false;
1342
1343     /* CP has detected a non standard number of lines on the incoming
1344        video compared to what it is configured to receive by s_dv_timings */
1345     return io_read(sd, 0x12) & 0x01;
1346 }
1347
1348 static inline bool in_free_run(struct v4l2_subdev *sd)
1349 {
1350     return cp_read(sd, 0xff) & 0x10;
1351 }
1352
1353 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1354 {
1355     *status = 0;
1356     *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1357     *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1358     if (!in_free_run(sd) && no_lock_cp(sd))
1359         *status |= is_digital_input(sd) ?
1360                V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1361
1362     v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1363
1364     return 0;
1365 }
1366
1367 /* ----------------------------------------------------------------------- */
1368
1369 struct stdi_readback {
1370     u16 bl, lcf, lcvs;
1371     u8 hs_pol, vs_pol;
1372     bool interlaced;
1373 };
1374
1375 static int stdi2dv_timings(struct v4l2_subdev *sd,
1376         struct stdi_readback *stdi,
1377         struct v4l2_dv_timings *timings)
1378 {
1379     struct adv76xx_state *state = to_state(sd);
1380     u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1381     u32 pix_clk;
1382     int i;
1383
1384     for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1385         const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1386
1387         if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1388                        adv76xx_get_dv_timings_cap(sd, -1),
1389                        adv76xx_check_dv_timings, NULL))
1390             continue;
1391         if (vtotal(bt) != stdi->lcf + 1)
1392             continue;
1393         if (bt->vsync != stdi->lcvs)
1394             continue;
1395
1396         pix_clk = hfreq * htotal(bt);
1397
1398         if ((pix_clk < bt->pixelclock + 1000000) &&
1399             (pix_clk > bt->pixelclock - 1000000)) {
1400             *timings = v4l2_dv_timings_presets[i];
1401             return 0;
1402         }
1403     }
1404
1405     if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1406             (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1407             (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1408             false, timings))
1409         return 0;
1410     if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1411             (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1412             (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1413             false, state->aspect_ratio, timings))
1414         return 0;
1415
1416     v4l2_dbg(2, debug, sd,
1417         "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1418         __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1419         stdi->hs_pol, stdi->vs_pol);
1420     return -1;
1421 }
1422
1423
1424 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1425 {
1426     struct adv76xx_state *state = to_state(sd);
1427     const struct adv76xx_chip_info *info = state->info;
1428     u8 polarity;
1429
1430     if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1431         v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1432         return -1;
1433     }
1434
1435     /* read STDI */
1436     stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1437     stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1438     stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1439     stdi->interlaced = io_read(sd, 0x12) & 0x10;
1440
1441     if (adv76xx_has_afe(state)) {
1442         /* read SSPD */
1443         polarity = cp_read(sd, 0xb5);
1444         if ((polarity & 0x03) == 0x01) {
1445             stdi->hs_pol = polarity & 0x10
1446                      ? (polarity & 0x08 ? '+' : '-') : 'x';
1447             stdi->vs_pol = polarity & 0x40
1448                      ? (polarity & 0x20 ? '+' : '-') : 'x';
1449         } else {
1450             stdi->hs_pol = 'x';
1451             stdi->vs_pol = 'x';
1452         }
1453     } else {
1454         polarity = hdmi_read(sd, 0x05);
1455         stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1456         stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1457     }
1458
1459     if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1460         v4l2_dbg(2, debug, sd,
1461             "%s: signal lost during readout of STDI/SSPD\n", __func__);
1462         return -1;
1463     }
1464
1465     if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1466         v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1467         memset(stdi, 0, sizeof(struct stdi_readback));
1468         return -1;
1469     }
1470
1471     v4l2_dbg(2, debug, sd,
1472         "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1473         __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1474         stdi->hs_pol, stdi->vs_pol,
1475         stdi->interlaced ? "interlaced" : "progressive");
1476
1477     return 0;
1478 }
1479
1480 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1481             struct v4l2_enum_dv_timings *timings)
1482 {
1483     struct adv76xx_state *state = to_state(sd);
1484
1485     if (timings->pad >= state->source_pad)
1486         return -EINVAL;
1487
1488     return v4l2_enum_dv_timings_cap(timings,
1489         adv76xx_get_dv_timings_cap(sd, timings->pad),
1490         adv76xx_check_dv_timings, NULL);
1491 }
1492
1493 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1494             struct v4l2_dv_timings_cap *cap)
1495 {
1496     struct adv76xx_state *state = to_state(sd);
1497     unsigned int pad = cap->pad;
1498
1499     if (cap->pad >= state->source_pad)
1500         return -EINVAL;
1501
1502     *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1503     cap->pad = pad;
1504
1505     return 0;
1506 }
1507
1508 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1509    if the format is listed in adv76xx_timings[] */
1510 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1511         struct v4l2_dv_timings *timings)
1512 {
1513     v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1514                  is_digital_input(sd) ? 250000 : 1000000,
1515                  adv76xx_check_dv_timings, NULL);
1516 }
1517
1518 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1519 {
1520     int a, b;
1521
1522     a = hdmi_read(sd, 0x06);
1523     b = hdmi_read(sd, 0x3b);
1524     if (a < 0 || b < 0)
1525         return 0;
1526
1527     return a * 1000000 + ((b & 0x30) >> 4) * 250000;
1528 }
1529
1530 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1531 {
1532     int a, b;
1533
1534     a = hdmi_read(sd, 0x51);
1535     b = hdmi_read(sd, 0x52);
1536     if (a < 0 || b < 0)
1537         return 0;
1538
1539     return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1540 }
1541
1542 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1543 {
1544     struct adv76xx_state *state = to_state(sd);
1545     const struct adv76xx_chip_info *info = state->info;
1546     unsigned int freq, bits_per_channel, pixelrepetition;
1547
1548     freq = info->read_hdmi_pixelclock(sd);
1549     if (is_hdmi(sd)) {
1550         /* adjust for deep color mode and pixel repetition */
1551         bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1552         pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1;
1553
1554         freq = freq * 8 / bits_per_channel / pixelrepetition;
1555     }
1556
1557     return freq;
1558 }
1559
1560 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1561             struct v4l2_dv_timings *timings)
1562 {
1563     struct adv76xx_state *state = to_state(sd);
1564     const struct adv76xx_chip_info *info = state->info;
1565     struct v4l2_bt_timings *bt = &timings->bt;
1566     struct stdi_readback stdi;
1567
1568     if (!timings)
1569         return -EINVAL;
1570
1571     memset(timings, 0, sizeof(struct v4l2_dv_timings));
1572
1573     if (no_signal(sd)) {
1574         state->restart_stdi_once = true;
1575         v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1576         return -ENOLINK;
1577     }
1578
1579     /* read STDI */
1580     if (read_stdi(sd, &stdi)) {
1581         v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1582         return -ENOLINK;
1583     }
1584     bt->interlaced = stdi.interlaced ?
1585         V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1586
1587     if (is_digital_input(sd)) {
1588         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1589         u8 vic = 0;
1590         u32 w, h;
1591
1592         w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1593         h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1594
1595         if (hdmi_signal && (io_read(sd, 0x60) & 1))
1596             vic = infoframe_read(sd, 0x04);
1597
1598         if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1599             bt->width == w && bt->height == h)
1600             goto found;
1601
1602         timings->type = V4L2_DV_BT_656_1120;
1603
1604         bt->width = w;
1605         bt->height = h;
1606         bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd);
1607         bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1608         bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1609         bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1610         bt->vfrontporch = hdmi_read16(sd, 0x2a,
1611             info->field0_vfrontporch_mask) / 2;
1612         bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1613         bt->vbackporch = hdmi_read16(sd, 0x32,
1614             info->field0_vbackporch_mask) / 2;
1615         bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1616             ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1617         if (bt->interlaced == V4L2_DV_INTERLACED) {
1618             bt->height += hdmi_read16(sd, 0x0b,
1619                 info->field1_height_mask);
1620             bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1621                 info->field1_vfrontporch_mask) / 2;
1622             bt->il_vsync = hdmi_read16(sd, 0x30,
1623                 info->field1_vsync_mask) / 2;
1624             bt->il_vbackporch = hdmi_read16(sd, 0x34,
1625                 info->field1_vbackporch_mask) / 2;
1626         }
1627         adv76xx_fill_optional_dv_timings_fields(sd, timings);
1628     } else {
1629         /* find format
1630          * Since LCVS values are inaccurate [REF_03, p. 275-276],
1631          * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1632          */
1633         if (!stdi2dv_timings(sd, &stdi, timings))
1634             goto found;
1635         stdi.lcvs += 1;
1636         v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1637         if (!stdi2dv_timings(sd, &stdi, timings))
1638             goto found;
1639         stdi.lcvs -= 2;
1640         v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1641         if (stdi2dv_timings(sd, &stdi, timings)) {
1642             /*
1643              * The STDI block may measure wrong values, especially
1644              * for lcvs and lcf. If the driver can not find any
1645              * valid timing, the STDI block is restarted to measure
1646              * the video timings again. The function will return an
1647              * error, but the restart of STDI will generate a new
1648              * STDI interrupt and the format detection process will
1649              * restart.
1650              */
1651             if (state->restart_stdi_once) {
1652                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1653                 /* TODO restart STDI for Sync Channel 2 */
1654                 /* enter one-shot mode */
1655                 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1656                 /* trigger STDI restart */
1657                 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1658                 /* reset to continuous mode */
1659                 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1660                 state->restart_stdi_once = false;
1661                 return -ENOLINK;
1662             }
1663             v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1664             return -ERANGE;
1665         }
1666         state->restart_stdi_once = true;
1667     }
1668 found:
1669
1670     if (no_signal(sd)) {
1671         v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1672         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1673         return -ENOLINK;
1674     }
1675
1676     if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1677             (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1678         v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1679                 __func__, (u32)bt->pixelclock);
1680         return -ERANGE;
1681     }
1682
1683     if (debug > 1)
1684         v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1685                       timings, true);
1686
1687     return 0;
1688 }
1689
1690 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1691         struct v4l2_dv_timings *timings)
1692 {
1693     struct adv76xx_state *state = to_state(sd);
1694     struct v4l2_bt_timings *bt;
1695     int err;
1696
1697     if (!timings)
1698         return -EINVAL;
1699
1700     if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1701         v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1702         return 0;
1703     }
1704
1705     bt = &timings->bt;
1706
1707     if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1708                    adv76xx_check_dv_timings, NULL))
1709         return -ERANGE;
1710
1711     adv76xx_fill_optional_dv_timings_fields(sd, timings);
1712
1713     state->timings = *timings;
1714
1715     cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1716
1717     /* Use prim_mode and vid_std when available */
1718     err = configure_predefined_video_timings(sd, timings);
1719     if (err) {
1720         /* custom settings when the video format
1721          does not have prim_mode/vid_std */
1722         configure_custom_video_timings(sd, bt);
1723     }
1724
1725     set_rgb_quantization_range(sd);
1726
1727     if (debug > 1)
1728         v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1729                       timings, true);
1730     return 0;
1731 }
1732
1733 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1734         struct v4l2_dv_timings *timings)
1735 {
1736     struct adv76xx_state *state = to_state(sd);
1737
1738     *timings = state->timings;
1739     return 0;
1740 }
1741
1742 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1743 {
1744     hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1745 }
1746
1747 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1748 {
1749     hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1750 }
1751
1752 static void enable_input(struct v4l2_subdev *sd)
1753 {
1754     struct adv76xx_state *state = to_state(sd);
1755
1756     if (is_analog_input(sd)) {
1757         io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1758     } else if (is_digital_input(sd)) {
1759         hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1760         state->info->set_termination(sd, true);
1761         io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1762         hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1763     } else {
1764         v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1765                 __func__, state->selected_input);
1766     }
1767 }
1768
1769 static void disable_input(struct v4l2_subdev *sd)
1770 {
1771     struct adv76xx_state *state = to_state(sd);
1772
1773     hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1774     msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1775     io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1776     state->info->set_termination(sd, false);
1777 }
1778
1779 static void select_input(struct v4l2_subdev *sd)
1780 {
1781     struct adv76xx_state *state = to_state(sd);
1782     const struct adv76xx_chip_info *info = state->info;
1783
1784     if (is_analog_input(sd)) {
1785         adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1786
1787         afe_write(sd, 0x00, 0x08); /* power up ADC */
1788         afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1789         afe_write(sd, 0xc8, 0x00); /* phase control */
1790     } else if (is_digital_input(sd)) {
1791         hdmi_write(sd, 0x00, state->selected_input & 0x03);
1792
1793         adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1794
1795         if (adv76xx_has_afe(state)) {
1796             afe_write(sd, 0x00, 0xff); /* power down ADC */
1797             afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1798             afe_write(sd, 0xc8, 0x40); /* phase control */
1799         }
1800
1801         cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1802         cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1803         cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1804     } else {
1805         v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1806                 __func__, state->selected_input);
1807     }
1808 }
1809
1810 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1811         u32 input, u32 output, u32 config)
1812 {
1813     struct adv76xx_state *state = to_state(sd);
1814
1815     v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1816             __func__, input, state->selected_input);
1817
1818     if (input == state->selected_input)
1819         return 0;
1820
1821     if (input > state->info->max_port)
1822         return -EINVAL;
1823
1824     state->selected_input = input;
1825
1826     disable_input(sd);
1827     select_input(sd);
1828     enable_input(sd);
1829
1830     v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1831
1832     return 0;
1833 }
1834
1835 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1836                   struct v4l2_subdev_state *sd_state,
1837                   struct v4l2_subdev_mbus_code_enum *code)
1838 {
1839     struct adv76xx_state *state = to_state(sd);
1840
1841     if (code->index >= state->info->nformats)
1842         return -EINVAL;
1843
1844     code->code = state->info->formats[code->index].code;
1845
1846     return 0;
1847 }
1848
1849 static void adv76xx_fill_format(struct adv76xx_state *state,
1850                 struct v4l2_mbus_framefmt *format)
1851 {
1852     memset(format, 0, sizeof(*format));
1853
1854     format->width = state->timings.bt.width;
1855     format->height = state->timings.bt.height;
1856     format->field = V4L2_FIELD_NONE;
1857     format->colorspace = V4L2_COLORSPACE_SRGB;
1858
1859     if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1860         format->colorspace = (state->timings.bt.height <= 576) ?
1861             V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1862 }
1863
1864 /*
1865  * Compute the op_ch_sel value required to obtain on the bus the component order
1866  * corresponding to the selected format taking into account bus reordering
1867  * applied by the board at the output of the device.
1868  *
1869  * The following table gives the op_ch_value from the format component order
1870  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1871  * adv76xx_bus_order value in row).
1872  *
1873  *           |  GBR(0)  GRB(1)  BGR(2)  RGB(3)  BRG(4)  RBG(5)
1874  * ----------+-------------------------------------------------
1875  * RGB (NOP) |  GBR GRB BGR RGB BRG RBG
1876  * GRB (1-2) |  BGR RGB GBR GRB RBG BRG
1877  * RBG (2-3) |  GRB GBR BRG RBG BGR RGB
1878  * BGR (1-3) |  RBG BRG RGB BGR GRB GBR
1879  * BRG (ROR) |  BRG RBG GRB GBR RGB BGR
1880  * GBR (ROL) |  RGB BGR RBG BRG GBR GRB
1881  */
1882 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1883 {
1884 #define _SEL(a,b,c,d,e,f)   { \
1885     ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1886     ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1887 #define _BUS(x)         [ADV7604_BUS_ORDER_##x]
1888
1889     static const unsigned int op_ch_sel[6][6] = {
1890         _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1891         _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1892         _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1893         _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1894         _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1895         _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1896     };
1897
1898     return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1899 }
1900
1901 static void adv76xx_setup_format(struct adv76xx_state *state)
1902 {
1903     struct v4l2_subdev *sd = &state->sd;
1904
1905     io_write_clr_set(sd, 0x02, 0x02,
1906             state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1907     io_write(sd, 0x03, state->format->op_format_sel |
1908          state->pdata.op_format_mode_sel);
1909     io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1910     io_write_clr_set(sd, 0x05, 0x01,
1911             state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1912     set_rgb_quantization_range(sd);
1913 }
1914
1915 static int adv76xx_get_format(struct v4l2_subdev *sd,
1916                   struct v4l2_subdev_state *sd_state,
1917                   struct v4l2_subdev_format *format)
1918 {
1919     struct adv76xx_state *state = to_state(sd);
1920
1921     if (format->pad != state->source_pad)
1922         return -EINVAL;
1923
1924     adv76xx_fill_format(state, &format->format);
1925
1926     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1927         struct v4l2_mbus_framefmt *fmt;
1928
1929         fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1930         format->format.code = fmt->code;
1931     } else {
1932         format->format.code = state->format->code;
1933     }
1934
1935     return 0;
1936 }
1937
1938 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1939                  struct v4l2_subdev_state *sd_state,
1940                  struct v4l2_subdev_selection *sel)
1941 {
1942     struct adv76xx_state *state = to_state(sd);
1943
1944     if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1945         return -EINVAL;
1946     /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1947     if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1948         return -EINVAL;
1949
1950     sel->r.left = 0;
1951     sel->r.top  = 0;
1952     sel->r.width    = state->timings.bt.width;
1953     sel->r.height   = state->timings.bt.height;
1954
1955     return 0;
1956 }
1957
1958 static int adv76xx_set_format(struct v4l2_subdev *sd,
1959                   struct v4l2_subdev_state *sd_state,
1960                   struct v4l2_subdev_format *format)
1961 {
1962     struct adv76xx_state *state = to_state(sd);
1963     const struct adv76xx_format_info *info;
1964
1965     if (format->pad != state->source_pad)
1966         return -EINVAL;
1967
1968     info = adv76xx_format_info(state, format->format.code);
1969     if (!info)
1970         info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1971
1972     adv76xx_fill_format(state, &format->format);
1973     format->format.code = info->code;
1974
1975     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1976         struct v4l2_mbus_framefmt *fmt;
1977
1978         fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1979         fmt->code = format->format.code;
1980     } else {
1981         state->format = info;
1982         adv76xx_setup_format(state);
1983     }
1984
1985     return 0;
1986 }
1987
1988 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
1989 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1990 {
1991     struct adv76xx_state *state = to_state(sd);
1992
1993     if ((cec_read(sd, 0x11) & 0x01) == 0) {
1994         v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1995         return;
1996     }
1997
1998     if (tx_raw_status & 0x02) {
1999         v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2000              __func__);
2001         cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2002                   1, 0, 0, 0);
2003         return;
2004     }
2005     if (tx_raw_status & 0x04) {
2006         u8 status;
2007         u8 nack_cnt;
2008         u8 low_drive_cnt;
2009
2010         v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2011         /*
2012          * We set this status bit since this hardware performs
2013          * retransmissions.
2014          */
2015         status = CEC_TX_STATUS_MAX_RETRIES;
2016         nack_cnt = cec_read(sd, 0x14) & 0xf;
2017         if (nack_cnt)
2018             status |= CEC_TX_STATUS_NACK;
2019         low_drive_cnt = cec_read(sd, 0x14) >> 4;
2020         if (low_drive_cnt)
2021             status |= CEC_TX_STATUS_LOW_DRIVE;
2022         cec_transmit_done(state->cec_adap, status,
2023                   0, nack_cnt, low_drive_cnt, 0);
2024         return;
2025     }
2026     if (tx_raw_status & 0x01) {
2027         v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2028         cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2029         return;
2030     }
2031 }
2032
2033 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2034 {
2035     struct adv76xx_state *state = to_state(sd);
2036     const struct adv76xx_chip_info *info = state->info;
2037     u8 cec_irq;
2038
2039     /* cec controller */
2040     cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
2041     if (!cec_irq)
2042         return;
2043
2044     v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2045     adv76xx_cec_tx_raw_status(sd, cec_irq);
2046     if (cec_irq & 0x08) {
2047         struct cec_msg msg;
2048
2049         msg.len = cec_read(sd, 0x25) & 0x1f;
2050         if (msg.len > 16)
2051             msg.len = 16;
2052
2053         if (msg.len) {
2054             u8 i;
2055
2056             for (i = 0; i < msg.len; i++)
2057                 msg.msg[i] = cec_read(sd, i + 0x15);
2058             cec_write(sd, info->cec_rx_enable,
2059                   info->cec_rx_enable_mask); /* re-enable rx */
2060             cec_received_msg(state->cec_adap, &msg);
2061         }
2062     }
2063
2064     if (info->cec_irq_swap) {
2065         /*
2066          * Note: the bit order is swapped between 0x4d and 0x4e
2067          * on adv7604
2068          */
2069         cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2070               ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2071     }
2072     io_write(sd, info->cec_irq_status + 1, cec_irq);
2073
2074     if (handled)
2075         *handled = true;
2076 }
2077
2078 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2079 {
2080     struct adv76xx_state *state = cec_get_drvdata(adap);
2081     const struct adv76xx_chip_info *info = state->info;
2082     struct v4l2_subdev *sd = &state->sd;
2083
2084     if (!state->cec_enabled_adap && enable) {
2085         cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2086         cec_write(sd, 0x2c, 0x01);  /* cec soft reset */
2087         cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2088         /* enabled irqs: */
2089         /* tx: ready */
2090         /* tx: arbitration lost */
2091         /* tx: retry timeout */
2092         /* rx: ready */
2093         io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);
2094         cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask);
2095     } else if (state->cec_enabled_adap && !enable) {
2096         /* disable cec interrupts */
2097         io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);
2098         /* disable address mask 1-3 */
2099         cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2100         /* power down cec section */
2101         cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2102         state->cec_valid_addrs = 0;
2103     }
2104     state->cec_enabled_adap = enable;
2105     adv76xx_s_detect_tx_5v_ctrl(sd);
2106     return 0;
2107 }
2108
2109 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2110 {
2111     struct adv76xx_state *state = cec_get_drvdata(adap);
2112     struct v4l2_subdev *sd = &state->sd;
2113     unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2114
2115     if (!state->cec_enabled_adap)
2116         return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2117
2118     if (addr == CEC_LOG_ADDR_INVALID) {
2119         cec_write_clr_set(sd, 0x27, 0x70, 0);
2120         state->cec_valid_addrs = 0;
2121         return 0;
2122     }
2123
2124     for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2125         bool is_valid = state->cec_valid_addrs & (1 << i);
2126
2127         if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2128             free_idx = i;
2129         if (is_valid && state->cec_addr[i] == addr)
2130             return 0;
2131     }
2132     if (i == ADV76XX_MAX_ADDRS) {
2133         i = free_idx;
2134         if (i == ADV76XX_MAX_ADDRS)
2135             return -ENXIO;
2136     }
2137     state->cec_addr[i] = addr;
2138     state->cec_valid_addrs |= 1 << i;
2139
2140     switch (i) {
2141     case 0:
2142         /* enable address mask 0 */
2143         cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2144         /* set address for mask 0 */
2145         cec_write_clr_set(sd, 0x28, 0x0f, addr);
2146         break;
2147     case 1:
2148         /* enable address mask 1 */
2149         cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2150         /* set address for mask 1 */
2151         cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2152         break;
2153     case 2:
2154         /* enable address mask 2 */
2155         cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2156         /* set address for mask 1 */
2157         cec_write_clr_set(sd, 0x29, 0x0f, addr);
2158         break;
2159     }
2160     return 0;
2161 }
2162
2163 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2164                      u32 signal_free_time, struct cec_msg *msg)
2165 {
2166     struct adv76xx_state *state = cec_get_drvdata(adap);
2167     struct v4l2_subdev *sd = &state->sd;
2168     u8 len = msg->len;
2169     unsigned int i;
2170
2171     /*
2172      * The number of retries is the number of attempts - 1, but retry
2173      * at least once. It's not clear if a value of 0 is allowed, so
2174      * let's do at least one retry.
2175      */
2176     cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2177
2178     if (len > 16) {
2179         v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2180         return -EINVAL;
2181     }
2182
2183     /* write data */
2184     for (i = 0; i < len; i++)
2185         cec_write(sd, i, msg->msg[i]);
2186
2187     /* set length (data + header) */
2188     cec_write(sd, 0x10, len);
2189     /* start transmit, enable tx */
2190     cec_write(sd, 0x11, 0x01);
2191     return 0;
2192 }
2193
2194 static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2195     .adap_enable = adv76xx_cec_adap_enable,
2196     .adap_log_addr = adv76xx_cec_adap_log_addr,
2197     .adap_transmit = adv76xx_cec_adap_transmit,
2198 };
2199 #endif
2200
2201 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2202 {
2203     struct adv76xx_state *state = to_state(sd);
2204     const struct adv76xx_chip_info *info = state->info;
2205     const u8 irq_reg_0x43 = io_read(sd, 0x43);
2206     const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2207     const u8 irq_reg_0x70 = io_read(sd, 0x70);
2208     u8 fmt_change_digital;
2209     u8 fmt_change;
2210     u8 tx_5v;
2211
2212     if (irq_reg_0x43)
2213         io_write(sd, 0x44, irq_reg_0x43);
2214     if (irq_reg_0x70)
2215         io_write(sd, 0x71, irq_reg_0x70);
2216     if (irq_reg_0x6b)
2217         io_write(sd, 0x6c, irq_reg_0x6b);
2218
2219     v4l2_dbg(2, debug, sd, "%s: ", __func__);
2220
2221     /* format change */
2222     fmt_change = irq_reg_0x43 & 0x98;
2223     fmt_change_digital = is_digital_input(sd)
2224                ? irq_reg_0x6b & info->fmt_change_digital_mask
2225                : 0;
2226
2227     if (fmt_change || fmt_change_digital) {
2228         v4l2_dbg(1, debug, sd,
2229             "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2230             __func__, fmt_change, fmt_change_digital);
2231
2232         v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2233
2234         if (handled)
2235             *handled = true;
2236     }
2237     /* HDMI/DVI mode */
2238     if (irq_reg_0x6b & 0x01) {
2239         v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2240             (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2241         set_rgb_quantization_range(sd);
2242         if (handled)
2243             *handled = true;
2244     }
2245
2246 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2247     /* cec */
2248     adv76xx_cec_isr(sd, handled);
2249 #endif
2250
2251     /* tx 5v detect */
2252     tx_5v = irq_reg_0x70 & info->cable_det_mask;
2253     if (tx_5v) {
2254         v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2255         adv76xx_s_detect_tx_5v_ctrl(sd);
2256         if (handled)
2257             *handled = true;
2258     }
2259     return 0;
2260 }
2261
2262 static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id)
2263 {
2264     struct adv76xx_state *state = dev_id;
2265     bool handled = false;
2266
2267     adv76xx_isr(&state->sd, 0, &handled);
2268
2269     return handled ? IRQ_HANDLED : IRQ_NONE;
2270 }
2271
2272 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2273 {
2274     struct adv76xx_state *state = to_state(sd);
2275     u8 *data = NULL;
2276
2277     memset(edid->reserved, 0, sizeof(edid->reserved));
2278
2279     switch (edid->pad) {
2280     case ADV76XX_PAD_HDMI_PORT_A:
2281     case ADV7604_PAD_HDMI_PORT_B:
2282     case ADV7604_PAD_HDMI_PORT_C:
2283     case ADV7604_PAD_HDMI_PORT_D:
2284         if (state->edid.present & (1 << edid->pad))
2285             data = state->edid.edid;
2286         break;
2287     default:
2288         return -EINVAL;
2289     }
2290
2291     if (edid->start_block == 0 && edid->blocks == 0) {
2292         edid->blocks = data ? state->edid.blocks : 0;
2293         return 0;
2294     }
2295
2296     if (!data)
2297         return -ENODATA;
2298
2299     if (edid->start_block >= state->edid.blocks)
2300         return -EINVAL;
2301
2302     if (edid->start_block + edid->blocks > state->edid.blocks)
2303         edid->blocks = state->edid.blocks - edid->start_block;
2304
2305     memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2306
2307     return 0;
2308 }
2309
2310 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2311 {
2312     struct adv76xx_state *state = to_state(sd);
2313     const struct adv76xx_chip_info *info = state->info;
2314     unsigned int spa_loc;
2315     u16 pa, parent_pa;
2316     int err;
2317     int i;
2318
2319     memset(edid->reserved, 0, sizeof(edid->reserved));
2320
2321     if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2322         return -EINVAL;
2323     if (edid->start_block != 0)
2324         return -EINVAL;
2325     if (edid->blocks == 0) {
2326         /* Disable hotplug and I2C access to EDID RAM from DDC port */
2327         state->edid.present &= ~(1 << edid->pad);
2328         adv76xx_set_hpd(state, state->edid.present);
2329         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2330
2331         /* Fall back to a 16:9 aspect ratio */
2332         state->aspect_ratio.numerator = 16;
2333         state->aspect_ratio.denominator = 9;
2334
2335         if (!state->edid.present) {
2336             state->edid.blocks = 0;
2337             cec_phys_addr_invalidate(state->cec_adap);
2338         }
2339
2340         v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2341                 __func__, edid->pad, state->edid.present);
2342         return 0;
2343     }
2344     if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) {
2345         edid->blocks = ADV76XX_MAX_EDID_BLOCKS;
2346         return -E2BIG;
2347     }
2348
2349     pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2350     err = v4l2_phys_addr_validate(pa, &parent_pa, NULL);
2351     if (err)
2352         return err;
2353
2354     if (!spa_loc) {
2355         /*
2356          * There is no SPA, so just set spa_loc to 128 and pa to whatever
2357          * data is there.
2358          */
2359         spa_loc = 128;
2360         pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1];
2361     }
2362
2363     v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2364             __func__, edid->pad, state->edid.present);
2365
2366     /* Disable hotplug and I2C access to EDID RAM from DDC port */
2367     cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2368     adv76xx_set_hpd(state, 0);
2369     rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2370
2371     switch (edid->pad) {
2372     case ADV76XX_PAD_HDMI_PORT_A:
2373         state->spa_port_a[0] = pa >> 8;
2374         state->spa_port_a[1] = pa & 0xff;
2375         break;
2376     case ADV7604_PAD_HDMI_PORT_B:
2377         rep_write(sd, info->edid_spa_port_b_reg, pa >> 8);
2378         rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff);
2379         break;
2380     case ADV7604_PAD_HDMI_PORT_C:
2381         rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8);
2382         rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff);
2383         break;
2384     case ADV7604_PAD_HDMI_PORT_D:
2385         rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8);
2386         rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff);
2387         break;
2388     default:
2389         return -EINVAL;
2390     }
2391
2392     if (info->edid_spa_loc_reg) {
2393         u8 mask = info->edid_spa_loc_msb_mask;
2394
2395         rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff);
2396         rep_write_clr_set(sd, info->edid_spa_loc_reg + 1,
2397                   mask, (spa_loc & 0x100) ? mask : 0);
2398     }
2399
2400     edid->edid[spa_loc] = state->spa_port_a[0];
2401     edid->edid[spa_loc + 1] = state->spa_port_a[1];
2402
2403     memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2404     state->edid.blocks = edid->blocks;
2405     state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2406             edid->edid[0x16]);
2407     state->edid.present |= 1 << edid->pad;
2408
2409     rep_write_clr_set(sd, info->edid_segment_reg,
2410               info->edid_segment_mask, 0);
2411     err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid);
2412     if (err < 0) {
2413         v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2414         return err;
2415     }
2416     if (edid->blocks > 2) {
2417         rep_write_clr_set(sd, info->edid_segment_reg,
2418                   info->edid_segment_mask,
2419                   info->edid_segment_mask);
2420         err = edid_write_block(sd, 128 * (edid->blocks - 2),
2421                        state->edid.edid + 256);
2422         if (err < 0) {
2423             v4l2_err(sd, "error %d writing edid pad %d\n",
2424                  err, edid->pad);
2425             return err;
2426         }
2427     }
2428
2429     /* adv76xx calculates the checksums and enables I2C access to internal
2430        EDID RAM from DDC port. */
2431     rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2432
2433     for (i = 0; i < 1000; i++) {
2434         if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2435             break;
2436         mdelay(1);
2437     }
2438     if (i == 1000) {
2439         v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2440         return -EIO;
2441     }
2442     cec_s_phys_addr(state->cec_adap, parent_pa, false);
2443
2444     /* enable hotplug after 100 ms */
2445     schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2446     return 0;
2447 }
2448
2449 /*********** avi info frame CEA-861-E **************/
2450
2451 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2452     { "AVI", 0x01, 0xe0, 0x00 },
2453     { "Audio", 0x02, 0xe3, 0x1c },
2454     { "SDP", 0x04, 0xe6, 0x2a },
2455     { "Vendor", 0x10, 0xec, 0x54 }
2456 };
2457
2458 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2459                   union hdmi_infoframe *frame)
2460 {
2461     uint8_t buffer[32];
2462     u8 len;
2463     int i;
2464
2465     if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2466         v4l2_info(sd, "%s infoframe not received\n",
2467               adv76xx_cri[index].desc);
2468         return -ENOENT;
2469     }
2470
2471     for (i = 0; i < 3; i++)
2472         buffer[i] = infoframe_read(sd,
2473                        adv76xx_cri[index].head_addr + i);
2474
2475     len = buffer[2] + 1;
2476
2477     if (len + 3 > sizeof(buffer)) {
2478         v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2479              adv76xx_cri[index].desc, len);
2480         return -ENOENT;
2481     }
2482
2483     for (i = 0; i < len; i++)
2484         buffer[i + 3] = infoframe_read(sd,
2485                        adv76xx_cri[index].payload_addr + i);
2486
2487     if (hdmi_infoframe_unpack(frame, buffer, len + 3) < 0) {
2488         v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2489              adv76xx_cri[index].desc);
2490         return -ENOENT;
2491     }
2492     return 0;
2493 }
2494
2495 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2496 {
2497     int i;
2498
2499     if (!is_hdmi(sd)) {
2500         v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2501         return;
2502     }
2503
2504     for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2505         union hdmi_infoframe frame;
2506         struct i2c_client *client = v4l2_get_subdevdata(sd);
2507
2508         if (!adv76xx_read_infoframe(sd, i, &frame))
2509             hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2510     }
2511 }
2512
2513 static int adv76xx_log_status(struct v4l2_subdev *sd)
2514 {
2515     struct adv76xx_state *state = to_state(sd);
2516     const struct adv76xx_chip_info *info = state->info;
2517     struct v4l2_dv_timings timings;
2518     struct stdi_readback stdi;
2519     u8 reg_io_0x02 = io_read(sd, 0x02);
2520     u8 edid_enabled;
2521     u8 cable_det;
2522
2523     static const char * const csc_coeff_sel_rb[16] = {
2524         "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2525         "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2526         "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2527         "reserved", "reserved", "reserved", "reserved", "manual"
2528     };
2529     static const char * const input_color_space_txt[16] = {
2530         "RGB limited range (16-235)", "RGB full range (0-255)",
2531         "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2532         "xvYCC Bt.601", "xvYCC Bt.709",
2533         "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2534         "invalid", "invalid", "invalid", "invalid", "invalid",
2535         "invalid", "invalid", "automatic"
2536     };
2537     static const char * const hdmi_color_space_txt[16] = {
2538         "RGB limited range (16-235)", "RGB full range (0-255)",
2539         "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2540         "xvYCC Bt.601", "xvYCC Bt.709",
2541         "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2542         "sYCC", "opYCC 601", "opRGB", "invalid", "invalid",
2543         "invalid", "invalid", "invalid"
2544     };
2545     static const char * const rgb_quantization_range_txt[] = {
2546         "Automatic",
2547         "RGB limited range (16-235)",
2548         "RGB full range (0-255)",
2549     };
2550     static const char * const deep_color_mode_txt[4] = {
2551         "8-bits per channel",
2552         "10-bits per channel",
2553         "12-bits per channel",
2554         "16-bits per channel (not supported)"
2555     };
2556
2557     v4l2_info(sd, "-----Chip status-----\n");
2558     v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2559     edid_enabled = rep_read(sd, info->edid_status_reg);
2560     v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2561             ((edid_enabled & 0x01) ? "Yes" : "No"),
2562             ((edid_enabled & 0x02) ? "Yes" : "No"),
2563             ((edid_enabled & 0x04) ? "Yes" : "No"),
2564             ((edid_enabled & 0x08) ? "Yes" : "No"));
2565     v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2566             "enabled" : "disabled");
2567     if (state->cec_enabled_adap) {
2568         int i;
2569
2570         for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2571             bool is_valid = state->cec_valid_addrs & (1 << i);
2572
2573             if (is_valid)
2574                 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2575                       state->cec_addr[i]);
2576         }
2577     }
2578
2579     v4l2_info(sd, "-----Signal status-----\n");
2580     cable_det = info->read_cable_det(sd);
2581     v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2582             ((cable_det & 0x01) ? "Yes" : "No"),
2583             ((cable_det & 0x02) ? "Yes" : "No"),
2584             ((cable_det & 0x04) ? "Yes" : "No"),
2585             ((cable_det & 0x08) ? "Yes" : "No"));
2586     v4l2_info(sd, "TMDS signal detected: %s\n",
2587             no_signal_tmds(sd) ? "false" : "true");
2588     v4l2_info(sd, "TMDS signal locked: %s\n",
2589             no_lock_tmds(sd) ? "false" : "true");
2590     v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2591     v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2592     v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2593     v4l2_info(sd, "CP free run: %s\n",
2594             (in_free_run(sd)) ? "on" : "off");
2595     v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2596             io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2597             (io_read(sd, 0x01) & 0x70) >> 4);
2598
2599     v4l2_info(sd, "-----Video Timings-----\n");
2600     if (read_stdi(sd, &stdi))
2601         v4l2_info(sd, "STDI: not locked\n");
2602     else
2603         v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2604                 stdi.lcf, stdi.bl, stdi.lcvs,
2605                 stdi.interlaced ? "interlaced" : "progressive",
2606                 stdi.hs_pol, stdi.vs_pol);
2607     if (adv76xx_query_dv_timings(sd, &timings))
2608         v4l2_info(sd, "No video detected\n");
2609     else
2610         v4l2_print_dv_timings(sd->name, "Detected format: ",
2611                       &timings, true);
2612     v4l2_print_dv_timings(sd->name, "Configured format: ",
2613                   &state->timings, true);
2614
2615     if (no_signal(sd))
2616         return 0;
2617
2618     v4l2_info(sd, "-----Color space-----\n");
2619     v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2620             rgb_quantization_range_txt[state->rgb_quantization_range]);
2621     v4l2_info(sd, "Input color space: %s\n",
2622             input_color_space_txt[reg_io_0x02 >> 4]);
2623     v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2624             (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2625             (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2626                 "(16-235)" : "(0-255)",
2627             (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2628     v4l2_info(sd, "Color space conversion: %s\n",
2629             csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2630
2631     if (!is_digital_input(sd))
2632         return 0;
2633
2634     v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2635     v4l2_info(sd, "Digital video port selected: %c\n",
2636             (hdmi_read(sd, 0x00) & 0x03) + 'A');
2637     v4l2_info(sd, "HDCP encrypted content: %s\n",
2638             (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2639     v4l2_info(sd, "HDCP keys read: %s%s\n",
2640             (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2641             (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2642     if (is_hdmi(sd)) {
2643         bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2644         bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2645         bool audio_mute = io_read(sd, 0x65) & 0x40;
2646
2647         v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2648                 audio_pll_locked ? "locked" : "not locked",
2649                 audio_sample_packet_detect ? "detected" : "not detected",
2650                 audio_mute ? "muted" : "enabled");
2651         if (audio_pll_locked && audio_sample_packet_detect) {
2652             v4l2_info(sd, "Audio format: %s\n",
2653                     (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2654         }
2655         v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2656                 (hdmi_read(sd, 0x5c) << 8) +
2657                 (hdmi_read(sd, 0x5d) & 0xf0));
2658         v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2659                 (hdmi_read(sd, 0x5e) << 8) +
2660                 hdmi_read(sd, 0x5f));
2661         v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2662
2663         v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2664         v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2665
2666         adv76xx_log_infoframes(sd);
2667     }
2668
2669     return 0;
2670 }
2671
2672 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2673                    struct v4l2_fh *fh,
2674                    struct v4l2_event_subscription *sub)
2675 {
2676     switch (sub->type) {
2677     case V4L2_EVENT_SOURCE_CHANGE:
2678         return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2679     case V4L2_EVENT_CTRL:
2680         return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2681     default:
2682         return -EINVAL;
2683     }
2684 }
2685
2686 static int adv76xx_registered(struct v4l2_subdev *sd)
2687 {
2688     struct adv76xx_state *state = to_state(sd);
2689     struct i2c_client *client = v4l2_get_subdevdata(sd);
2690     int err;
2691
2692     err = cec_register_adapter(state->cec_adap, &client->dev);
2693     if (err)
2694         cec_delete_adapter(state->cec_adap);
2695     return err;
2696 }
2697
2698 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2699 {
2700     struct adv76xx_state *state = to_state(sd);
2701
2702     cec_unregister_adapter(state->cec_adap);
2703 }
2704
2705 /* ----------------------------------------------------------------------- */
2706
2707 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2708     .s_ctrl = adv76xx_s_ctrl,
2709     .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2710 };
2711
2712 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2713     .log_status = adv76xx_log_status,
2714     .interrupt_service_routine = adv76xx_isr,
2715     .subscribe_event = adv76xx_subscribe_event,
2716     .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2717 #ifdef CONFIG_VIDEO_ADV_DEBUG
2718     .g_register = adv76xx_g_register,
2719     .s_register = adv76xx_s_register,
2720 #endif
2721 };
2722
2723 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2724     .s_routing = adv76xx_s_routing,
2725     .g_input_status = adv76xx_g_input_status,
2726     .s_dv_timings = adv76xx_s_dv_timings,
2727     .g_dv_timings = adv76xx_g_dv_timings,
2728     .query_dv_timings = adv76xx_query_dv_timings,
2729 };
2730
2731 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2732     .enum_mbus_code = adv76xx_enum_mbus_code,
2733     .get_selection = adv76xx_get_selection,
2734     .get_fmt = adv76xx_get_format,
2735     .set_fmt = adv76xx_set_format,
2736     .get_edid = adv76xx_get_edid,
2737     .set_edid = adv76xx_set_edid,
2738     .dv_timings_cap = adv76xx_dv_timings_cap,
2739     .enum_dv_timings = adv76xx_enum_dv_timings,
2740 };
2741
2742 static const struct v4l2_subdev_ops adv76xx_ops = {
2743     .core = &adv76xx_core_ops,
2744     .video = &adv76xx_video_ops,
2745     .pad = &adv76xx_pad_ops,
2746 };
2747
2748 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2749     .registered = adv76xx_registered,
2750     .unregistered = adv76xx_unregistered,
2751 };
2752
2753 /* -------------------------- custom ctrls ---------------------------------- */
2754
2755 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2756     .ops = &adv76xx_ctrl_ops,
2757     .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2758     .name = "Analog Sampling Phase",
2759     .type = V4L2_CTRL_TYPE_INTEGER,
2760     .min = 0,
2761     .max = 0x1f,
2762     .step = 1,
2763     .def = 0,
2764 };
2765
2766 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2767     .ops = &adv76xx_ctrl_ops,
2768     .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2769     .name = "Free Running Color, Manual",
2770     .type = V4L2_CTRL_TYPE_BOOLEAN,
2771     .min = false,
2772     .max = true,
2773     .step = 1,
2774     .def = false,
2775 };
2776
2777 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2778     .ops = &adv76xx_ctrl_ops,
2779     .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2780     .name = "Free Running Color",
2781     .type = V4L2_CTRL_TYPE_INTEGER,
2782     .min = 0x0,
2783     .max = 0xffffff,
2784     .step = 0x1,
2785     .def = 0x0,
2786 };
2787
2788 /* ----------------------------------------------------------------------- */
2789
2790 struct adv76xx_register_map {
2791     const char *name;
2792     u8 default_addr;
2793 };
2794
2795 static const struct adv76xx_register_map adv76xx_default_addresses[] = {
2796     [ADV76XX_PAGE_IO] = { "main", 0x4c },
2797     [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 },
2798     [ADV76XX_PAGE_CEC] = { "cec", 0x40 },
2799     [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e },
2800     [ADV7604_PAGE_ESDP] = { "esdp", 0x38 },
2801     [ADV7604_PAGE_DPP] = { "dpp", 0x3c },
2802     [ADV76XX_PAGE_AFE] = { "afe", 0x26 },
2803     [ADV76XX_PAGE_REP] = { "rep", 0x32 },
2804     [ADV76XX_PAGE_EDID] = { "edid", 0x36 },
2805     [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 },
2806     [ADV76XX_PAGE_TEST] = { "test", 0x30 },
2807     [ADV76XX_PAGE_CP] = { "cp", 0x22 },
2808     [ADV7604_PAGE_VDP] = { "vdp", 0x24 },
2809 };
2810
2811 static int adv76xx_core_init(struct v4l2_subdev *sd)
2812 {
2813     struct adv76xx_state *state = to_state(sd);
2814     const struct adv76xx_chip_info *info = state->info;
2815     struct adv76xx_platform_data *pdata = &state->pdata;
2816
2817     hdmi_write(sd, 0x48,
2818         (pdata->disable_pwrdnb ? 0x80 : 0) |
2819         (pdata->disable_cable_det_rst ? 0x40 : 0));
2820
2821     disable_input(sd);
2822
2823     if (pdata->default_input >= 0 &&
2824         pdata->default_input < state->source_pad) {
2825         state->selected_input = pdata->default_input;
2826         select_input(sd);
2827         enable_input(sd);
2828     }
2829
2830     /* power */
2831     io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2832     io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2833     cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2834
2835     /* HPD */
2836     if (info->type != ADV7604) {
2837         /* Set manual HPD values to 0 */
2838         io_write_clr_set(sd, 0x20, 0xc0, 0);
2839         /*
2840          * Set HPA_DELAY to 200 ms and set automatic HPD control
2841          * to: internal EDID is active AND a cable is detected
2842          * AND the manual HPD control is set to 1.
2843          */
2844         hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26);
2845     }
2846
2847     /* video format */
2848     io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2849     io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2850             pdata->insert_av_codes << 2 |
2851             pdata->replicate_av_codes << 1);
2852     adv76xx_setup_format(state);
2853
2854     cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2855
2856     /* VS, HS polarities */
2857     io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2858          pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2859
2860     /* Adjust drive strength */
2861     io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2862                 pdata->dr_str_clk << 2 |
2863                 pdata->dr_str_sync);
2864
2865     cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2866     cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2867     cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2868                       ADI recommended setting [REF_01, c. 2.3.3] */
2869     cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2870                       ADI recommended setting [REF_01, c. 2.3.3] */
2871     cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2872                      for digital formats */
2873
2874     /* HDMI audio */
2875     hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2876     hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2877     hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2878
2879     /* TODO from platform data */
2880     afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2881
2882     if (adv76xx_has_afe(state)) {
2883         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2884         io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2885     }
2886
2887     /* interrupts */
2888     io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2889     io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2890     io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2891     io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2892     info->setup_irqs(sd);
2893
2894     return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2895 }
2896
2897 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2898 {
2899     io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2900 }
2901
2902 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2903 {
2904     io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2905 }
2906
2907 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2908 {
2909     io_write(sd, 0x41, 0xd0); /* disable INT2 */
2910 }
2911
2912 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2913 {
2914     unsigned int i;
2915
2916     for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i)
2917         i2c_unregister_device(state->i2c_clients[i]);
2918 }
2919
2920 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2921                            unsigned int page)
2922 {
2923     struct i2c_client *client = v4l2_get_subdevdata(sd);
2924     struct adv76xx_state *state = to_state(sd);
2925     struct adv76xx_platform_data *pdata = &state->pdata;
2926     unsigned int io_reg = 0xf2 + page;
2927     struct i2c_client *new_client;
2928
2929     if (pdata && pdata->i2c_addresses[page])
2930         new_client = i2c_new_dummy_device(client->adapter,
2931                        pdata->i2c_addresses[page]);
2932     else
2933         new_client = i2c_new_ancillary_device(client,
2934                 adv76xx_default_addresses[page].name,
2935                 adv76xx_default_addresses[page].default_addr);
2936
2937     if (!IS_ERR(new_client))
2938         io_write(sd, io_reg, new_client->addr << 1);
2939
2940     return new_client;
2941 }
2942
2943 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2944     /* reset ADI recommended settings for HDMI: */
2945     /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2946     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2947     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2948     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2949     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2950     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2951     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2952     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2953     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2954     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2955     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2956     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2957     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2958
2959     /* set ADI recommended settings for digitizer */
2960     /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2961     { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2962     { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2963     { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2964     { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2965     { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2966
2967     { ADV76XX_REG_SEQ_TERM, 0 },
2968 };
2969
2970 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2971     /* set ADI recommended settings for HDMI: */
2972     /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2973     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2974     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2975     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2976     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2977     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2978     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2979     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2980     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2981     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2982     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2983     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2984
2985     /* reset ADI recommended settings for digitizer */
2986     /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2987     { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2988     { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2989
2990     { ADV76XX_REG_SEQ_TERM, 0 },
2991 };
2992
2993 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2994     /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2995     { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2996     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2997     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2998     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2999     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3000     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3001     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3002     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3003     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3004     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
3005     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
3006
3007     { ADV76XX_REG_SEQ_TERM, 0 },
3008 };
3009
3010 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
3011     { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3012     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3013     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3014     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3015     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3016     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3017     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3018     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3019     { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3020     { ADV76XX_REG_SEQ_TERM, 0 },
3021 };
3022
3023 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
3024     [ADV7604] = {
3025         .type = ADV7604,
3026         .has_afe = true,
3027         .max_port = ADV7604_PAD_VGA_COMP,
3028         .num_dv_ports = 4,
3029         .edid_enable_reg = 0x77,
3030         .edid_status_reg = 0x7d,
3031         .edid_segment_reg = 0x77,
3032         .edid_segment_mask = 0x10,
3033         .edid_spa_loc_reg = 0x76,
3034         .edid_spa_loc_msb_mask = 0x40,
3035         .edid_spa_port_b_reg = 0x70,
3036         .lcf_reg = 0xb3,
3037         .tdms_lock_mask = 0xe0,
3038         .cable_det_mask = 0x1e,
3039         .fmt_change_digital_mask = 0xc1,
3040         .cp_csc = 0xfc,
3041         .cec_irq_status = 0x4d,
3042         .cec_rx_enable = 0x26,
3043         .cec_rx_enable_mask = 0x01,
3044         .cec_irq_swap = true,
3045         .formats = adv7604_formats,
3046         .nformats = ARRAY_SIZE(adv7604_formats),
3047         .set_termination = adv7604_set_termination,
3048         .setup_irqs = adv7604_setup_irqs,
3049         .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
3050         .read_cable_det = adv7604_read_cable_det,
3051         .recommended_settings = {
3052             [0] = adv7604_recommended_settings_afe,
3053             [1] = adv7604_recommended_settings_hdmi,
3054         },
3055         .num_recommended_settings = {
3056             [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
3057             [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
3058         },
3059         .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
3060             BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
3061             BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
3062             BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
3063             BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
3064             BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
3065             BIT(ADV7604_PAGE_VDP),
3066         .linewidth_mask = 0xfff,
3067         .field0_height_mask = 0xfff,
3068         .field1_height_mask = 0xfff,
3069         .hfrontporch_mask = 0x3ff,
3070         .hsync_mask = 0x3ff,
3071         .hbackporch_mask = 0x3ff,
3072         .field0_vfrontporch_mask = 0x1fff,
3073         .field0_vsync_mask = 0x1fff,
3074         .field0_vbackporch_mask = 0x1fff,
3075         .field1_vfrontporch_mask = 0x1fff,
3076         .field1_vsync_mask = 0x1fff,
3077         .field1_vbackporch_mask = 0x1fff,
3078     },
3079     [ADV7611] = {
3080         .type = ADV7611,
3081         .has_afe = false,
3082         .max_port = ADV76XX_PAD_HDMI_PORT_A,
3083         .num_dv_ports = 1,
3084         .edid_enable_reg = 0x74,
3085         .edid_status_reg = 0x76,
3086         .edid_segment_reg = 0x7a,
3087         .edid_segment_mask = 0x01,
3088         .lcf_reg = 0xa3,
3089         .tdms_lock_mask = 0x43,
3090         .cable_det_mask = 0x01,
3091         .fmt_change_digital_mask = 0x03,
3092         .cp_csc = 0xf4,
3093         .cec_irq_status = 0x93,
3094         .cec_rx_enable = 0x2c,
3095         .cec_rx_enable_mask = 0x02,
3096         .formats = adv7611_formats,
3097         .nformats = ARRAY_SIZE(adv7611_formats),
3098         .set_termination = adv7611_set_termination,
3099         .setup_irqs = adv7611_setup_irqs,
3100         .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3101         .read_cable_det = adv7611_read_cable_det,
3102         .recommended_settings = {
3103             [1] = adv7611_recommended_settings_hdmi,
3104         },
3105         .num_recommended_settings = {
3106             [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
3107         },
3108         .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3109             BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3110             BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
3111             BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3112         .linewidth_mask = 0x1fff,
3113         .field0_height_mask = 0x1fff,
3114         .field1_height_mask = 0x1fff,
3115         .hfrontporch_mask = 0x1fff,
3116         .hsync_mask = 0x1fff,
3117         .hbackporch_mask = 0x1fff,
3118         .field0_vfrontporch_mask = 0x3fff,
3119         .field0_vsync_mask = 0x3fff,
3120         .field0_vbackporch_mask = 0x3fff,
3121         .field1_vfrontporch_mask = 0x3fff,
3122         .field1_vsync_mask = 0x3fff,
3123         .field1_vbackporch_mask = 0x3fff,
3124     },
3125     [ADV7612] = {
3126         .type = ADV7612,
3127         .has_afe = false,
3128         .max_port = ADV76XX_PAD_HDMI_PORT_A,    /* B not supported */
3129         .num_dv_ports = 1,          /* normally 2 */
3130         .edid_enable_reg = 0x74,
3131         .edid_status_reg = 0x76,
3132         .edid_segment_reg = 0x7a,
3133         .edid_segment_mask = 0x01,
3134         .edid_spa_loc_reg = 0x70,
3135         .edid_spa_loc_msb_mask = 0x01,
3136         .edid_spa_port_b_reg = 0x52,
3137         .lcf_reg = 0xa3,
3138         .tdms_lock_mask = 0x43,
3139         .cable_det_mask = 0x01,
3140         .fmt_change_digital_mask = 0x03,
3141         .cp_csc = 0xf4,
3142         .cec_irq_status = 0x93,
3143         .cec_rx_enable = 0x2c,
3144         .cec_rx_enable_mask = 0x02,
3145         .formats = adv7612_formats,
3146         .nformats = ARRAY_SIZE(adv7612_formats),
3147         .set_termination = adv7611_set_termination,
3148         .setup_irqs = adv7612_setup_irqs,
3149         .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3150         .read_cable_det = adv7612_read_cable_det,
3151         .recommended_settings = {
3152             [1] = adv7612_recommended_settings_hdmi,
3153         },
3154         .num_recommended_settings = {
3155             [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3156         },
3157         .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3158             BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3159             BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
3160             BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3161         .linewidth_mask = 0x1fff,
3162         .field0_height_mask = 0x1fff,
3163         .field1_height_mask = 0x1fff,
3164         .hfrontporch_mask = 0x1fff,
3165         .hsync_mask = 0x1fff,
3166         .hbackporch_mask = 0x1fff,
3167         .field0_vfrontporch_mask = 0x3fff,
3168         .field0_vsync_mask = 0x3fff,
3169         .field0_vbackporch_mask = 0x3fff,
3170         .field1_vfrontporch_mask = 0x3fff,
3171         .field1_vsync_mask = 0x3fff,
3172         .field1_vbackporch_mask = 0x3fff,
3173     },
3174 };
3175
3176 static const struct i2c_device_id adv76xx_i2c_id[] = {
3177     { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3178     { "adv7610", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3179     { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3180     { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3181     { }
3182 };
3183 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3184
3185 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3186     { .compatible = "adi,adv7610", .data = &adv76xx_chip_info[ADV7611] },
3187     { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3188     { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3189     { }
3190 };
3191 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3192
3193 static int adv76xx_parse_dt(struct adv76xx_state *state)
3194 {
3195     struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
3196     struct device_node *endpoint;
3197     struct device_node *np;
3198     unsigned int flags;
3199     int ret;
3200     u32 v;
3201
3202     np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3203
3204     /* Parse the endpoint. */
3205     endpoint = of_graph_get_next_endpoint(np, NULL);
3206     if (!endpoint)
3207         return -EINVAL;
3208
3209     ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
3210     of_node_put(endpoint);
3211     if (ret)
3212         return ret;
3213
3214     if (!of_property_read_u32(np, "default-input", &v))
3215         state->pdata.default_input = v;
3216     else
3217         state->pdata.default_input = -1;
3218
3219     flags = bus_cfg.bus.parallel.flags;
3220
3221     if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3222         state->pdata.inv_hs_pol = 1;
3223
3224     if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3225         state->pdata.inv_vs_pol = 1;
3226
3227     if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3228         state->pdata.inv_llc_pol = 1;
3229
3230     if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3231         state->pdata.insert_av_codes = 1;
3232
3233     /* Disable the interrupt for now as no DT-based board uses it. */
3234     state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH;
3235
3236     /* Hardcode the remaining platform data fields. */
3237     state->pdata.disable_pwrdnb = 0;
3238     state->pdata.disable_cable_det_rst = 0;
3239     state->pdata.blank_data = 1;
3240     state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3241     state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3242     state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
3243     state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
3244     state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3245
3246     return 0;
3247 }
3248
3249 static const struct regmap_config adv76xx_regmap_cnf[] = {
3250     {
3251         .name           = "io",
3252         .reg_bits       = 8,
3253         .val_bits       = 8,
3254
3255         .max_register       = 0xff,
3256         .cache_type     = REGCACHE_NONE,
3257     },
3258     {
3259         .name           = "avlink",
3260         .reg_bits       = 8,
3261         .val_bits       = 8,
3262
3263         .max_register       = 0xff,
3264         .cache_type     = REGCACHE_NONE,
3265     },
3266     {
3267         .name           = "cec",
3268         .reg_bits       = 8,
3269         .val_bits       = 8,
3270
3271         .max_register       = 0xff,
3272         .cache_type     = REGCACHE_NONE,
3273     },
3274     {
3275         .name           = "infoframe",
3276         .reg_bits       = 8,
3277         .val_bits       = 8,
3278
3279         .max_register       = 0xff,
3280         .cache_type     = REGCACHE_NONE,
3281     },
3282     {
3283         .name           = "esdp",
3284         .reg_bits       = 8,
3285         .val_bits       = 8,
3286
3287         .max_register       = 0xff,
3288         .cache_type     = REGCACHE_NONE,
3289     },
3290     {
3291         .name           = "epp",
3292         .reg_bits       = 8,
3293         .val_bits       = 8,
3294
3295         .max_register       = 0xff,
3296         .cache_type     = REGCACHE_NONE,
3297     },
3298     {
3299         .name           = "afe",
3300         .reg_bits       = 8,
3301         .val_bits       = 8,
3302
3303         .max_register       = 0xff,
3304         .cache_type     = REGCACHE_NONE,
3305     },
3306     {
3307         .name           = "rep",
3308         .reg_bits       = 8,
3309         .val_bits       = 8,
3310
3311         .max_register       = 0xff,
3312         .cache_type     = REGCACHE_NONE,
3313     },
3314     {
3315         .name           = "edid",
3316         .reg_bits       = 8,
3317         .val_bits       = 8,
3318
3319         .max_register       = 0xff,
3320         .cache_type     = REGCACHE_NONE,
3321     },
3322
3323     {
3324         .name           = "hdmi",
3325         .reg_bits       = 8,
3326         .val_bits       = 8,
3327
3328         .max_register       = 0xff,
3329         .cache_type     = REGCACHE_NONE,
3330     },
3331     {
3332         .name           = "test",
3333         .reg_bits       = 8,
3334         .val_bits       = 8,
3335
3336         .max_register       = 0xff,
3337         .cache_type     = REGCACHE_NONE,
3338     },
3339     {
3340         .name           = "cp",
3341         .reg_bits       = 8,
3342         .val_bits       = 8,
3343
3344         .max_register       = 0xff,
3345         .cache_type     = REGCACHE_NONE,
3346     },
3347     {
3348         .name           = "vdp",
3349         .reg_bits       = 8,
3350         .val_bits       = 8,
3351
3352         .max_register       = 0xff,
3353         .cache_type     = REGCACHE_NONE,
3354     },
3355 };
3356
3357 static int configure_regmap(struct adv76xx_state *state, int region)
3358 {
3359     int err;
3360
3361     if (!state->i2c_clients[region])
3362         return -ENODEV;
3363
3364     state->regmap[region] =
3365         devm_regmap_init_i2c(state->i2c_clients[region],
3366                      &adv76xx_regmap_cnf[region]);
3367
3368     if (IS_ERR(state->regmap[region])) {
3369         err = PTR_ERR(state->regmap[region]);
3370         v4l_err(state->i2c_clients[region],
3371             "Error initializing regmap %d with error %d\n",
3372             region, err);
3373         return -EINVAL;
3374     }
3375
3376     return 0;
3377 }
3378
3379 static int configure_regmaps(struct adv76xx_state *state)
3380 {
3381     int i, err;
3382
3383     for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3384         err = configure_regmap(state, i);
3385         if (err && (err != -ENODEV))
3386             return err;
3387     }
3388     return 0;
3389 }
3390
3391 static void adv76xx_reset(struct adv76xx_state *state)
3392 {
3393     if (state->reset_gpio) {
3394         /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3395         gpiod_set_value_cansleep(state->reset_gpio, 0);
3396         usleep_range(5000, 10000);
3397         gpiod_set_value_cansleep(state->reset_gpio, 1);
3398         /* It is recommended to wait 5 ms after the low pulse before */
3399         /* an I2C write is performed to the ADV76XX. */
3400         usleep_range(5000, 10000);
3401     }
3402 }
3403
3404 static int adv76xx_probe(struct i2c_client *client,
3405              const struct i2c_device_id *id)
3406 {
3407     static const struct v4l2_dv_timings cea640x480 =
3408         V4L2_DV_BT_CEA_640X480P59_94;
3409     struct adv76xx_state *state;
3410     struct v4l2_ctrl_handler *hdl;
3411     struct v4l2_ctrl *ctrl;
3412     struct v4l2_subdev *sd;
3413     unsigned int i;
3414     unsigned int val, val2;
3415     int err;
3416
3417     /* Check if the adapter supports the needed features */
3418     if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3419         return -EIO;
3420     v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3421             client->addr << 1);
3422
3423     state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3424     if (!state)
3425         return -ENOMEM;
3426
3427     state->i2c_clients[ADV76XX_PAGE_IO] = client;
3428
3429     /* initialize variables */
3430     state->restart_stdi_once = true;
3431     state->selected_input = ~0;
3432
3433     if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3434         const struct of_device_id *oid;
3435
3436         oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3437         state->info = oid->data;
3438
3439         err = adv76xx_parse_dt(state);
3440         if (err < 0) {
3441             v4l_err(client, "DT parsing error\n");
3442             return err;
3443         }
3444     } else if (client->dev.platform_data) {
3445         struct adv76xx_platform_data *pdata = client->dev.platform_data;
3446
3447         state->info = (const struct adv76xx_chip_info *)id->driver_data;
3448         state->pdata = *pdata;
3449     } else {
3450         v4l_err(client, "No platform data!\n");
3451         return -ENODEV;
3452     }
3453
3454     /* Request GPIOs. */
3455     for (i = 0; i < state->info->num_dv_ports; ++i) {
3456         state->hpd_gpio[i] =
3457             devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3458                               GPIOD_OUT_LOW);
3459         if (IS_ERR(state->hpd_gpio[i]))
3460             return PTR_ERR(state->hpd_gpio[i]);
3461
3462         if (state->hpd_gpio[i])
3463             v4l_info(client, "Handling HPD %u GPIO\n", i);
3464     }
3465     state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3466                                 GPIOD_OUT_HIGH);
3467     if (IS_ERR(state->reset_gpio))
3468         return PTR_ERR(state->reset_gpio);
3469
3470     adv76xx_reset(state);
3471
3472     state->timings = cea640x480;
3473     state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3474
3475     sd = &state->sd;
3476     v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3477     snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3478         id->name, i2c_adapter_id(client->adapter),
3479         client->addr);
3480     sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3481     sd->internal_ops = &adv76xx_int_ops;
3482
3483     /* Configure IO Regmap region */
3484     err = configure_regmap(state, ADV76XX_PAGE_IO);
3485
3486     if (err) {
3487         v4l2_err(sd, "Error configuring IO regmap region\n");
3488         return -ENODEV;
3489     }
3490
3491     /*
3492      * Verify that the chip is present. On ADV7604 the RD_INFO register only
3493      * identifies the revision, while on ADV7611 it identifies the model as
3494      * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3495      */
3496     switch (state->info->type) {
3497     case ADV7604:
3498         err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3499         if (err) {
3500             v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3501             return -ENODEV;
3502         }
3503         if (val != 0x68) {
3504             v4l2_err(sd, "not an ADV7604 on address 0x%x\n",
3505                  client->addr << 1);
3506             return -ENODEV;
3507         }
3508         break;
3509     case ADV7611:
3510     case ADV7612:
3511         err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3512                 0xea,
3513                 &val);
3514         if (err) {
3515             v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3516             return -ENODEV;
3517         }
3518         val2 = val << 8;
3519         err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3520                 0xeb,
3521                 &val);
3522         if (err) {
3523             v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3524             return -ENODEV;
3525         }
3526         val |= val2;
3527         if ((state->info->type == ADV7611 && val != 0x2051) ||
3528             (state->info->type == ADV7612 && val != 0x2041)) {
3529             v4l2_err(sd, "not an %s on address 0x%x\n",
3530                  state->info->type == ADV7611 ? "ADV7610/11" : "ADV7612",
3531                  client->addr << 1);
3532             return -ENODEV;
3533         }
3534         break;
3535     }
3536
3537     /* control handlers */
3538     hdl = &state->hdl;
3539     v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3540
3541     v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3542             V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3543     v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3544             V4L2_CID_CONTRAST, 0, 255, 1, 128);
3545     v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3546             V4L2_CID_SATURATION, 0, 255, 1, 128);
3547     v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3548             V4L2_CID_HUE, 0, 128, 1, 0);
3549     ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3550             V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3551             0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3552     if (ctrl)
3553         ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3554
3555     state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3556             V4L2_CID_DV_RX_POWER_PRESENT, 0,
3557             (1 << state->info->num_dv_ports) - 1, 0, 0);
3558     state->rgb_quantization_range_ctrl =
3559         v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3560             V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3561             0, V4L2_DV_RGB_RANGE_AUTO);
3562
3563     /* custom controls */
3564     if (adv76xx_has_afe(state))
3565         state->analog_sampling_phase_ctrl =
3566             v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3567     state->free_run_color_manual_ctrl =
3568         v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3569     state->free_run_color_ctrl =
3570         v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3571
3572     sd->ctrl_handler = hdl;
3573     if (hdl->error) {
3574         err = hdl->error;
3575         goto err_hdl;
3576     }
3577     if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3578         err = -ENODEV;
3579         goto err_hdl;
3580     }
3581
3582     for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3583         struct i2c_client *dummy_client;
3584
3585         if (!(BIT(i) & state->info->page_mask))
3586             continue;
3587
3588         dummy_client = adv76xx_dummy_client(sd, i);
3589         if (IS_ERR(dummy_client)) {
3590             err = PTR_ERR(dummy_client);
3591             v4l2_err(sd, "failed to create i2c client %u\n", i);
3592             goto err_i2c;
3593         }
3594
3595         state->i2c_clients[i] = dummy_client;
3596     }
3597
3598     INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3599             adv76xx_delayed_work_enable_hotplug);
3600
3601     state->source_pad = state->info->num_dv_ports
3602               + (state->info->has_afe ? 2 : 0);
3603     for (i = 0; i < state->source_pad; ++i)
3604         state->pads[i].flags = MEDIA_PAD_FL_SINK;
3605     state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3606     sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3607
3608     err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3609                 state->pads);
3610     if (err)
3611         goto err_work_queues;
3612
3613     /* Configure regmaps */
3614     err = configure_regmaps(state);
3615     if (err)
3616         goto err_entity;
3617
3618     err = adv76xx_core_init(sd);
3619     if (err)
3620         goto err_entity;
3621
3622     if (client->irq) {
3623         err = devm_request_threaded_irq(&client->dev,
3624                         client->irq,
3625                         NULL, adv76xx_irq_handler,
3626                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
3627                         client->name, state);
3628         if (err)
3629             goto err_entity;
3630     }
3631
3632 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3633     state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3634         state, dev_name(&client->dev),
3635         CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
3636     err = PTR_ERR_OR_ZERO(state->cec_adap);
3637     if (err)
3638         goto err_entity;
3639 #endif
3640
3641     v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3642             client->addr << 1, client->adapter->name);
3643
3644     err = v4l2_async_register_subdev(sd);
3645     if (err)
3646         goto err_entity;
3647
3648     return 0;
3649
3650 err_entity:
3651     media_entity_cleanup(&sd->entity);
3652 err_work_queues:
3653     cancel_delayed_work(&state->delayed_work_enable_hotplug);
3654 err_i2c:
3655     adv76xx_unregister_clients(state);
3656 err_hdl:
3657     v4l2_ctrl_handler_free(hdl);
3658     return err;
3659 }
3660
3661 /* ----------------------------------------------------------------------- */
3662
3663 static int adv76xx_remove(struct i2c_client *client)
3664 {
3665     struct v4l2_subdev *sd = i2c_get_clientdata(client);
3666     struct adv76xx_state *state = to_state(sd);
3667
3668     /* disable interrupts */
3669     io_write(sd, 0x40, 0);
3670     io_write(sd, 0x41, 0);
3671     io_write(sd, 0x46, 0);
3672     io_write(sd, 0x6e, 0);
3673     io_write(sd, 0x73, 0);
3674
3675     cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3676     v4l2_async_unregister_subdev(sd);
3677     media_entity_cleanup(&sd->entity);
3678     adv76xx_unregister_clients(to_state(sd));
3679     v4l2_ctrl_handler_free(sd->ctrl_handler);
3680     return 0;
3681 }
3682
3683 /* ----------------------------------------------------------------------- */
3684
3685 static struct i2c_driver adv76xx_driver = {
3686     .driver = {
3687         .name = "adv7604",
3688         .of_match_table = of_match_ptr(adv76xx_of_id),
3689     },
3690     .probe = adv76xx_probe,
3691     .remove = adv76xx_remove,
3692     .id_table = adv76xx_i2c_id,
3693 };
3694
3695 module_i2c_driver(adv76xx_driver);