i2c/adv748x/adv748x.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Driver for Analog Devices ADV748X video decoder and HDMI receiver
0004  *
0005  * Copyright (C) 2017 Renesas Electronics Corp.
0006  *
0007  * Authors:
0008  *  Koji Matsuoka <koji.matsuoka.xm@renesas.com>
0009  *  Niklas Söderlund <niklas.soderlund@ragnatech.se>
0010  *  Kieran Bingham <kieran.bingham@ideasonboard.com>
0011  *
0012  * The ADV748x range of receivers have the following configurations:
0013  *
0014  *                  Analog   HDMI  MHL  4-Lane  1-Lane
0015  *                    In      In         CSI     CSI
0016  *       ADV7480               X    X     X
0017  *       ADV7481      X        X    X     X       X
0018  *       ADV7482      X        X          X       X
0019  */
0020
0021 #include <linux/i2c.h>
0022
0023 #ifndef _ADV748X_H_
0024 #define _ADV748X_H_
0025
0026 enum adv748x_page {
0027     ADV748X_PAGE_IO,
0028     ADV748X_PAGE_DPLL,
0029     ADV748X_PAGE_CP,
0030     ADV748X_PAGE_HDMI,
0031     ADV748X_PAGE_EDID,
0032     ADV748X_PAGE_REPEATER,
0033     ADV748X_PAGE_INFOFRAME,
0034     ADV748X_PAGE_CBUS,
0035     ADV748X_PAGE_CEC,
0036     ADV748X_PAGE_SDP,
0037     ADV748X_PAGE_TXB,
0038     ADV748X_PAGE_TXA,
0039     ADV748X_PAGE_MAX,
0040
0041     /* Fake pages for register sequences */
0042     ADV748X_PAGE_EOR,       /* End Mark */
0043 };
0044
0045 /*
0046  * Device tree port number definitions
0047  *
0048  * The ADV748X ports define the mapping between subdevices
0049  * and the device tree specification
0050  */
0051 enum adv748x_ports {
0052     ADV748X_PORT_AIN0 = 0,
0053     ADV748X_PORT_AIN1 = 1,
0054     ADV748X_PORT_AIN2 = 2,
0055     ADV748X_PORT_AIN3 = 3,
0056     ADV748X_PORT_AIN4 = 4,
0057     ADV748X_PORT_AIN5 = 5,
0058     ADV748X_PORT_AIN6 = 6,
0059     ADV748X_PORT_AIN7 = 7,
0060     ADV748X_PORT_HDMI = 8,
0061     ADV748X_PORT_TTL = 9,
0062     ADV748X_PORT_TXA = 10,
0063     ADV748X_PORT_TXB = 11,
0064     ADV748X_PORT_MAX = 12,
0065 };
0066
0067 enum adv748x_csi2_pads {
0068     ADV748X_CSI2_SINK,
0069     ADV748X_CSI2_SOURCE,
0070     ADV748X_CSI2_NR_PADS,
0071 };
0072
0073 /* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
0074 #define ADV748X_CSI2_MAX_SUBDEVS 2
0075
0076 struct adv748x_csi2 {
0077     struct adv748x_state *state;
0078     struct v4l2_mbus_framefmt format;
0079     unsigned int page;
0080     unsigned int port;
0081     unsigned int num_lanes;
0082     unsigned int active_lanes;
0083
0084     struct media_pad pads[ADV748X_CSI2_NR_PADS];
0085     struct v4l2_ctrl_handler ctrl_hdl;
0086     struct v4l2_ctrl *pixel_rate;
0087     struct v4l2_subdev *src;
0088     struct v4l2_subdev sd;
0089 };
0090
0091 #define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
0092 #define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
0093
0094 #define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL)
0095 #define is_txa(_tx) ((_tx) == &(_tx)->state->txa)
0096 #define is_txb(_tx) ((_tx) == &(_tx)->state->txb)
0097 #define is_tx(_tx) (is_txa(_tx) || is_txb(_tx))
0098
0099 #define is_afe_enabled(_state)                  \
0100     ((_state)->endpoints[ADV748X_PORT_AIN0] != NULL ||  \
0101      (_state)->endpoints[ADV748X_PORT_AIN1] != NULL ||  \
0102      (_state)->endpoints[ADV748X_PORT_AIN2] != NULL ||  \
0103      (_state)->endpoints[ADV748X_PORT_AIN3] != NULL ||  \
0104      (_state)->endpoints[ADV748X_PORT_AIN4] != NULL ||  \
0105      (_state)->endpoints[ADV748X_PORT_AIN5] != NULL ||  \
0106      (_state)->endpoints[ADV748X_PORT_AIN6] != NULL ||  \
0107      (_state)->endpoints[ADV748X_PORT_AIN7] != NULL)
0108 #define is_hdmi_enabled(_state) ((_state)->endpoints[ADV748X_PORT_HDMI] != NULL)
0109
0110 enum adv748x_hdmi_pads {
0111     ADV748X_HDMI_SINK,
0112     ADV748X_HDMI_SOURCE,
0113     ADV748X_HDMI_NR_PADS,
0114 };
0115
0116 struct adv748x_hdmi {
0117     struct media_pad pads[ADV748X_HDMI_NR_PADS];
0118     struct v4l2_ctrl_handler ctrl_hdl;
0119     struct v4l2_subdev sd;
0120     struct v4l2_mbus_framefmt format;
0121
0122     struct v4l2_dv_timings timings;
0123     struct v4l2_fract aspect_ratio;
0124
0125     struct adv748x_csi2 *tx;
0126
0127     struct {
0128         u8 edid[512];
0129         u32 present;
0130         unsigned int blocks;
0131     } edid;
0132 };
0133
0134 #define adv748x_ctrl_to_hdmi(ctrl) \
0135     container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
0136 #define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
0137
0138 enum adv748x_afe_pads {
0139     ADV748X_AFE_SINK_AIN0,
0140     ADV748X_AFE_SINK_AIN1,
0141     ADV748X_AFE_SINK_AIN2,
0142     ADV748X_AFE_SINK_AIN3,
0143     ADV748X_AFE_SINK_AIN4,
0144     ADV748X_AFE_SINK_AIN5,
0145     ADV748X_AFE_SINK_AIN6,
0146     ADV748X_AFE_SINK_AIN7,
0147     ADV748X_AFE_SOURCE,
0148     ADV748X_AFE_NR_PADS,
0149 };
0150
0151 struct adv748x_afe {
0152     struct media_pad pads[ADV748X_AFE_NR_PADS];
0153     struct v4l2_ctrl_handler ctrl_hdl;
0154     struct v4l2_subdev sd;
0155     struct v4l2_mbus_framefmt format;
0156
0157     struct adv748x_csi2 *tx;
0158
0159     bool streaming;
0160     v4l2_std_id curr_norm;
0161     unsigned int input;
0162 };
0163
0164 #define adv748x_ctrl_to_afe(ctrl) \
0165     container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
0166 #define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
0167
0168 /**
0169  * struct adv748x_state - State of ADV748X
0170  * @dev:        (OF) device
0171  * @client:     I2C client
0172  * @mutex:      protect global state
0173  *
0174  * @endpoints:      parsed device node endpoints for each port
0175  *
0176  * @i2c_addresses:  I2C Page addresses
0177  * @i2c_clients:    I2C clients for the page accesses
0178  * @regmap:     regmap configuration pages.
0179  *
0180  * @hdmi:       state of HDMI receiver context
0181  * @afe:        state of AFE receiver context
0182  * @txa:        state of TXA transmitter context
0183  * @txb:        state of TXB transmitter context
0184  */
0185 struct adv748x_state {
0186     struct device *dev;
0187     struct i2c_client *client;
0188     struct mutex mutex;
0189
0190     struct device_node *endpoints[ADV748X_PORT_MAX];
0191
0192     struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
0193     struct regmap *regmap[ADV748X_PAGE_MAX];
0194
0195     struct adv748x_hdmi hdmi;
0196     struct adv748x_afe afe;
0197     struct adv748x_csi2 txa;
0198     struct adv748x_csi2 txb;
0199 };
0200
0201 #define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
0202 #define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
0203
0204 #define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg)
0205 #define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
0206 #define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg)
0207
0208 /* Register Mappings */
0209
0210 /* IO Map */
0211 #define ADV748X_IO_PD           0x00    /* power down controls */
0212 #define ADV748X_IO_PD_RX_EN     BIT(6)
0213
0214 #define ADV748X_IO_REG_01       0x01    /* pwrdn{2}b, prog_xtal_freq */
0215 #define ADV748X_IO_REG_01_PWRDN_MASK    (BIT(7) | BIT(6))
0216 #define ADV748X_IO_REG_01_PWRDN2B   BIT(7)  /* CEC Wakeup Support */
0217 #define ADV748X_IO_REG_01_PWRDNB    BIT(6)  /* CEC Wakeup Support */
0218
0219 #define ADV748X_IO_REG_04       0x04
0220 #define ADV748X_IO_REG_04_FORCE_FR  BIT(0)  /* Force CP free-run */
0221
0222 #define ADV748X_IO_DATAPATH     0x03    /* datapath cntrl */
0223 #define ADV748X_IO_DATAPATH_VFREQ_M 0x70
0224 #define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4
0225
0226 #define ADV748X_IO_VID_STD      0x05
0227
0228 #define ADV748X_IO_10           0x10    /* io_reg_10 */
0229 #define ADV748X_IO_10_CSI4_EN       BIT(7)
0230 #define ADV748X_IO_10_CSI1_EN       BIT(6)
0231 #define ADV748X_IO_10_PIX_OUT_EN    BIT(5)
0232 #define ADV748X_IO_10_CSI4_IN_SEL_AFE   BIT(3)
0233
0234 #define ADV748X_IO_CHIP_REV_ID_1    0xdf
0235 #define ADV748X_IO_CHIP_REV_ID_2    0xe0
0236
0237 #define ADV748X_IO_REG_F2       0xf2
0238 #define ADV748X_IO_REG_F2_READ_AUTO_INC BIT(0)
0239
0240 /* For PAGE slave address offsets */
0241 #define ADV748X_IO_SLAVE_ADDR_BASE  0xf2
0242
0243 /*
0244  * The ADV748x_Recommended_Settings_PrA_2014-08-20.pdf details both 0x80 and
0245  * 0xff as examples for performing a software reset.
0246  */
0247 #define ADV748X_IO_REG_FF       0xff
0248 #define ADV748X_IO_REG_FF_MAIN_RESET    0xff
0249
0250 /* HDMI RX Map */
0251 #define ADV748X_HDMI_LW1        0x07    /* line width_1 */
0252 #define ADV748X_HDMI_LW1_VERT_FILTER    BIT(7)
0253 #define ADV748X_HDMI_LW1_DE_REGEN   BIT(5)
0254 #define ADV748X_HDMI_LW1_WIDTH_MASK 0x1fff
0255
0256 #define ADV748X_HDMI_F0H1       0x09    /* field0 height_1 */
0257 #define ADV748X_HDMI_F0H1_HEIGHT_MASK   0x1fff
0258
0259 #define ADV748X_HDMI_F1H1       0x0b    /* field1 height_1 */
0260 #define ADV748X_HDMI_F1H1_INTERLACED    BIT(5)
0261
0262 #define ADV748X_HDMI_HFRONT_PORCH   0x20    /* hsync_front_porch_1 */
0263 #define ADV748X_HDMI_HFRONT_PORCH_MASK  0x1fff
0264
0265 #define ADV748X_HDMI_HSYNC_WIDTH    0x22    /* hsync_pulse_width_1 */
0266 #define ADV748X_HDMI_HSYNC_WIDTH_MASK   0x1fff
0267
0268 #define ADV748X_HDMI_HBACK_PORCH    0x24    /* hsync_back_porch_1 */
0269 #define ADV748X_HDMI_HBACK_PORCH_MASK   0x1fff
0270
0271 #define ADV748X_HDMI_VFRONT_PORCH   0x2a    /* field0_vs_front_porch_1 */
0272 #define ADV748X_HDMI_VFRONT_PORCH_MASK  0x3fff
0273
0274 #define ADV748X_HDMI_VSYNC_WIDTH    0x2e    /* field0_vs_pulse_width_1 */
0275 #define ADV748X_HDMI_VSYNC_WIDTH_MASK   0x3fff
0276
0277 #define ADV748X_HDMI_VBACK_PORCH    0x32    /* field0_vs_back_porch_1 */
0278 #define ADV748X_HDMI_VBACK_PORCH_MASK   0x3fff
0279
0280 #define ADV748X_HDMI_TMDS_1     0x51    /* hdmi_reg_51 */
0281 #define ADV748X_HDMI_TMDS_2     0x52    /* hdmi_reg_52 */
0282
0283 /* HDMI RX Repeater Map */
0284 #define ADV748X_REPEATER_EDID_SZ    0x70    /* primary_edid_size */
0285 #define ADV748X_REPEATER_EDID_SZ_SHIFT  4
0286
0287 #define ADV748X_REPEATER_EDID_CTL   0x74    /* hdcp edid controls */
0288 #define ADV748X_REPEATER_EDID_CTL_EN    BIT(0)  /* man_edid_a_enable */
0289
0290 /* SDP Main Map */
0291 #define ADV748X_SDP_INSEL       0x00    /* user_map_rw_reg_00 */
0292
0293 #define ADV748X_SDP_VID_SEL     0x02    /* user_map_rw_reg_02 */
0294 #define ADV748X_SDP_VID_SEL_MASK    0xf0
0295 #define ADV748X_SDP_VID_SEL_SHIFT   4
0296
0297 /* Contrast - Unsigned*/
0298 #define ADV748X_SDP_CON         0x08    /* user_map_rw_reg_08 */
0299 #define ADV748X_SDP_CON_MIN     0
0300 #define ADV748X_SDP_CON_DEF     128
0301 #define ADV748X_SDP_CON_MAX     255
0302
0303 /* Brightness - Signed */
0304 #define ADV748X_SDP_BRI         0x0a    /* user_map_rw_reg_0a */
0305 #define ADV748X_SDP_BRI_MIN     -128
0306 #define ADV748X_SDP_BRI_DEF     0
0307 #define ADV748X_SDP_BRI_MAX     127
0308
0309 /* Hue - Signed, inverted*/
0310 #define ADV748X_SDP_HUE         0x0b    /* user_map_rw_reg_0b */
0311 #define ADV748X_SDP_HUE_MIN     -127
0312 #define ADV748X_SDP_HUE_DEF     0
0313 #define ADV748X_SDP_HUE_MAX     128
0314
0315 /* Test Patterns / Default Values */
0316 #define ADV748X_SDP_DEF         0x0c    /* user_map_rw_reg_0c */
0317 #define ADV748X_SDP_DEF_VAL_EN      BIT(0)  /* Force free run mode */
0318 #define ADV748X_SDP_DEF_VAL_AUTO_EN BIT(1)  /* Free run when no signal */
0319
0320 #define ADV748X_SDP_MAP_SEL     0x0e    /* user_map_rw_reg_0e */
0321 #define ADV748X_SDP_MAP_SEL_RO_MAIN 1
0322
0323 /* Free run pattern select */
0324 #define ADV748X_SDP_FRP         0x14
0325 #define ADV748X_SDP_FRP_MASK        GENMASK(3, 1)
0326
0327 /* Saturation */
0328 #define ADV748X_SDP_SD_SAT_U        0xe3    /* user_map_rw_reg_e3 */
0329 #define ADV748X_SDP_SD_SAT_V        0xe4    /* user_map_rw_reg_e4 */
0330 #define ADV748X_SDP_SAT_MIN     0
0331 #define ADV748X_SDP_SAT_DEF     128
0332 #define ADV748X_SDP_SAT_MAX     255
0333
0334 /* SDP RO Main Map */
0335 #define ADV748X_SDP_RO_10       0x10
0336 #define ADV748X_SDP_RO_10_IN_LOCK   BIT(0)
0337
0338 /* CP Map */
0339 #define ADV748X_CP_PAT_GEN      0x37    /* int_pat_gen_1 */
0340 #define ADV748X_CP_PAT_GEN_EN       BIT(7)
0341
0342 /* Contrast Control - Unsigned */
0343 #define ADV748X_CP_CON          0x3a    /* contrast_cntrl */
0344 #define ADV748X_CP_CON_MIN      0   /* Minimum contrast */
0345 #define ADV748X_CP_CON_DEF      128 /* Default */
0346 #define ADV748X_CP_CON_MAX      255 /* Maximum contrast */
0347
0348 /* Saturation Control - Unsigned */
0349 #define ADV748X_CP_SAT          0x3b    /* saturation_cntrl */
0350 #define ADV748X_CP_SAT_MIN      0   /* Minimum saturation */
0351 #define ADV748X_CP_SAT_DEF      128 /* Default */
0352 #define ADV748X_CP_SAT_MAX      255 /* Maximum saturation */
0353
0354 /* Brightness Control - Signed */
0355 #define ADV748X_CP_BRI          0x3c    /* brightness_cntrl */
0356 #define ADV748X_CP_BRI_MIN      -128    /* Luma is -512d */
0357 #define ADV748X_CP_BRI_DEF      0   /* Luma is 0 */
0358 #define ADV748X_CP_BRI_MAX      127 /* Luma is 508d */
0359
0360 /* Hue Control */
0361 #define ADV748X_CP_HUE          0x3d    /* hue_cntrl */
0362 #define ADV748X_CP_HUE_MIN      0   /* -90 degree */
0363 #define ADV748X_CP_HUE_DEF      0   /* -90 degree */
0364 #define ADV748X_CP_HUE_MAX      255 /* +90 degree */
0365
0366 #define ADV748X_CP_VID_ADJ      0x3e    /* vid_adj_0 */
0367 #define ADV748X_CP_VID_ADJ_ENABLE   BIT(7)  /* Enable colour controls */
0368
0369 #define ADV748X_CP_DE_POS_HIGH      0x8b    /* de_pos_adj_6 */
0370 #define ADV748X_CP_DE_POS_HIGH_SET  BIT(6)
0371 #define ADV748X_CP_DE_POS_END_LOW   0x8c    /* de_pos_adj_7 */
0372 #define ADV748X_CP_DE_POS_START_LOW 0x8d    /* de_pos_adj_8 */
0373
0374 #define ADV748X_CP_VID_ADJ_2            0x91
0375 #define ADV748X_CP_VID_ADJ_2_INTERLACED     BIT(6)
0376 #define ADV748X_CP_VID_ADJ_2_INTERLACED_3D  BIT(4)
0377
0378 #define ADV748X_CP_CLMP_POS     0xc9    /* clmp_pos_cntrl_4 */
0379 #define ADV748X_CP_CLMP_POS_DIS_AUTO    BIT(0)  /* dis_auto_param_buff */
0380
0381 /* CSI : TXA/TXB Maps */
0382 #define ADV748X_CSI_VC_REF      0x0d    /* csi_tx_top_reg_0d */
0383 #define ADV748X_CSI_VC_REF_SHIFT    6
0384
0385 #define ADV748X_CSI_FS_AS_LS        0x1e    /* csi_tx_top_reg_1e */
0386 #define ADV748X_CSI_FS_AS_LS_UNKNOWN    BIT(6)  /* Undocumented bit */
0387
0388 /* Register handling */
0389
0390 int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
0391 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
0392 int adv748x_write_block(struct adv748x_state *state, int client_page,
0393             unsigned int init_reg, const void *val,
0394             size_t val_len);
0395
0396 #define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
0397 #define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
0398 #define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v))
0399
0400 #define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
0401 #define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, (r)+1)) & (m))
0402 #define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
0403
0404 #define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
0405 #define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
0406
0407 #define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
0408 #define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
0409 #define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) | (v))
0410
0411 #define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
0412 #define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
0413 #define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v))
0414
0415 #define tx_read(t, r) adv748x_read(t->state, t->page, r)
0416 #define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
0417
0418 static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
0419 {
0420     pad = media_pad_remote_pad_first(pad);
0421     if (!pad)
0422         return NULL;
0423
0424     return media_entity_to_v4l2_subdev(pad->entity);
0425 }
0426
0427 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
0428              const struct v4l2_subdev_ops *ops, u32 function,
0429              const char *ident);
0430
0431 int adv748x_register_subdevs(struct adv748x_state *state,
0432                  struct v4l2_device *v4l2_dev);
0433
0434 int adv748x_tx_power(struct adv748x_csi2 *tx, bool on);
0435
0436 int adv748x_afe_init(struct adv748x_afe *afe);
0437 void adv748x_afe_cleanup(struct adv748x_afe *afe);
0438 int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input);
0439
0440 int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
0441 void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
0442 int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc);
0443 int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
0444
0445 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
0446 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
0447
0448 #endif /* _ADV748X_H_ */