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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for Analog Devices ADV748X HDMI receiver with AFE
0004  *
0005  * Copyright (C) 2017 Renesas Electronics Corp.
0006  *
0007  * Authors:
0008  *  Koji Matsuoka <koji.matsuoka.xm@renesas.com>
0009  *  Niklas Söderlund <niklas.soderlund@ragnatech.se>
0010  *  Kieran Bingham <kieran.bingham@ideasonboard.com>
0011  */
0012 
0013 #include <linux/delay.h>
0014 #include <linux/errno.h>
0015 #include <linux/i2c.h>
0016 #include <linux/module.h>
0017 #include <linux/mutex.h>
0018 #include <linux/of_graph.h>
0019 #include <linux/regmap.h>
0020 #include <linux/slab.h>
0021 #include <linux/v4l2-dv-timings.h>
0022 
0023 #include <media/v4l2-ctrls.h>
0024 #include <media/v4l2-device.h>
0025 #include <media/v4l2-dv-timings.h>
0026 #include <media/v4l2-fwnode.h>
0027 #include <media/v4l2-ioctl.h>
0028 
0029 #include "adv748x.h"
0030 
0031 /* -----------------------------------------------------------------------------
0032  * Register manipulation
0033  */
0034 
0035 #define ADV748X_REGMAP_CONF(n) \
0036 { \
0037     .name = n, \
0038     .reg_bits = 8, \
0039     .val_bits = 8, \
0040     .max_register = 0xff, \
0041     .cache_type = REGCACHE_NONE, \
0042 }
0043 
0044 static const struct regmap_config adv748x_regmap_cnf[] = {
0045     ADV748X_REGMAP_CONF("io"),
0046     ADV748X_REGMAP_CONF("dpll"),
0047     ADV748X_REGMAP_CONF("cp"),
0048     ADV748X_REGMAP_CONF("hdmi"),
0049     ADV748X_REGMAP_CONF("edid"),
0050     ADV748X_REGMAP_CONF("repeater"),
0051     ADV748X_REGMAP_CONF("infoframe"),
0052     ADV748X_REGMAP_CONF("cbus"),
0053     ADV748X_REGMAP_CONF("cec"),
0054     ADV748X_REGMAP_CONF("sdp"),
0055     ADV748X_REGMAP_CONF("txa"),
0056     ADV748X_REGMAP_CONF("txb"),
0057 };
0058 
0059 static int adv748x_configure_regmap(struct adv748x_state *state, int region)
0060 {
0061     int err;
0062 
0063     if (!state->i2c_clients[region])
0064         return -ENODEV;
0065 
0066     state->regmap[region] =
0067         devm_regmap_init_i2c(state->i2c_clients[region],
0068                      &adv748x_regmap_cnf[region]);
0069 
0070     if (IS_ERR(state->regmap[region])) {
0071         err = PTR_ERR(state->regmap[region]);
0072         adv_err(state,
0073             "Error initializing regmap %d with error %d\n",
0074             region, err);
0075         return -EINVAL;
0076     }
0077 
0078     return 0;
0079 }
0080 struct adv748x_register_map {
0081     const char *name;
0082     u8 default_addr;
0083 };
0084 
0085 static const struct adv748x_register_map adv748x_default_addresses[] = {
0086     [ADV748X_PAGE_IO] = { "main", 0x70 },
0087     [ADV748X_PAGE_DPLL] = { "dpll", 0x26 },
0088     [ADV748X_PAGE_CP] = { "cp", 0x22 },
0089     [ADV748X_PAGE_HDMI] = { "hdmi", 0x34 },
0090     [ADV748X_PAGE_EDID] = { "edid", 0x36 },
0091     [ADV748X_PAGE_REPEATER] = { "repeater", 0x32 },
0092     [ADV748X_PAGE_INFOFRAME] = { "infoframe", 0x31 },
0093     [ADV748X_PAGE_CBUS] = { "cbus", 0x30 },
0094     [ADV748X_PAGE_CEC] = { "cec", 0x41 },
0095     [ADV748X_PAGE_SDP] = { "sdp", 0x79 },
0096     [ADV748X_PAGE_TXB] = { "txb", 0x48 },
0097     [ADV748X_PAGE_TXA] = { "txa", 0x4a },
0098 };
0099 
0100 static int adv748x_read_check(struct adv748x_state *state,
0101                   int client_page, u8 reg)
0102 {
0103     struct i2c_client *client = state->i2c_clients[client_page];
0104     int err;
0105     unsigned int val;
0106 
0107     err = regmap_read(state->regmap[client_page], reg, &val);
0108 
0109     if (err) {
0110         adv_err(state, "error reading %02x, %02x\n",
0111                 client->addr, reg);
0112         return err;
0113     }
0114 
0115     return val;
0116 }
0117 
0118 int adv748x_read(struct adv748x_state *state, u8 page, u8 reg)
0119 {
0120     return adv748x_read_check(state, page, reg);
0121 }
0122 
0123 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value)
0124 {
0125     return regmap_write(state->regmap[page], reg, value);
0126 }
0127 
0128 static int adv748x_write_check(struct adv748x_state *state, u8 page, u8 reg,
0129                    u8 value, int *error)
0130 {
0131     if (*error)
0132         return *error;
0133 
0134     *error = adv748x_write(state, page, reg, value);
0135     return *error;
0136 }
0137 
0138 /* adv748x_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
0139  * size to one or more registers.
0140  *
0141  * A value of zero will be returned on success, a negative errno will
0142  * be returned in error cases.
0143  */
0144 int adv748x_write_block(struct adv748x_state *state, int client_page,
0145             unsigned int init_reg, const void *val,
0146             size_t val_len)
0147 {
0148     struct regmap *regmap = state->regmap[client_page];
0149 
0150     if (val_len > I2C_SMBUS_BLOCK_MAX)
0151         val_len = I2C_SMBUS_BLOCK_MAX;
0152 
0153     return regmap_raw_write(regmap, init_reg, val, val_len);
0154 }
0155 
0156 static int adv748x_set_slave_addresses(struct adv748x_state *state)
0157 {
0158     struct i2c_client *client;
0159     unsigned int i;
0160     u8 io_reg;
0161 
0162     for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
0163         io_reg = ADV748X_IO_SLAVE_ADDR_BASE + i;
0164         client = state->i2c_clients[i];
0165 
0166         io_write(state, io_reg, client->addr << 1);
0167     }
0168 
0169     return 0;
0170 }
0171 
0172 static void adv748x_unregister_clients(struct adv748x_state *state)
0173 {
0174     unsigned int i;
0175 
0176     for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i)
0177         i2c_unregister_device(state->i2c_clients[i]);
0178 }
0179 
0180 static int adv748x_initialise_clients(struct adv748x_state *state)
0181 {
0182     unsigned int i;
0183     int ret;
0184 
0185     for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
0186         state->i2c_clients[i] = i2c_new_ancillary_device(
0187                 state->client,
0188                 adv748x_default_addresses[i].name,
0189                 adv748x_default_addresses[i].default_addr);
0190 
0191         if (IS_ERR(state->i2c_clients[i])) {
0192             adv_err(state, "failed to create i2c client %u\n", i);
0193             return PTR_ERR(state->i2c_clients[i]);
0194         }
0195 
0196         ret = adv748x_configure_regmap(state, i);
0197         if (ret)
0198             return ret;
0199     }
0200 
0201     return 0;
0202 }
0203 
0204 /**
0205  * struct adv748x_reg_value - Register write instruction
0206  * @page:       Regmap page identifier
0207  * @reg:        I2C register
0208  * @value:      value to write to @page at @reg
0209  */
0210 struct adv748x_reg_value {
0211     u8 page;
0212     u8 reg;
0213     u8 value;
0214 };
0215 
0216 static int adv748x_write_regs(struct adv748x_state *state,
0217                   const struct adv748x_reg_value *regs)
0218 {
0219     int ret;
0220 
0221     for (; regs->page != ADV748X_PAGE_EOR; regs++) {
0222         ret = adv748x_write(state, regs->page, regs->reg, regs->value);
0223         if (ret < 0) {
0224             adv_err(state, "Error regs page: 0x%02x reg: 0x%02x\n",
0225                 regs->page, regs->reg);
0226             return ret;
0227         }
0228     }
0229 
0230     return 0;
0231 }
0232 
0233 /* -----------------------------------------------------------------------------
0234  * TXA and TXB
0235  */
0236 
0237 static int adv748x_power_up_tx(struct adv748x_csi2 *tx)
0238 {
0239     struct adv748x_state *state = tx->state;
0240     u8 page = is_txa(tx) ? ADV748X_PAGE_TXA : ADV748X_PAGE_TXB;
0241     int ret = 0;
0242 
0243     /* Enable n-lane MIPI */
0244     adv748x_write_check(state, page, 0x00, 0x80 | tx->active_lanes, &ret);
0245 
0246     /* Set Auto DPHY Timing */
0247     adv748x_write_check(state, page, 0x00, 0xa0 | tx->active_lanes, &ret);
0248 
0249     /* ADI Required Write */
0250     if (tx->src == &state->hdmi.sd) {
0251         adv748x_write_check(state, page, 0xdb, 0x10, &ret);
0252         adv748x_write_check(state, page, 0xd6, 0x07, &ret);
0253     } else {
0254         adv748x_write_check(state, page, 0xd2, 0x40, &ret);
0255     }
0256 
0257     adv748x_write_check(state, page, 0xc4, 0x0a, &ret);
0258     adv748x_write_check(state, page, 0x71, 0x33, &ret);
0259     adv748x_write_check(state, page, 0x72, 0x11, &ret);
0260 
0261     /* i2c_dphy_pwdn - 1'b0 */
0262     adv748x_write_check(state, page, 0xf0, 0x00, &ret);
0263 
0264     /* ADI Required Writes*/
0265     adv748x_write_check(state, page, 0x31, 0x82, &ret);
0266     adv748x_write_check(state, page, 0x1e, 0x40, &ret);
0267 
0268     /* i2c_mipi_pll_en - 1'b1 */
0269     adv748x_write_check(state, page, 0xda, 0x01, &ret);
0270     usleep_range(2000, 2500);
0271 
0272     /* Power-up CSI-TX */
0273     adv748x_write_check(state, page, 0x00, 0x20 | tx->active_lanes, &ret);
0274     usleep_range(1000, 1500);
0275 
0276     /* ADI Required Writes */
0277     adv748x_write_check(state, page, 0xc1, 0x2b, &ret);
0278     usleep_range(1000, 1500);
0279     adv748x_write_check(state, page, 0x31, 0x80, &ret);
0280 
0281     return ret;
0282 }
0283 
0284 static int adv748x_power_down_tx(struct adv748x_csi2 *tx)
0285 {
0286     struct adv748x_state *state = tx->state;
0287     u8 page = is_txa(tx) ? ADV748X_PAGE_TXA : ADV748X_PAGE_TXB;
0288     int ret = 0;
0289 
0290     /* ADI Required Writes */
0291     adv748x_write_check(state, page, 0x31, 0x82, &ret);
0292     adv748x_write_check(state, page, 0x1e, 0x00, &ret);
0293 
0294     /* Enable n-lane MIPI */
0295     adv748x_write_check(state, page, 0x00, 0x80 | tx->active_lanes, &ret);
0296 
0297     /* i2c_mipi_pll_en - 1'b1 */
0298     adv748x_write_check(state, page, 0xda, 0x01, &ret);
0299 
0300     /* ADI Required Write */
0301     adv748x_write_check(state, page, 0xc1, 0x3b, &ret);
0302 
0303     return ret;
0304 }
0305 
0306 int adv748x_tx_power(struct adv748x_csi2 *tx, bool on)
0307 {
0308     int val;
0309 
0310     if (!is_tx_enabled(tx))
0311         return 0;
0312 
0313     val = tx_read(tx, ADV748X_CSI_FS_AS_LS);
0314     if (val < 0)
0315         return val;
0316 
0317     /*
0318      * This test against BIT(6) is not documented by the datasheet, but was
0319      * specified in the downstream driver.
0320      * Track with a WARN_ONCE to determine if it is ever set by HW.
0321      */
0322     WARN_ONCE((on && val & ADV748X_CSI_FS_AS_LS_UNKNOWN),
0323             "Enabling with unknown bit set");
0324 
0325     return on ? adv748x_power_up_tx(tx) : adv748x_power_down_tx(tx);
0326 }
0327 
0328 /* -----------------------------------------------------------------------------
0329  * Media Operations
0330  */
0331 static int adv748x_link_setup(struct media_entity *entity,
0332                   const struct media_pad *local,
0333                   const struct media_pad *remote, u32 flags)
0334 {
0335     struct v4l2_subdev *rsd = media_entity_to_v4l2_subdev(remote->entity);
0336     struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
0337     struct adv748x_state *state = v4l2_get_subdevdata(sd);
0338     struct adv748x_csi2 *tx = adv748x_sd_to_csi2(sd);
0339     bool enable = flags & MEDIA_LNK_FL_ENABLED;
0340     u8 io10_mask = ADV748X_IO_10_CSI1_EN |
0341                ADV748X_IO_10_CSI4_EN |
0342                ADV748X_IO_10_CSI4_IN_SEL_AFE;
0343     u8 io10 = 0;
0344 
0345     /* Refuse to enable multiple links to the same TX at the same time. */
0346     if (enable && tx->src)
0347         return -EINVAL;
0348 
0349     /* Set or clear the source (HDMI or AFE) and the current TX. */
0350     if (rsd == &state->afe.sd)
0351         state->afe.tx = enable ? tx : NULL;
0352     else
0353         state->hdmi.tx = enable ? tx : NULL;
0354 
0355     tx->src = enable ? rsd : NULL;
0356 
0357     if (state->afe.tx) {
0358         /* AFE Requires TXA enabled, even when output to TXB */
0359         io10 |= ADV748X_IO_10_CSI4_EN;
0360         if (is_txa(tx)) {
0361             /*
0362              * Output from the SD-core (480i and 576i) from the TXA
0363              * interface requires reducing the number of enabled
0364              * data lanes in order to guarantee a valid link
0365              * frequency.
0366              */
0367             tx->active_lanes = min(tx->num_lanes, 2U);
0368             io10 |= ADV748X_IO_10_CSI4_IN_SEL_AFE;
0369         } else {
0370             /* TXB has a single data lane, no need to adjust. */
0371             io10 |= ADV748X_IO_10_CSI1_EN;
0372         }
0373     }
0374 
0375     if (state->hdmi.tx) {
0376         /*
0377          * Restore the number of active lanes, in case we have gone
0378          * through an AFE->TXA streaming sessions.
0379          */
0380         tx->active_lanes = tx->num_lanes;
0381         io10 |= ADV748X_IO_10_CSI4_EN;
0382     }
0383 
0384     return io_clrset(state, ADV748X_IO_10, io10_mask, io10);
0385 }
0386 
0387 static const struct media_entity_operations adv748x_tx_media_ops = {
0388     .link_setup = adv748x_link_setup,
0389     .link_validate  = v4l2_subdev_link_validate,
0390 };
0391 
0392 static const struct media_entity_operations adv748x_media_ops = {
0393     .link_validate = v4l2_subdev_link_validate,
0394 };
0395 
0396 /* -----------------------------------------------------------------------------
0397  * HW setup
0398  */
0399 
0400 /* Initialize CP Core with RGB888 format. */
0401 static const struct adv748x_reg_value adv748x_init_hdmi[] = {
0402     /* Disable chip powerdown & Enable HDMI Rx block */
0403     {ADV748X_PAGE_IO, 0x00, 0x40},
0404 
0405     {ADV748X_PAGE_REPEATER, 0x40, 0x83}, /* Enable HDCP 1.1 */
0406 
0407     {ADV748X_PAGE_HDMI, 0x00, 0x08},/* Foreground Channel = A */
0408     {ADV748X_PAGE_HDMI, 0x98, 0xff},/* ADI Required Write */
0409     {ADV748X_PAGE_HDMI, 0x99, 0xa3},/* ADI Required Write */
0410     {ADV748X_PAGE_HDMI, 0x9a, 0x00},/* ADI Required Write */
0411     {ADV748X_PAGE_HDMI, 0x9b, 0x0a},/* ADI Required Write */
0412     {ADV748X_PAGE_HDMI, 0x9d, 0x40},/* ADI Required Write */
0413     {ADV748X_PAGE_HDMI, 0xcb, 0x09},/* ADI Required Write */
0414     {ADV748X_PAGE_HDMI, 0x3d, 0x10},/* ADI Required Write */
0415     {ADV748X_PAGE_HDMI, 0x3e, 0x7b},/* ADI Required Write */
0416     {ADV748X_PAGE_HDMI, 0x3f, 0x5e},/* ADI Required Write */
0417     {ADV748X_PAGE_HDMI, 0x4e, 0xfe},/* ADI Required Write */
0418     {ADV748X_PAGE_HDMI, 0x4f, 0x18},/* ADI Required Write */
0419     {ADV748X_PAGE_HDMI, 0x57, 0xa3},/* ADI Required Write */
0420     {ADV748X_PAGE_HDMI, 0x58, 0x04},/* ADI Required Write */
0421     {ADV748X_PAGE_HDMI, 0x85, 0x10},/* ADI Required Write */
0422 
0423     {ADV748X_PAGE_HDMI, 0x83, 0x00},/* Enable All Terminations */
0424     {ADV748X_PAGE_HDMI, 0xa3, 0x01},/* ADI Required Write */
0425     {ADV748X_PAGE_HDMI, 0xbe, 0x00},/* ADI Required Write */
0426 
0427     {ADV748X_PAGE_HDMI, 0x6c, 0x01},/* HPA Manual Enable */
0428     {ADV748X_PAGE_HDMI, 0xf8, 0x01},/* HPA Asserted */
0429     {ADV748X_PAGE_HDMI, 0x0f, 0x00},/* Audio Mute Speed Set to Fastest */
0430     /* (Smallest Step Size) */
0431 
0432     {ADV748X_PAGE_IO, 0x04, 0x02},  /* RGB Out of CP */
0433     {ADV748X_PAGE_IO, 0x12, 0xf0},  /* CSC Depends on ip Packets, SDR 444 */
0434     {ADV748X_PAGE_IO, 0x17, 0x80},  /* Luma & Chroma can reach 254d */
0435     {ADV748X_PAGE_IO, 0x03, 0x86},  /* CP-Insert_AV_Code */
0436 
0437     {ADV748X_PAGE_CP, 0x7c, 0x00},  /* ADI Required Write */
0438 
0439     {ADV748X_PAGE_IO, 0x0c, 0xe0},  /* Enable LLC_DLL & Double LLC Timing */
0440     {ADV748X_PAGE_IO, 0x0e, 0xdd},  /* LLC/PIX/SPI PINS TRISTATED AUD */
0441 
0442     {ADV748X_PAGE_EOR, 0xff, 0xff}  /* End of register table */
0443 };
0444 
0445 /* Initialize AFE core with YUV8 format. */
0446 static const struct adv748x_reg_value adv748x_init_afe[] = {
0447     {ADV748X_PAGE_IO, 0x00, 0x30},  /* Disable chip powerdown Rx */
0448     {ADV748X_PAGE_IO, 0xf2, 0x01},  /* Enable I2C Read Auto-Increment */
0449 
0450     {ADV748X_PAGE_IO, 0x0e, 0xff},  /* LLC/PIX/AUD/SPI PINS TRISTATED */
0451 
0452     {ADV748X_PAGE_SDP, 0x0f, 0x00}, /* Exit Power Down Mode */
0453     {ADV748X_PAGE_SDP, 0x52, 0xcd}, /* ADI Required Write */
0454 
0455     {ADV748X_PAGE_SDP, 0x0e, 0x80}, /* ADI Required Write */
0456     {ADV748X_PAGE_SDP, 0x9c, 0x00}, /* ADI Required Write */
0457     {ADV748X_PAGE_SDP, 0x9c, 0xff}, /* ADI Required Write */
0458     {ADV748X_PAGE_SDP, 0x0e, 0x00}, /* ADI Required Write */
0459 
0460     /* ADI recommended writes for improved video quality */
0461     {ADV748X_PAGE_SDP, 0x80, 0x51}, /* ADI Required Write */
0462     {ADV748X_PAGE_SDP, 0x81, 0x51}, /* ADI Required Write */
0463     {ADV748X_PAGE_SDP, 0x82, 0x68}, /* ADI Required Write */
0464 
0465     {ADV748X_PAGE_SDP, 0x03, 0x42}, /* Tri-S Output , PwrDwn 656 pads */
0466     {ADV748X_PAGE_SDP, 0x04, 0xb5}, /* ITU-R BT.656-4 compatible */
0467     {ADV748X_PAGE_SDP, 0x13, 0x00}, /* ADI Required Write */
0468 
0469     {ADV748X_PAGE_SDP, 0x17, 0x41}, /* Select SH1 */
0470     {ADV748X_PAGE_SDP, 0x31, 0x12}, /* ADI Required Write */
0471     {ADV748X_PAGE_SDP, 0xe6, 0x4f},  /* V bit end pos manually in NTSC */
0472 
0473     {ADV748X_PAGE_EOR, 0xff, 0xff}  /* End of register table */
0474 };
0475 
0476 static int adv748x_sw_reset(struct adv748x_state *state)
0477 {
0478     int ret;
0479 
0480     ret = io_write(state, ADV748X_IO_REG_FF, ADV748X_IO_REG_FF_MAIN_RESET);
0481     if (ret)
0482         return ret;
0483 
0484     usleep_range(5000, 6000);
0485 
0486     /* Disable CEC Wakeup from power-down mode */
0487     ret = io_clrset(state, ADV748X_IO_REG_01, ADV748X_IO_REG_01_PWRDN_MASK,
0488             ADV748X_IO_REG_01_PWRDNB);
0489     if (ret)
0490         return ret;
0491 
0492     /* Enable I2C Read Auto-Increment for consecutive reads */
0493     return io_write(state, ADV748X_IO_REG_F2,
0494             ADV748X_IO_REG_F2_READ_AUTO_INC);
0495 }
0496 
0497 static int adv748x_reset(struct adv748x_state *state)
0498 {
0499     int ret;
0500     u8 regval = 0;
0501 
0502     ret = adv748x_sw_reset(state);
0503     if (ret < 0)
0504         return ret;
0505 
0506     ret = adv748x_set_slave_addresses(state);
0507     if (ret < 0)
0508         return ret;
0509 
0510     /* Initialize CP and AFE cores. */
0511     ret = adv748x_write_regs(state, adv748x_init_hdmi);
0512     if (ret)
0513         return ret;
0514 
0515     ret = adv748x_write_regs(state, adv748x_init_afe);
0516     if (ret)
0517         return ret;
0518 
0519     adv748x_afe_s_input(&state->afe, state->afe.input);
0520 
0521     adv_dbg(state, "AFE Default input set to %d\n", state->afe.input);
0522 
0523     /* Reset TXA and TXB */
0524     adv748x_tx_power(&state->txa, 1);
0525     adv748x_tx_power(&state->txa, 0);
0526     adv748x_tx_power(&state->txb, 1);
0527     adv748x_tx_power(&state->txb, 0);
0528 
0529     /* Disable chip powerdown & Enable HDMI Rx block */
0530     io_write(state, ADV748X_IO_PD, ADV748X_IO_PD_RX_EN);
0531 
0532     /* Conditionally enable TXa and TXb. */
0533     if (is_tx_enabled(&state->txa)) {
0534         regval |= ADV748X_IO_10_CSI4_EN;
0535         adv748x_csi2_set_virtual_channel(&state->txa, 0);
0536     }
0537     if (is_tx_enabled(&state->txb)) {
0538         regval |= ADV748X_IO_10_CSI1_EN;
0539         adv748x_csi2_set_virtual_channel(&state->txb, 0);
0540     }
0541     io_write(state, ADV748X_IO_10, regval);
0542 
0543     /* Use vid_std and v_freq as freerun resolution for CP */
0544     cp_clrset(state, ADV748X_CP_CLMP_POS, ADV748X_CP_CLMP_POS_DIS_AUTO,
0545                           ADV748X_CP_CLMP_POS_DIS_AUTO);
0546 
0547     return 0;
0548 }
0549 
0550 static int adv748x_identify_chip(struct adv748x_state *state)
0551 {
0552     int msb, lsb;
0553 
0554     lsb = io_read(state, ADV748X_IO_CHIP_REV_ID_1);
0555     msb = io_read(state, ADV748X_IO_CHIP_REV_ID_2);
0556 
0557     if (lsb < 0 || msb < 0) {
0558         adv_err(state, "Failed to read chip revision\n");
0559         return -EIO;
0560     }
0561 
0562     adv_info(state, "chip found @ 0x%02x revision %02x%02x\n",
0563          state->client->addr << 1, lsb, msb);
0564 
0565     return 0;
0566 }
0567 
0568 /* -----------------------------------------------------------------------------
0569  * Suspend / Resume
0570  */
0571 
0572 static int __maybe_unused adv748x_resume_early(struct device *dev)
0573 {
0574     struct i2c_client *client = to_i2c_client(dev);
0575     struct adv748x_state *state = i2c_get_clientdata(client);
0576 
0577     return adv748x_reset(state);
0578 }
0579 
0580 /* -----------------------------------------------------------------------------
0581  * i2c driver
0582  */
0583 
0584 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
0585              const struct v4l2_subdev_ops *ops, u32 function,
0586              const char *ident)
0587 {
0588     v4l2_subdev_init(sd, ops);
0589     sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
0590 
0591     /* the owner is the same as the i2c_client's driver owner */
0592     sd->owner = state->dev->driver->owner;
0593     sd->dev = state->dev;
0594 
0595     v4l2_set_subdevdata(sd, state);
0596 
0597     /* initialize name */
0598     snprintf(sd->name, sizeof(sd->name), "%s %d-%04x %s",
0599         state->dev->driver->name,
0600         i2c_adapter_id(state->client->adapter),
0601         state->client->addr, ident);
0602 
0603     sd->entity.function = function;
0604     sd->entity.ops = is_tx(adv748x_sd_to_csi2(sd)) ?
0605              &adv748x_tx_media_ops : &adv748x_media_ops;
0606 }
0607 
0608 static int adv748x_parse_csi2_lanes(struct adv748x_state *state,
0609                     unsigned int port,
0610                     struct device_node *ep)
0611 {
0612     struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
0613     unsigned int num_lanes;
0614     int ret;
0615 
0616     if (port != ADV748X_PORT_TXA && port != ADV748X_PORT_TXB)
0617         return 0;
0618 
0619     ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &vep);
0620     if (ret)
0621         return ret;
0622 
0623     num_lanes = vep.bus.mipi_csi2.num_data_lanes;
0624 
0625     if (vep.base.port == ADV748X_PORT_TXA) {
0626         if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) {
0627             adv_err(state, "TXA: Invalid number (%u) of lanes\n",
0628                 num_lanes);
0629             return -EINVAL;
0630         }
0631 
0632         state->txa.num_lanes = num_lanes;
0633         state->txa.active_lanes = num_lanes;
0634         adv_dbg(state, "TXA: using %u lanes\n", state->txa.num_lanes);
0635     }
0636 
0637     if (vep.base.port == ADV748X_PORT_TXB) {
0638         if (num_lanes != 1) {
0639             adv_err(state, "TXB: Invalid number (%u) of lanes\n",
0640                 num_lanes);
0641             return -EINVAL;
0642         }
0643 
0644         state->txb.num_lanes = num_lanes;
0645         state->txb.active_lanes = num_lanes;
0646         adv_dbg(state, "TXB: using %u lanes\n", state->txb.num_lanes);
0647     }
0648 
0649     return 0;
0650 }
0651 
0652 static int adv748x_parse_dt(struct adv748x_state *state)
0653 {
0654     struct device_node *ep_np = NULL;
0655     struct of_endpoint ep;
0656     bool out_found = false;
0657     bool in_found = false;
0658     int ret;
0659 
0660     for_each_endpoint_of_node(state->dev->of_node, ep_np) {
0661         of_graph_parse_endpoint(ep_np, &ep);
0662         adv_info(state, "Endpoint %pOF on port %d", ep.local_node,
0663              ep.port);
0664 
0665         if (ep.port >= ADV748X_PORT_MAX) {
0666             adv_err(state, "Invalid endpoint %pOF on port %d",
0667                 ep.local_node, ep.port);
0668 
0669             continue;
0670         }
0671 
0672         if (state->endpoints[ep.port]) {
0673             adv_err(state,
0674                 "Multiple port endpoints are not supported");
0675             continue;
0676         }
0677 
0678         of_node_get(ep_np);
0679         state->endpoints[ep.port] = ep_np;
0680 
0681         /*
0682          * At least one input endpoint and one output endpoint shall
0683          * be defined.
0684          */
0685         if (ep.port < ADV748X_PORT_TXA)
0686             in_found = true;
0687         else
0688             out_found = true;
0689 
0690         /* Store number of CSI-2 lanes used for TXA and TXB. */
0691         ret = adv748x_parse_csi2_lanes(state, ep.port, ep_np);
0692         if (ret)
0693             return ret;
0694     }
0695 
0696     return in_found && out_found ? 0 : -ENODEV;
0697 }
0698 
0699 static void adv748x_dt_cleanup(struct adv748x_state *state)
0700 {
0701     unsigned int i;
0702 
0703     for (i = 0; i < ADV748X_PORT_MAX; i++)
0704         of_node_put(state->endpoints[i]);
0705 }
0706 
0707 static int adv748x_probe(struct i2c_client *client)
0708 {
0709     struct adv748x_state *state;
0710     int ret;
0711 
0712     /* Check if the adapter supports the needed features */
0713     if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
0714         return -EIO;
0715 
0716     state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
0717     if (!state)
0718         return -ENOMEM;
0719 
0720     mutex_init(&state->mutex);
0721 
0722     state->dev = &client->dev;
0723     state->client = client;
0724     state->i2c_clients[ADV748X_PAGE_IO] = client;
0725     i2c_set_clientdata(client, state);
0726 
0727     /*
0728      * We can not use container_of to get back to the state with two TXs;
0729      * Initialize the TXs's fields unconditionally on the endpoint
0730      * presence to access them later.
0731      */
0732     state->txa.state = state->txb.state = state;
0733     state->txa.page = ADV748X_PAGE_TXA;
0734     state->txb.page = ADV748X_PAGE_TXB;
0735     state->txa.port = ADV748X_PORT_TXA;
0736     state->txb.port = ADV748X_PORT_TXB;
0737 
0738     /* Discover and process ports declared by the Device tree endpoints */
0739     ret = adv748x_parse_dt(state);
0740     if (ret) {
0741         adv_err(state, "Failed to parse device tree");
0742         goto err_free_mutex;
0743     }
0744 
0745     /* Configure IO Regmap region */
0746     ret = adv748x_configure_regmap(state, ADV748X_PAGE_IO);
0747     if (ret) {
0748         adv_err(state, "Error configuring IO regmap region");
0749         goto err_cleanup_dt;
0750     }
0751 
0752     ret = adv748x_identify_chip(state);
0753     if (ret) {
0754         adv_err(state, "Failed to identify chip");
0755         goto err_cleanup_dt;
0756     }
0757 
0758     /* Configure remaining pages as I2C clients with regmap access */
0759     ret = adv748x_initialise_clients(state);
0760     if (ret) {
0761         adv_err(state, "Failed to setup client regmap pages");
0762         goto err_cleanup_clients;
0763     }
0764 
0765     /* SW reset ADV748X to its default values */
0766     ret = adv748x_reset(state);
0767     if (ret) {
0768         adv_err(state, "Failed to reset hardware");
0769         goto err_cleanup_clients;
0770     }
0771 
0772     /* Initialise HDMI */
0773     ret = adv748x_hdmi_init(&state->hdmi);
0774     if (ret) {
0775         adv_err(state, "Failed to probe HDMI");
0776         goto err_cleanup_clients;
0777     }
0778 
0779     /* Initialise AFE */
0780     ret = adv748x_afe_init(&state->afe);
0781     if (ret) {
0782         adv_err(state, "Failed to probe AFE");
0783         goto err_cleanup_hdmi;
0784     }
0785 
0786     /* Initialise TXA */
0787     ret = adv748x_csi2_init(state, &state->txa);
0788     if (ret) {
0789         adv_err(state, "Failed to probe TXA");
0790         goto err_cleanup_afe;
0791     }
0792 
0793     /* Initialise TXB */
0794     ret = adv748x_csi2_init(state, &state->txb);
0795     if (ret) {
0796         adv_err(state, "Failed to probe TXB");
0797         goto err_cleanup_txa;
0798     }
0799 
0800     return 0;
0801 
0802 err_cleanup_txa:
0803     adv748x_csi2_cleanup(&state->txa);
0804 err_cleanup_afe:
0805     adv748x_afe_cleanup(&state->afe);
0806 err_cleanup_hdmi:
0807     adv748x_hdmi_cleanup(&state->hdmi);
0808 err_cleanup_clients:
0809     adv748x_unregister_clients(state);
0810 err_cleanup_dt:
0811     adv748x_dt_cleanup(state);
0812 err_free_mutex:
0813     mutex_destroy(&state->mutex);
0814 
0815     return ret;
0816 }
0817 
0818 static int adv748x_remove(struct i2c_client *client)
0819 {
0820     struct adv748x_state *state = i2c_get_clientdata(client);
0821 
0822     adv748x_afe_cleanup(&state->afe);
0823     adv748x_hdmi_cleanup(&state->hdmi);
0824 
0825     adv748x_csi2_cleanup(&state->txa);
0826     adv748x_csi2_cleanup(&state->txb);
0827 
0828     adv748x_unregister_clients(state);
0829     adv748x_dt_cleanup(state);
0830     mutex_destroy(&state->mutex);
0831 
0832     return 0;
0833 }
0834 
0835 static const struct of_device_id adv748x_of_table[] = {
0836     { .compatible = "adi,adv7481", },
0837     { .compatible = "adi,adv7482", },
0838     { }
0839 };
0840 MODULE_DEVICE_TABLE(of, adv748x_of_table);
0841 
0842 static const struct dev_pm_ops adv748x_pm_ops = {
0843     SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, adv748x_resume_early)
0844 };
0845 
0846 static struct i2c_driver adv748x_driver = {
0847     .driver = {
0848         .name = "adv748x",
0849         .of_match_table = adv748x_of_table,
0850         .pm = &adv748x_pm_ops,
0851     },
0852     .probe_new = adv748x_probe,
0853     .remove = adv748x_remove,
0854 };
0855 
0856 module_i2c_driver(adv748x_driver);
0857 
0858 MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>");
0859 MODULE_DESCRIPTION("ADV748X video decoder");
0860 MODULE_LICENSE("GPL");
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