media/i2c/adv7393_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ADV7393 encoder related structure and register definitions
0004  *
0005  * Copyright (C) 2010-2012 ADVANSEE - http://www.advansee.com/
0006  * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
0007  *
0008  * Based on ADV7343 driver,
0009  *
0010  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
0011  */
0012
0013 #ifndef ADV7393_REGS_H
0014 #define ADV7393_REGS_H
0015
0016 struct adv7393_std_info {
0017     u32 standard_val3;
0018     u32 fsc_val;
0019     v4l2_std_id stdid;
0020 };
0021
0022 /* Register offset macros */
0023 #define ADV7393_POWER_MODE_REG      (0x00)
0024 #define ADV7393_MODE_SELECT_REG     (0x01)
0025 #define ADV7393_MODE_REG0       (0x02)
0026
0027 #define ADV7393_DAC123_OUTPUT_LEVEL (0x0B)
0028
0029 #define ADV7393_SOFT_RESET      (0x17)
0030
0031 #define ADV7393_HD_MODE_REG1        (0x30)
0032 #define ADV7393_HD_MODE_REG2        (0x31)
0033 #define ADV7393_HD_MODE_REG3        (0x32)
0034 #define ADV7393_HD_MODE_REG4        (0x33)
0035 #define ADV7393_HD_MODE_REG5        (0x34)
0036 #define ADV7393_HD_MODE_REG6        (0x35)
0037
0038 #define ADV7393_HD_MODE_REG7        (0x39)
0039
0040 #define ADV7393_SD_MODE_REG1        (0x80)
0041 #define ADV7393_SD_MODE_REG2        (0x82)
0042 #define ADV7393_SD_MODE_REG3        (0x83)
0043 #define ADV7393_SD_MODE_REG4        (0x84)
0044 #define ADV7393_SD_MODE_REG5        (0x86)
0045 #define ADV7393_SD_MODE_REG6        (0x87)
0046 #define ADV7393_SD_MODE_REG7        (0x88)
0047 #define ADV7393_SD_MODE_REG8        (0x89)
0048
0049 #define ADV7393_SD_TIMING_REG0      (0x8A)
0050
0051 #define ADV7393_FSC_REG0        (0x8C)
0052 #define ADV7393_FSC_REG1        (0x8D)
0053 #define ADV7393_FSC_REG2        (0x8E)
0054 #define ADV7393_FSC_REG3        (0x8F)
0055
0056 #define ADV7393_SD_CGMS_WSS0        (0x99)
0057
0058 #define ADV7393_SD_HUE_ADJUST       (0xA0)
0059 #define ADV7393_SD_BRIGHTNESS_WSS   (0xA1)
0060
0061 /* Default values for the registers */
0062 #define ADV7393_POWER_MODE_REG_DEFAULT      (0x10)
0063 #define ADV7393_HD_MODE_REG1_DEFAULT        (0x3C)  /* Changed Default
0064                                720p EAV/SAV code*/
0065 #define ADV7393_HD_MODE_REG2_DEFAULT        (0x01)  /* Changed Pixel data
0066                                valid */
0067 #define ADV7393_HD_MODE_REG3_DEFAULT        (0x00)  /* Color delay 0 clks */
0068 #define ADV7393_HD_MODE_REG4_DEFAULT        (0xEC)  /* Changed */
0069 #define ADV7393_HD_MODE_REG5_DEFAULT        (0x08)
0070 #define ADV7393_HD_MODE_REG6_DEFAULT        (0x00)
0071 #define ADV7393_HD_MODE_REG7_DEFAULT        (0x00)
0072 #define ADV7393_SOFT_RESET_DEFAULT      (0x02)
0073 #define ADV7393_COMPOSITE_POWER_VALUE       (0x10)
0074 #define ADV7393_COMPONENT_POWER_VALUE       (0x1C)
0075 #define ADV7393_SVIDEO_POWER_VALUE      (0x0C)
0076 #define ADV7393_SD_HUE_ADJUST_DEFAULT       (0x80)
0077 #define ADV7393_SD_BRIGHTNESS_WSS_DEFAULT   (0x00)
0078
0079 #define ADV7393_SD_CGMS_WSS0_DEFAULT        (0x10)
0080
0081 #define ADV7393_SD_MODE_REG1_DEFAULT        (0x10)
0082 #define ADV7393_SD_MODE_REG2_DEFAULT        (0xC9)
0083 #define ADV7393_SD_MODE_REG3_DEFAULT        (0x00)
0084 #define ADV7393_SD_MODE_REG4_DEFAULT        (0x00)
0085 #define ADV7393_SD_MODE_REG5_DEFAULT        (0x02)
0086 #define ADV7393_SD_MODE_REG6_DEFAULT        (0x8C)
0087 #define ADV7393_SD_MODE_REG7_DEFAULT        (0x14)
0088 #define ADV7393_SD_MODE_REG8_DEFAULT        (0x00)
0089
0090 #define ADV7393_SD_TIMING_REG0_DEFAULT      (0x0C)
0091
0092 /* Bit masks for Mode Select Register */
0093 #define INPUT_MODE_MASK         (0x70)
0094 #define SD_INPUT_MODE           (0x00)
0095 #define HD_720P_INPUT_MODE      (0x10)
0096 #define HD_1080I_INPUT_MODE     (0x10)
0097
0098 /* Bit masks for Mode Register 0 */
0099 #define TEST_PATTERN_BLACK_BAR_EN   (0x04)
0100 #define YUV_OUTPUT_SELECT       (0x20)
0101 #define RGB_OUTPUT_SELECT       (0xDF)
0102
0103 /* Bit masks for SD brightness/WSS */
0104 #define SD_BRIGHTNESS_VALUE_MASK    (0x7F)
0105 #define SD_BLANK_WSS_DATA_MASK      (0x80)
0106
0107 /* Bit masks for soft reset register */
0108 #define SOFT_RESET          (0x02)
0109
0110 /* Bit masks for HD Mode Register 1 */
0111 #define OUTPUT_STD_MASK     (0x03)
0112 #define OUTPUT_STD_SHIFT    (0)
0113 #define OUTPUT_STD_EIA0_2   (0x00)
0114 #define OUTPUT_STD_EIA0_1   (0x01)
0115 #define OUTPUT_STD_FULL     (0x02)
0116 #define EMBEDDED_SYNC       (0x04)
0117 #define EXTERNAL_SYNC       (0xFB)
0118 #define STD_MODE_MASK       (0x1F)
0119 #define STD_MODE_SHIFT      (3)
0120 #define STD_MODE_720P       (0x05)
0121 #define STD_MODE_720P_25    (0x08)
0122 #define STD_MODE_720P_30    (0x07)
0123 #define STD_MODE_720P_50    (0x06)
0124 #define STD_MODE_1080I      (0x0D)
0125 #define STD_MODE_1080I_25   (0x0E)
0126 #define STD_MODE_1080P_24   (0x11)
0127 #define STD_MODE_1080P_25   (0x10)
0128 #define STD_MODE_1080P_30   (0x0F)
0129 #define STD_MODE_525P       (0x00)
0130 #define STD_MODE_625P       (0x03)
0131
0132 /* Bit masks for SD Mode Register 1 */
0133 #define SD_STD_MASK     (0x03)
0134 #define SD_STD_NTSC     (0x00)
0135 #define SD_STD_PAL_BDGHI    (0x01)
0136 #define SD_STD_PAL_M        (0x02)
0137 #define SD_STD_PAL_N        (0x03)
0138 #define SD_LUMA_FLTR_MASK   (0x07)
0139 #define SD_LUMA_FLTR_SHIFT  (2)
0140 #define SD_CHROMA_FLTR_MASK (0x07)
0141 #define SD_CHROMA_FLTR_SHIFT    (5)
0142
0143 /* Bit masks for SD Mode Register 2 */
0144 #define SD_PRPB_SSAF_EN     (0x01)
0145 #define SD_PRPB_SSAF_DI     (0xFE)
0146 #define SD_DAC_OUT1_EN      (0x02)
0147 #define SD_DAC_OUT1_DI      (0xFD)
0148 #define SD_PEDESTAL_EN      (0x08)
0149 #define SD_PEDESTAL_DI      (0xF7)
0150 #define SD_SQUARE_PIXEL_EN  (0x10)
0151 #define SD_SQUARE_PIXEL_DI  (0xEF)
0152 #define SD_PIXEL_DATA_VALID (0x40)
0153 #define SD_ACTIVE_EDGE_EN   (0x80)
0154 #define SD_ACTIVE_EDGE_DI   (0x7F)
0155
0156 /* Bit masks for HD Mode Register 6 */
0157 #define HD_PRPB_SYNC_EN     (0x04)
0158 #define HD_PRPB_SYNC_DI     (0xFB)
0159 #define HD_DAC_SWAP_EN      (0x08)
0160 #define HD_DAC_SWAP_DI      (0xF7)
0161 #define HD_GAMMA_CURVE_A    (0xEF)
0162 #define HD_GAMMA_CURVE_B    (0x10)
0163 #define HD_GAMMA_EN     (0x20)
0164 #define HD_GAMMA_DI     (0xDF)
0165 #define HD_ADPT_FLTR_MODEA  (0xBF)
0166 #define HD_ADPT_FLTR_MODEB  (0x40)
0167 #define HD_ADPT_FLTR_EN     (0x80)
0168 #define HD_ADPT_FLTR_DI     (0x7F)
0169
0170 #define ADV7393_BRIGHTNESS_MAX  (63)
0171 #define ADV7393_BRIGHTNESS_MIN  (-64)
0172 #define ADV7393_BRIGHTNESS_DEF  (0)
0173 #define ADV7393_HUE_MAX     (127)
0174 #define ADV7393_HUE_MIN     (-128)
0175 #define ADV7393_HUE_DEF     (0)
0176 #define ADV7393_GAIN_MAX    (64)
0177 #define ADV7393_GAIN_MIN    (-64)
0178 #define ADV7393_GAIN_DEF    (0)
0179
0180 #endif