media/i2c/adv7343_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ADV7343 encoder related structure and register definitions
0004  *
0005  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
0006  */
0007
0008 #ifndef ADV7343_REGS_H
0009 #define ADV7343_REGS_H
0010
0011 struct adv7343_std_info {
0012     u32 standard_val3;
0013     u32 fsc_val;
0014     v4l2_std_id stdid;
0015 };
0016
0017 /* Register offset macros */
0018 #define ADV7343_POWER_MODE_REG      (0x00)
0019 #define ADV7343_MODE_SELECT_REG     (0x01)
0020 #define ADV7343_MODE_REG0       (0x02)
0021
0022 #define ADV7343_DAC2_OUTPUT_LEVEL   (0x0b)
0023
0024 #define ADV7343_SOFT_RESET      (0x17)
0025
0026 #define ADV7343_HD_MODE_REG1        (0x30)
0027 #define ADV7343_HD_MODE_REG2        (0x31)
0028 #define ADV7343_HD_MODE_REG3        (0x32)
0029 #define ADV7343_HD_MODE_REG4        (0x33)
0030 #define ADV7343_HD_MODE_REG5        (0x34)
0031 #define ADV7343_HD_MODE_REG6        (0x35)
0032
0033 #define ADV7343_HD_MODE_REG7        (0x39)
0034
0035 #define ADV7343_SD_MODE_REG1        (0x80)
0036 #define ADV7343_SD_MODE_REG2        (0x82)
0037 #define ADV7343_SD_MODE_REG3        (0x83)
0038 #define ADV7343_SD_MODE_REG4        (0x84)
0039 #define ADV7343_SD_MODE_REG5        (0x86)
0040 #define ADV7343_SD_MODE_REG6        (0x87)
0041 #define ADV7343_SD_MODE_REG7        (0x88)
0042 #define ADV7343_SD_MODE_REG8        (0x89)
0043
0044 #define ADV7343_FSC_REG0        (0x8C)
0045 #define ADV7343_FSC_REG1        (0x8D)
0046 #define ADV7343_FSC_REG2        (0x8E)
0047 #define ADV7343_FSC_REG3        (0x8F)
0048
0049 #define ADV7343_SD_CGMS_WSS0        (0x99)
0050
0051 #define ADV7343_SD_HUE_REG      (0xA0)
0052 #define ADV7343_SD_BRIGHTNESS_WSS   (0xA1)
0053
0054 /* Default values for the registers */
0055 #define ADV7343_POWER_MODE_REG_DEFAULT      (0x10)
0056 #define ADV7343_HD_MODE_REG1_DEFAULT        (0x3C)  /* Changed Default
0057                                720p EAVSAV code*/
0058 #define ADV7343_HD_MODE_REG2_DEFAULT        (0x01)  /* Changed Pixel data
0059                                valid */
0060 #define ADV7343_HD_MODE_REG3_DEFAULT        (0x00)  /* Color delay 0 clks */
0061 #define ADV7343_HD_MODE_REG4_DEFAULT        (0xE8)  /* Changed */
0062 #define ADV7343_HD_MODE_REG5_DEFAULT        (0x08)
0063 #define ADV7343_HD_MODE_REG6_DEFAULT        (0x00)
0064 #define ADV7343_HD_MODE_REG7_DEFAULT        (0x00)
0065 #define ADV7343_SD_MODE_REG8_DEFAULT        (0x00)
0066 #define ADV7343_SOFT_RESET_DEFAULT      (0x02)
0067 #define ADV7343_COMPOSITE_POWER_VALUE       (0x80)
0068 #define ADV7343_COMPONENT_POWER_VALUE       (0x1C)
0069 #define ADV7343_SVIDEO_POWER_VALUE      (0x60)
0070 #define ADV7343_SD_HUE_REG_DEFAULT      (127)
0071 #define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT   (0x03)
0072
0073 #define ADV7343_SD_CGMS_WSS0_DEFAULT        (0x10)
0074
0075 #define ADV7343_SD_MODE_REG1_DEFAULT        (0x00)
0076 #define ADV7343_SD_MODE_REG2_DEFAULT        (0xC9)
0077 #define ADV7343_SD_MODE_REG3_DEFAULT        (0x10)
0078 #define ADV7343_SD_MODE_REG4_DEFAULT        (0x01)
0079 #define ADV7343_SD_MODE_REG5_DEFAULT        (0x02)
0080 #define ADV7343_SD_MODE_REG6_DEFAULT        (0x0C)
0081 #define ADV7343_SD_MODE_REG7_DEFAULT        (0x04)
0082 #define ADV7343_SD_MODE_REG8_DEFAULT        (0x00)
0083
0084 /* Bit masks for Mode Select Register */
0085 #define INPUT_MODE_MASK         (0x70)
0086 #define SD_INPUT_MODE           (0x00)
0087 #define HD_720P_INPUT_MODE      (0x10)
0088 #define HD_1080I_INPUT_MODE     (0x10)
0089
0090 /* Bit masks for Mode Register 0 */
0091 #define TEST_PATTERN_BLACK_BAR_EN   (0x04)
0092 #define YUV_OUTPUT_SELECT       (0x20)
0093 #define RGB_OUTPUT_SELECT       (0xDF)
0094
0095 /* Bit masks for DAC output levels */
0096 #define DAC_OUTPUT_LEVEL_MASK       (0xFF)
0097
0098 /* Bit masks for soft reset register */
0099 #define SOFT_RESET          (0x02)
0100
0101 /* Bit masks for HD Mode Register 1 */
0102 #define OUTPUT_STD_MASK     (0x03)
0103 #define OUTPUT_STD_SHIFT    (0)
0104 #define OUTPUT_STD_EIA0_2   (0x00)
0105 #define OUTPUT_STD_EIA0_1   (0x01)
0106 #define OUTPUT_STD_FULL     (0x02)
0107 #define EMBEDDED_SYNC       (0x04)
0108 #define EXTERNAL_SYNC       (0xFB)
0109 #define STD_MODE_SHIFT      (3)
0110 #define STD_MODE_MASK       (0x1F)
0111 #define STD_MODE_720P       (0x05)
0112 #define STD_MODE_720P_25    (0x08)
0113 #define STD_MODE_720P_30    (0x07)
0114 #define STD_MODE_720P_50    (0x06)
0115 #define STD_MODE_1080I      (0x0D)
0116 #define STD_MODE_1080I_25fps    (0x0E)
0117 #define STD_MODE_1080P_24   (0x12)
0118 #define STD_MODE_1080P_25   (0x10)
0119 #define STD_MODE_1080P_30   (0x0F)
0120 #define STD_MODE_525P       (0x00)
0121 #define STD_MODE_625P       (0x03)
0122
0123 /* Bit masks for SD Mode Register 1 */
0124 #define SD_STD_MASK     (0x03)
0125 #define SD_STD_NTSC     (0x00)
0126 #define SD_STD_PAL_BDGHI    (0x01)
0127 #define SD_STD_PAL_M        (0x02)
0128 #define SD_STD_PAL_N        (0x03)
0129 #define SD_LUMA_FLTR_MASK   (0x7)
0130 #define SD_LUMA_FLTR_SHIFT  (0x2)
0131 #define SD_CHROMA_FLTR_MASK (0x7)
0132 #define SD_CHROMA_FLTR_SHIFT    (0x5)
0133
0134 /* Bit masks for SD Mode Register 2 */
0135 #define SD_PBPR_SSAF_EN     (0x01)
0136 #define SD_PBPR_SSAF_DI     (0xFE)
0137 #define SD_DAC_1_DI     (0xFD)
0138 #define SD_DAC_2_DI     (0xFB)
0139 #define SD_PEDESTAL_EN      (0x08)
0140 #define SD_PEDESTAL_DI      (0xF7)
0141 #define SD_SQUARE_PIXEL_EN  (0x10)
0142 #define SD_SQUARE_PIXEL_DI  (0xEF)
0143 #define SD_PIXEL_DATA_VALID (0x40)
0144 #define SD_ACTIVE_EDGE_EN   (0x80)
0145 #define SD_ACTIVE_EDGE_DI   (0x7F)
0146
0147 /* Bit masks for HD Mode Register 6 */
0148 #define HD_RGB_INPUT_EN     (0x02)
0149 #define HD_RGB_INPUT_DI     (0xFD)
0150 #define HD_PBPR_SYNC_EN     (0x04)
0151 #define HD_PBPR_SYNC_DI     (0xFB)
0152 #define HD_DAC_SWAP_EN      (0x08)
0153 #define HD_DAC_SWAP_DI      (0xF7)
0154 #define HD_GAMMA_CURVE_A    (0xEF)
0155 #define HD_GAMMA_CURVE_B    (0x10)
0156 #define HD_GAMMA_EN     (0x20)
0157 #define HD_GAMMA_DI     (0xDF)
0158 #define HD_ADPT_FLTR_MODEB  (0x40)
0159 #define HD_ADPT_FLTR_MODEA  (0xBF)
0160 #define HD_ADPT_FLTR_EN     (0x80)
0161 #define HD_ADPT_FLTR_DI     (0x7F)
0162
0163 #define ADV7343_BRIGHTNESS_MAX  (127)
0164 #define ADV7343_BRIGHTNESS_MIN  (0)
0165 #define ADV7343_BRIGHTNESS_DEF  (3)
0166 #define ADV7343_HUE_MAX     (255)
0167 #define ADV7343_HUE_MIN     (0)
0168 #define ADV7343_HUE_DEF     (127)
0169 #define ADV7343_GAIN_MAX    (64)
0170 #define ADV7343_GAIN_MIN    (-64)
0171 #define ADV7343_GAIN_DEF    (0)
0172
0173 #endif