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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * adv7183.c Analog Devices ADV7183 video decoder driver
0004  *
0005  * Copyright (c) 2011 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/delay.h>
0009 #include <linux/errno.h>
0010 #include <linux/gpio/consumer.h>
0011 #include <linux/i2c.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/slab.h>
0015 #include <linux/types.h>
0016 #include <linux/videodev2.h>
0017 
0018 #include <media/i2c/adv7183.h>
0019 #include <media/v4l2-ctrls.h>
0020 #include <media/v4l2-device.h>
0021 
0022 #include "adv7183_regs.h"
0023 
0024 struct adv7183 {
0025     struct v4l2_subdev sd;
0026     struct v4l2_ctrl_handler hdl;
0027 
0028     v4l2_std_id std; /* Current set standard */
0029     u32 input;
0030     u32 output;
0031     struct gpio_desc *reset_pin;
0032     struct gpio_desc *oe_pin;
0033     struct v4l2_mbus_framefmt fmt;
0034 };
0035 
0036 /* EXAMPLES USING 27 MHz CLOCK
0037  * Mode 1 CVBS Input (Composite Video on AIN5)
0038  * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
0039  */
0040 static const unsigned char adv7183_init_regs[] = {
0041     ADV7183_IN_CTRL, 0x04,           /* CVBS input on AIN5 */
0042     ADV7183_DIGI_CLAMP_CTRL_1, 0x00, /* Slow down digital clamps */
0043     ADV7183_SHAP_FILT_CTRL, 0x41,    /* Set CSFM to SH1 */
0044     ADV7183_ADC_CTRL, 0x16,          /* Power down ADC 1 and ADC 2 */
0045     ADV7183_CTI_DNR_CTRL_4, 0x04,    /* Set DNR threshold to 4 for flat response */
0046     /* ADI recommended programming sequence */
0047     ADV7183_ADI_CTRL, 0x80,
0048     ADV7183_CTI_DNR_CTRL_4, 0x20,
0049     0x52, 0x18,
0050     0x58, 0xED,
0051     0x77, 0xC5,
0052     0x7C, 0x93,
0053     0x7D, 0x00,
0054     0xD0, 0x48,
0055     0xD5, 0xA0,
0056     0xD7, 0xEA,
0057     ADV7183_SD_SATURATION_CR, 0x3E,
0058     ADV7183_PAL_V_END, 0x3E,
0059     ADV7183_PAL_F_TOGGLE, 0x0F,
0060     ADV7183_ADI_CTRL, 0x00,
0061 };
0062 
0063 static inline struct adv7183 *to_adv7183(struct v4l2_subdev *sd)
0064 {
0065     return container_of(sd, struct adv7183, sd);
0066 }
0067 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
0068 {
0069     return &container_of(ctrl->handler, struct adv7183, hdl)->sd;
0070 }
0071 
0072 static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg)
0073 {
0074     struct i2c_client *client = v4l2_get_subdevdata(sd);
0075 
0076     return i2c_smbus_read_byte_data(client, reg);
0077 }
0078 
0079 static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg,
0080                 unsigned char value)
0081 {
0082     struct i2c_client *client = v4l2_get_subdevdata(sd);
0083 
0084     return i2c_smbus_write_byte_data(client, reg, value);
0085 }
0086 
0087 static int adv7183_writeregs(struct v4l2_subdev *sd,
0088         const unsigned char *regs, unsigned int num)
0089 {
0090     unsigned char reg, data;
0091     unsigned int cnt = 0;
0092 
0093     if (num & 0x1) {
0094         v4l2_err(sd, "invalid regs array\n");
0095         return -1;
0096     }
0097 
0098     while (cnt < num) {
0099         reg = *regs++;
0100         data = *regs++;
0101         cnt += 2;
0102 
0103         adv7183_write(sd, reg, data);
0104     }
0105     return 0;
0106 }
0107 
0108 static int adv7183_log_status(struct v4l2_subdev *sd)
0109 {
0110     struct adv7183 *decoder = to_adv7183(sd);
0111 
0112     v4l2_info(sd, "adv7183: Input control = 0x%02x\n",
0113             adv7183_read(sd, ADV7183_IN_CTRL));
0114     v4l2_info(sd, "adv7183: Video selection = 0x%02x\n",
0115             adv7183_read(sd, ADV7183_VD_SEL));
0116     v4l2_info(sd, "adv7183: Output control = 0x%02x\n",
0117             adv7183_read(sd, ADV7183_OUT_CTRL));
0118     v4l2_info(sd, "adv7183: Extended output control = 0x%02x\n",
0119             adv7183_read(sd, ADV7183_EXT_OUT_CTRL));
0120     v4l2_info(sd, "adv7183: Autodetect enable = 0x%02x\n",
0121             adv7183_read(sd, ADV7183_AUTO_DET_EN));
0122     v4l2_info(sd, "adv7183: Contrast = 0x%02x\n",
0123             adv7183_read(sd, ADV7183_CONTRAST));
0124     v4l2_info(sd, "adv7183: Brightness = 0x%02x\n",
0125             adv7183_read(sd, ADV7183_BRIGHTNESS));
0126     v4l2_info(sd, "adv7183: Hue = 0x%02x\n",
0127             adv7183_read(sd, ADV7183_HUE));
0128     v4l2_info(sd, "adv7183: Default value Y = 0x%02x\n",
0129             adv7183_read(sd, ADV7183_DEF_Y));
0130     v4l2_info(sd, "adv7183: Default value C = 0x%02x\n",
0131             adv7183_read(sd, ADV7183_DEF_C));
0132     v4l2_info(sd, "adv7183: ADI control = 0x%02x\n",
0133             adv7183_read(sd, ADV7183_ADI_CTRL));
0134     v4l2_info(sd, "adv7183: Power Management = 0x%02x\n",
0135             adv7183_read(sd, ADV7183_POW_MANAGE));
0136     v4l2_info(sd, "adv7183: Status 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
0137             adv7183_read(sd, ADV7183_STATUS_1),
0138             adv7183_read(sd, ADV7183_STATUS_2),
0139             adv7183_read(sd, ADV7183_STATUS_3));
0140     v4l2_info(sd, "adv7183: Ident = 0x%02x\n",
0141             adv7183_read(sd, ADV7183_IDENT));
0142     v4l2_info(sd, "adv7183: Analog clamp control = 0x%02x\n",
0143             adv7183_read(sd, ADV7183_ANAL_CLAMP_CTRL));
0144     v4l2_info(sd, "adv7183: Digital clamp control 1 = 0x%02x\n",
0145             adv7183_read(sd, ADV7183_DIGI_CLAMP_CTRL_1));
0146     v4l2_info(sd, "adv7183: Shaping filter control 1 and 2 = 0x%02x 0x%02x\n",
0147             adv7183_read(sd, ADV7183_SHAP_FILT_CTRL),
0148             adv7183_read(sd, ADV7183_SHAP_FILT_CTRL_2));
0149     v4l2_info(sd, "adv7183: Comb filter control = 0x%02x\n",
0150             adv7183_read(sd, ADV7183_COMB_FILT_CTRL));
0151     v4l2_info(sd, "adv7183: ADI control 2 = 0x%02x\n",
0152             adv7183_read(sd, ADV7183_ADI_CTRL_2));
0153     v4l2_info(sd, "adv7183: Pixel delay control = 0x%02x\n",
0154             adv7183_read(sd, ADV7183_PIX_DELAY_CTRL));
0155     v4l2_info(sd, "adv7183: Misc gain control = 0x%02x\n",
0156             adv7183_read(sd, ADV7183_MISC_GAIN_CTRL));
0157     v4l2_info(sd, "adv7183: AGC mode control = 0x%02x\n",
0158             adv7183_read(sd, ADV7183_AGC_MODE_CTRL));
0159     v4l2_info(sd, "adv7183: Chroma gain control 1 and 2 = 0x%02x 0x%02x\n",
0160             adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_1),
0161             adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_2));
0162     v4l2_info(sd, "adv7183: Luma gain control 1 and 2 = 0x%02x 0x%02x\n",
0163             adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_1),
0164             adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_2));
0165     v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
0166             adv7183_read(sd, ADV7183_VS_FIELD_CTRL_1),
0167             adv7183_read(sd, ADV7183_VS_FIELD_CTRL_2),
0168             adv7183_read(sd, ADV7183_VS_FIELD_CTRL_3));
0169     v4l2_info(sd, "adv7183: Hsync position control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
0170             adv7183_read(sd, ADV7183_HS_POS_CTRL_1),
0171             adv7183_read(sd, ADV7183_HS_POS_CTRL_2),
0172             adv7183_read(sd, ADV7183_HS_POS_CTRL_3));
0173     v4l2_info(sd, "adv7183: Polarity = 0x%02x\n",
0174             adv7183_read(sd, ADV7183_POLARITY));
0175     v4l2_info(sd, "adv7183: ADC control = 0x%02x\n",
0176             adv7183_read(sd, ADV7183_ADC_CTRL));
0177     v4l2_info(sd, "adv7183: SD offset Cb and Cr = 0x%02x 0x%02x\n",
0178             adv7183_read(sd, ADV7183_SD_OFFSET_CB),
0179             adv7183_read(sd, ADV7183_SD_OFFSET_CR));
0180     v4l2_info(sd, "adv7183: SD saturation Cb and Cr = 0x%02x 0x%02x\n",
0181             adv7183_read(sd, ADV7183_SD_SATURATION_CB),
0182             adv7183_read(sd, ADV7183_SD_SATURATION_CR));
0183     v4l2_info(sd, "adv7183: Drive strength = 0x%02x\n",
0184             adv7183_read(sd, ADV7183_DRIVE_STR));
0185     v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name);
0186     return 0;
0187 }
0188 
0189 static int adv7183_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
0190 {
0191     struct adv7183 *decoder = to_adv7183(sd);
0192 
0193     *std = decoder->std;
0194     return 0;
0195 }
0196 
0197 static int adv7183_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
0198 {
0199     struct adv7183 *decoder = to_adv7183(sd);
0200     int reg;
0201 
0202     reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
0203     if (std == V4L2_STD_PAL_60)
0204         reg |= 0x60;
0205     else if (std == V4L2_STD_NTSC_443)
0206         reg |= 0x70;
0207     else if (std == V4L2_STD_PAL_N)
0208         reg |= 0x90;
0209     else if (std == V4L2_STD_PAL_M)
0210         reg |= 0xA0;
0211     else if (std == V4L2_STD_PAL_Nc)
0212         reg |= 0xC0;
0213     else if (std & V4L2_STD_PAL)
0214         reg |= 0x80;
0215     else if (std & V4L2_STD_NTSC)
0216         reg |= 0x50;
0217     else if (std & V4L2_STD_SECAM)
0218         reg |= 0xE0;
0219     else
0220         return -EINVAL;
0221     adv7183_write(sd, ADV7183_IN_CTRL, reg);
0222 
0223     decoder->std = std;
0224 
0225     return 0;
0226 }
0227 
0228 static int adv7183_reset(struct v4l2_subdev *sd, u32 val)
0229 {
0230     int reg;
0231 
0232     reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80;
0233     adv7183_write(sd, ADV7183_POW_MANAGE, reg);
0234     /* wait 5ms before any further i2c writes are performed */
0235     usleep_range(5000, 10000);
0236     return 0;
0237 }
0238 
0239 static int adv7183_s_routing(struct v4l2_subdev *sd,
0240                 u32 input, u32 output, u32 config)
0241 {
0242     struct adv7183 *decoder = to_adv7183(sd);
0243     int reg;
0244 
0245     if ((input > ADV7183_COMPONENT1) || (output > ADV7183_16BIT_OUT))
0246         return -EINVAL;
0247 
0248     if (input != decoder->input) {
0249         decoder->input = input;
0250         reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0;
0251         switch (input) {
0252         case ADV7183_COMPOSITE1:
0253             reg |= 0x1;
0254             break;
0255         case ADV7183_COMPOSITE2:
0256             reg |= 0x2;
0257             break;
0258         case ADV7183_COMPOSITE3:
0259             reg |= 0x3;
0260             break;
0261         case ADV7183_COMPOSITE4:
0262             reg |= 0x4;
0263             break;
0264         case ADV7183_COMPOSITE5:
0265             reg |= 0x5;
0266             break;
0267         case ADV7183_COMPOSITE6:
0268             reg |= 0xB;
0269             break;
0270         case ADV7183_COMPOSITE7:
0271             reg |= 0xC;
0272             break;
0273         case ADV7183_COMPOSITE8:
0274             reg |= 0xD;
0275             break;
0276         case ADV7183_COMPOSITE9:
0277             reg |= 0xE;
0278             break;
0279         case ADV7183_COMPOSITE10:
0280             reg |= 0xF;
0281             break;
0282         case ADV7183_SVIDEO0:
0283             reg |= 0x6;
0284             break;
0285         case ADV7183_SVIDEO1:
0286             reg |= 0x7;
0287             break;
0288         case ADV7183_SVIDEO2:
0289             reg |= 0x8;
0290             break;
0291         case ADV7183_COMPONENT0:
0292             reg |= 0x9;
0293             break;
0294         case ADV7183_COMPONENT1:
0295             reg |= 0xA;
0296             break;
0297         default:
0298             break;
0299         }
0300         adv7183_write(sd, ADV7183_IN_CTRL, reg);
0301     }
0302 
0303     if (output != decoder->output) {
0304         decoder->output = output;
0305         reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0;
0306         switch (output) {
0307         case ADV7183_16BIT_OUT:
0308             reg |= 0x9;
0309             break;
0310         default:
0311             reg |= 0xC;
0312             break;
0313         }
0314         adv7183_write(sd, ADV7183_OUT_CTRL, reg);
0315     }
0316 
0317     return 0;
0318 }
0319 
0320 static int adv7183_s_ctrl(struct v4l2_ctrl *ctrl)
0321 {
0322     struct v4l2_subdev *sd = to_sd(ctrl);
0323     int val = ctrl->val;
0324 
0325     switch (ctrl->id) {
0326     case V4L2_CID_BRIGHTNESS:
0327         if (val < 0)
0328             val = 127 - val;
0329         adv7183_write(sd, ADV7183_BRIGHTNESS, val);
0330         break;
0331     case V4L2_CID_CONTRAST:
0332         adv7183_write(sd, ADV7183_CONTRAST, val);
0333         break;
0334     case V4L2_CID_SATURATION:
0335         adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8);
0336         adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF));
0337         break;
0338     case V4L2_CID_HUE:
0339         adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8);
0340         adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF));
0341         break;
0342     default:
0343         return -EINVAL;
0344     }
0345 
0346     return 0;
0347 }
0348 
0349 static int adv7183_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
0350 {
0351     struct adv7183 *decoder = to_adv7183(sd);
0352     int reg;
0353 
0354     /* enable autodetection block */
0355     reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
0356     adv7183_write(sd, ADV7183_IN_CTRL, reg);
0357 
0358     /* wait autodetection switch */
0359     mdelay(10);
0360 
0361     /* get autodetection result */
0362     reg = adv7183_read(sd, ADV7183_STATUS_1);
0363     switch ((reg >> 0x4) & 0x7) {
0364     case 0:
0365         *std &= V4L2_STD_NTSC;
0366         break;
0367     case 1:
0368         *std &= V4L2_STD_NTSC_443;
0369         break;
0370     case 2:
0371         *std &= V4L2_STD_PAL_M;
0372         break;
0373     case 3:
0374         *std &= V4L2_STD_PAL_60;
0375         break;
0376     case 4:
0377         *std &= V4L2_STD_PAL;
0378         break;
0379     case 5:
0380         *std &= V4L2_STD_SECAM;
0381         break;
0382     case 6:
0383         *std &= V4L2_STD_PAL_Nc;
0384         break;
0385     case 7:
0386         *std &= V4L2_STD_SECAM;
0387         break;
0388     default:
0389         *std = V4L2_STD_UNKNOWN;
0390         break;
0391     }
0392 
0393     /* after std detection, write back user set std */
0394     adv7183_s_std(sd, decoder->std);
0395     return 0;
0396 }
0397 
0398 static int adv7183_g_input_status(struct v4l2_subdev *sd, u32 *status)
0399 {
0400     int reg;
0401 
0402     *status = V4L2_IN_ST_NO_SIGNAL;
0403     reg = adv7183_read(sd, ADV7183_STATUS_1);
0404     if (reg < 0)
0405         return reg;
0406     if (reg & 0x1)
0407         *status = 0;
0408     return 0;
0409 }
0410 
0411 static int adv7183_enum_mbus_code(struct v4l2_subdev *sd,
0412         struct v4l2_subdev_state *sd_state,
0413         struct v4l2_subdev_mbus_code_enum *code)
0414 {
0415     if (code->pad || code->index > 0)
0416         return -EINVAL;
0417 
0418     code->code = MEDIA_BUS_FMT_UYVY8_2X8;
0419     return 0;
0420 }
0421 
0422 static int adv7183_set_fmt(struct v4l2_subdev *sd,
0423         struct v4l2_subdev_state *sd_state,
0424         struct v4l2_subdev_format *format)
0425 {
0426     struct adv7183 *decoder = to_adv7183(sd);
0427     struct v4l2_mbus_framefmt *fmt = &format->format;
0428 
0429     if (format->pad)
0430         return -EINVAL;
0431 
0432     fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
0433     fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
0434     if (decoder->std & V4L2_STD_525_60) {
0435         fmt->field = V4L2_FIELD_SEQ_TB;
0436         fmt->width = 720;
0437         fmt->height = 480;
0438     } else {
0439         fmt->field = V4L2_FIELD_SEQ_BT;
0440         fmt->width = 720;
0441         fmt->height = 576;
0442     }
0443     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
0444         decoder->fmt = *fmt;
0445     else
0446         sd_state->pads->try_fmt = *fmt;
0447     return 0;
0448 }
0449 
0450 static int adv7183_get_fmt(struct v4l2_subdev *sd,
0451         struct v4l2_subdev_state *sd_state,
0452         struct v4l2_subdev_format *format)
0453 {
0454     struct adv7183 *decoder = to_adv7183(sd);
0455 
0456     if (format->pad)
0457         return -EINVAL;
0458 
0459     format->format = decoder->fmt;
0460     return 0;
0461 }
0462 
0463 static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
0464 {
0465     struct adv7183 *decoder = to_adv7183(sd);
0466 
0467     if (enable)
0468         gpiod_set_value(decoder->oe_pin, 1);
0469     else
0470         gpiod_set_value(decoder->oe_pin, 0);
0471     udelay(1);
0472     return 0;
0473 }
0474 
0475 #ifdef CONFIG_VIDEO_ADV_DEBUG
0476 static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
0477 {
0478     reg->val = adv7183_read(sd, reg->reg & 0xff);
0479     reg->size = 1;
0480     return 0;
0481 }
0482 
0483 static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
0484 {
0485     adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff);
0486     return 0;
0487 }
0488 #endif
0489 
0490 static const struct v4l2_ctrl_ops adv7183_ctrl_ops = {
0491     .s_ctrl = adv7183_s_ctrl,
0492 };
0493 
0494 static const struct v4l2_subdev_core_ops adv7183_core_ops = {
0495     .log_status = adv7183_log_status,
0496     .reset = adv7183_reset,
0497 #ifdef CONFIG_VIDEO_ADV_DEBUG
0498     .g_register = adv7183_g_register,
0499     .s_register = adv7183_s_register,
0500 #endif
0501 };
0502 
0503 static const struct v4l2_subdev_video_ops adv7183_video_ops = {
0504     .g_std = adv7183_g_std,
0505     .s_std = adv7183_s_std,
0506     .s_routing = adv7183_s_routing,
0507     .querystd = adv7183_querystd,
0508     .g_input_status = adv7183_g_input_status,
0509     .s_stream = adv7183_s_stream,
0510 };
0511 
0512 static const struct v4l2_subdev_pad_ops adv7183_pad_ops = {
0513     .enum_mbus_code = adv7183_enum_mbus_code,
0514     .get_fmt = adv7183_get_fmt,
0515     .set_fmt = adv7183_set_fmt,
0516 };
0517 
0518 static const struct v4l2_subdev_ops adv7183_ops = {
0519     .core = &adv7183_core_ops,
0520     .video = &adv7183_video_ops,
0521     .pad = &adv7183_pad_ops,
0522 };
0523 
0524 static int adv7183_probe(struct i2c_client *client,
0525             const struct i2c_device_id *id)
0526 {
0527     struct adv7183 *decoder;
0528     struct v4l2_subdev *sd;
0529     struct v4l2_ctrl_handler *hdl;
0530     int ret;
0531     struct v4l2_subdev_format fmt = {
0532         .which = V4L2_SUBDEV_FORMAT_ACTIVE,
0533     };
0534 
0535     /* Check if the adapter supports the needed features */
0536     if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
0537         return -EIO;
0538 
0539     v4l_info(client, "chip found @ 0x%02x (%s)\n",
0540             client->addr << 1, client->adapter->name);
0541 
0542     decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
0543     if (decoder == NULL)
0544         return -ENOMEM;
0545 
0546     /*
0547      * Requesting high will assert reset, the line should be
0548      * flagged as active low in descriptor table or machine description.
0549      */
0550     decoder->reset_pin = devm_gpiod_get(&client->dev, "reset",
0551                         GPIOD_OUT_HIGH);
0552     if (IS_ERR(decoder->reset_pin))
0553         return PTR_ERR(decoder->reset_pin);
0554     gpiod_set_consumer_name(decoder->reset_pin, "ADV7183 Reset");
0555     /*
0556      * Requesting low will start with output disabled, the line should be
0557      * flagged as active low in descriptor table or machine description.
0558      */
0559     decoder->oe_pin = devm_gpiod_get(&client->dev, "oe",
0560                      GPIOD_OUT_LOW);
0561     if (IS_ERR(decoder->oe_pin))
0562         return PTR_ERR(decoder->oe_pin);
0563     gpiod_set_consumer_name(decoder->reset_pin, "ADV7183 Output Enable");
0564 
0565     sd = &decoder->sd;
0566     v4l2_i2c_subdev_init(sd, client, &adv7183_ops);
0567 
0568     hdl = &decoder->hdl;
0569     v4l2_ctrl_handler_init(hdl, 4);
0570     v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
0571             V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
0572     v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
0573             V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x80);
0574     v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
0575             V4L2_CID_SATURATION, 0, 0xFFFF, 1, 0x8080);
0576     v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
0577             V4L2_CID_HUE, 0, 0xFFFF, 1, 0x8080);
0578     /* hook the control handler into the driver */
0579     sd->ctrl_handler = hdl;
0580     if (hdl->error) {
0581         ret = hdl->error;
0582 
0583         v4l2_ctrl_handler_free(hdl);
0584         return ret;
0585     }
0586 
0587     /* v4l2 doesn't support an autodetect standard, pick PAL as default */
0588     decoder->std = V4L2_STD_PAL;
0589     decoder->input = ADV7183_COMPOSITE4;
0590     decoder->output = ADV7183_8BIT_OUT;
0591 
0592     /* reset chip */
0593     /* reset pulse width at least 5ms */
0594     mdelay(10);
0595     /* De-assert reset line (descriptor tagged active low) */
0596     gpiod_set_value(decoder->reset_pin, 0);
0597     /* wait 5ms before any further i2c writes are performed */
0598     mdelay(5);
0599 
0600     adv7183_writeregs(sd, adv7183_init_regs, ARRAY_SIZE(adv7183_init_regs));
0601     adv7183_s_std(sd, decoder->std);
0602     fmt.format.width = 720;
0603     fmt.format.height = 576;
0604     adv7183_set_fmt(sd, NULL, &fmt);
0605 
0606     /* initialize the hardware to the default control values */
0607     ret = v4l2_ctrl_handler_setup(hdl);
0608     if (ret) {
0609         v4l2_ctrl_handler_free(hdl);
0610         return ret;
0611     }
0612 
0613     return 0;
0614 }
0615 
0616 static int adv7183_remove(struct i2c_client *client)
0617 {
0618     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0619 
0620     v4l2_device_unregister_subdev(sd);
0621     v4l2_ctrl_handler_free(sd->ctrl_handler);
0622     return 0;
0623 }
0624 
0625 static const struct i2c_device_id adv7183_id[] = {
0626     {"adv7183", 0},
0627     {},
0628 };
0629 
0630 MODULE_DEVICE_TABLE(i2c, adv7183_id);
0631 
0632 static struct i2c_driver adv7183_driver = {
0633     .driver = {
0634         .name   = "adv7183",
0635     },
0636     .probe          = adv7183_probe,
0637     .remove         = adv7183_remove,
0638     .id_table       = adv7183_id,
0639 };
0640 
0641 module_i2c_driver(adv7183_driver);
0642 
0643 MODULE_DESCRIPTION("Analog Devices ADV7183 video decoder driver");
0644 MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
0645 MODULE_LICENSE("GPL v2");
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